CN107170715B - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN107170715B CN107170715B CN201610397594.3A CN201610397594A CN107170715B CN 107170715 B CN107170715 B CN 107170715B CN 201610397594 A CN201610397594 A CN 201610397594A CN 107170715 B CN107170715 B CN 107170715B
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- dielectric layer
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- opening
- semiconductor package
- sheet metal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000004806 packaging method and process Methods 0.000 title abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000000084 colloidal system Substances 0.000 claims abstract description 27
- 238000012856 packing Methods 0.000 claims description 22
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 239000008393 encapsulating agent Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 72
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000012792 core layer Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000002905 metal composite material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- -1 ni au Chemical compound 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a metal sheet, a dielectric layer, a patterned circuit layer, a first chip and a packaging colloid. The dielectric layer covers the metal sheet. The dielectric layer has a first surface and a second surface opposite to each other, at least one first opening on the first surface, and a second opening on the second surface. The metal sheet is positioned in the second opening and is respectively exposed on the first surface and the second surface. The patterned circuit layer is configured on the second surface. The first chip is disposed on the metal sheet, wherein the first chip is located in the second opening and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and covers the first chip and the patterned circuit layer. A method for fabricating the semiconductor package structure is also provided. The semiconductor packaging structure provided by the invention is thinner in whole thickness and has a good heat dissipation effect.
Description
Technical field
The present invention relates to a kind of encapsulating structure and preparation method thereof more particularly to a kind of semiconductor package and its production
Method.
Background technique
In semiconductor industry, the production of integrated circuit (IC) can be divided mainly into three phases: the design of integrated circuit, collection
At the production of circuit and the encapsulation of integrated circuit.After the production of integrated circuits of wafer is completed, the active surface of wafer is configured
There are multiple connection pads.Finally, carrier (carrier) can be electrically connected at by connection pad by cutting resulting bare chip by wafer.It is logical
Chang Eryan, carrier can be lead frame (lead frame), substrate (substrate) or printed circuit board (printed
Circuit board), and chip can engage (wire bonding) or chip bonding (flip chip by routing
) etc. bonding modes are connected on carrier, so that the contact of the connection pad of chip and carrier is electrically connected, and then constitute core
Piece packaging body.
By taking package substrate as an example, there is core layer mostly, therefore thickness is thicker and higher cost.On the other hand, to make core
Piece packaging body has good radiating efficiency, and the existing practice is cooling fin to be attached to chip, and make to be coated on chip mostly
Packing colloid further coat cooling fin.Or be cooling fin is attached at packing colloid, and by be directly connected to or
The mode connect in succession makes cooling fin thermal coupling be connected to chip.Therefore, the integral thickness of chip packing-body is difficult to decrease.
Summary of the invention
The present invention provides a kind of production method of semiconductor package, and it is relatively thin and have to make to obtain integral thickness
The semiconductor package of good heat dissipation effect.
The present invention provides a kind of semiconductor package, and integral thickness is relatively thin and has good heat dissipation effect.
A kind of production method that the present invention proposes semiconductor package comprising following steps.Support plate is provided.Configuration gold
Belong to piece on support plate.Dielectric layer is formed on support plate, and dielectric layer is made to coat sheet metal.Dielectric layer has opposite first surface
With second surface, and dielectric layer is connected with first surface with support plate.Patterned line layer is formed in the second surface of dielectric layer
On.Support plate is removed, so that sheet metal is exposed to the first surface of dielectric layer.Part of dielectric layer is removed, is located at the first table to be formed
On face at least one first opening and on second surface second opening, wherein first opening expose it is partially patterned
Line layer, and the second opening exposes sheet metal.Configure the first chip on sheet metal, make the first chip be located at second opening
It is interior, and it is electrically connected patterned line layer.Packing colloid is formed on the second surface of dielectric layer, and makes packing colloid covering the
One chip and patterned line layer.
In one embodiment of this invention, the production method of above-mentioned semiconductor package further includes being formed outside at least one
In portion's connection terminal is open in first, and external connection terminals are electrically connected patterned line layer.
In one embodiment of this invention, the production method of above-mentioned semiconductor package further includes forming packaging plastic
Body configures the second chip in the top of the second surface of dielectric layer before on the second surface of dielectric layer, and makes the second chip
It is electrically connected at patterned line layer.
In one embodiment of this invention, the production method of above-mentioned semiconductor package further includes covering packing colloid
The second chip of lid.
In one embodiment of this invention, above-mentioned packing colloid fills up the second opening.
The present invention proposes a kind of semiconductor package comprising sheet metal, dielectric layer, patterned line layer, the first core
Piece and packing colloid.Dielectric layer coats sheet metal, and dielectric layer has opposite first surface and second surface, is located at the
At least one first opening on one surface and the second opening on second surface.Sheet metal is located in the second opening, and
It is respectively exposed to the first surface and second surface of dielectric layer.Patterned line layer is configured on the second surface of dielectric layer.The
One chip is configured on sheet metal, wherein the first chip is located in the second opening, and is electrically connected at patterned line layer.Encapsulation
Colloid is configured on the second surface of dielectric layer, and covers the first chip and patterned line layer.
In one embodiment of this invention, above-mentioned semiconductor package further includes an at least external connection terminals.Outside
Portion's connection terminal is configured in the first opening, and external connection terminals are electrically connected patterned line layer.
In one embodiment of this invention, above-mentioned semiconductor package further includes the second chip.The configuration of second chip
In the top of the second surface of dielectric layer, and it is electrically connected at patterned line layer.
In one embodiment of this invention, the second above-mentioned chip is packaged colloid and is covered.
In one embodiment of this invention, the bottom surface of above-mentioned sheet metal is flushed with the first surface of dielectric layer.
Based on above-mentioned, the resulting semiconductor package of production method production of semiconductor package through the invention
Without core layer, and each other, the chip Yu sheet metal of thermal coupling are all embedded in the opening of dielectric layer.On the other hand, sheet metal
A wherein surface for dielectric layer can be exposed to.Therefore, the integral thickness of semiconductor package of the invention can be reduced significantly,
And there is good heat dissipation effect simultaneously.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 to Fig. 8 is the diagrammatic cross-section of the production process of the semiconductor package of one embodiment of the invention；
Fig. 9 is the diagrammatic cross-section of the semiconductor package of another embodiment of the present invention.
Appended drawing reference:
10: support plate
100,100A: semiconductor package
110: sheet metal
111: bottom surface
120: dielectric layer
121: first surface
122: second surface
123: the first openings
124: the second openings
130: patterned line layer
140: the first chips
141: active surface
142: back surface
150: glue-line
160: conducting wire
170: packing colloid
180: external connection terminals
181: convex block
190: the second chips
191: active surface
Specific embodiment
Fig. 1 to Fig. 8 is the diagrammatic cross-section of the production process of the semiconductor package of one embodiment of the invention.It please refers to
Fig. 1, firstly, providing support plate 10.In the present embodiment, support plate 10 can be made of material with a higher rigidity, therefore be not easy stress and curved
Song deformation.With continued reference to FIG. 1, configuration sheet metal 110 is on support plate 10.Sheet metal 110 can directly be attached by its bottom surface 111
In on support plate 10, or pass through being temporarily fixed on support plate 10 on bottom surface 111 from shape glue film (not shown).Metal
The material of piece 110 can be copper, aluminium, silver or the good metal material of other thermal conductivity.
Then, referring to FIG. 2, for example, by using chemical vapour deposition technique (CVD) by conductor oxidate (such as titanium dioxide
Silicon) it is formed on support plate 10, and aforesaid semiconductor oxide is made to cover sheet metal 110, to form dielectric layer 120.In this implementation
In example, dielectric layer 120 has opposite first surface 121 and second surface 122, and wherein first surface 121 is connected with support plate 10
It connects, and is generally flushed with the bottom surface of sheet metal 110 111.Then, referring to FIG. 3, for example, by using sputter, printing, plating, nothing
The modes such as electricity plating, chemical vapor deposition or physical vapour deposition (PVD) (PVD) form patterned line layer 130 in dielectric layer 120
On second surface 122.At this point, dielectric layer 120 is between patterned line layer 130 and support plate 10.Then, referring to FIG. 4, moving
Except support plate 10, to expose the first surface 121 of dielectric layer 120 and the bottom surface 111 of sheet metal 110.It changes for an angle, gold
The bottom surface 111 for belonging to piece 110 is for example exposed to the first surface 121 of dielectric layer 120.It is noted that if sheet metal 110 is logical
Being temporarily fixed on support plate 10 on bottom surface 111 from shape glue film is crossed, then (figure is not from shape glue film when removing support plate 10
Show) it can be removed together.
Then, referring to FIG. 5, for example removing part of dielectric layer 120 by way of laser-induced thermal etching, it is located at first to be formed
At least one first 123 (schematically showing multiple) of opening on surface 121 and the second opening on second surface 122
124.When forming these first openings 123, it need to first make laser source alignment pattern line layer 130.Then, by laser beam projects
To the first surface 121 of dielectric layer 120, to be etched dielectric layer 120 until exposing patterned line layer 130, and with
Not undermining patterned line layer 130 is principle.On the other hand, in the opening of formation second 124, first laser source need to be made to metalloid
Piece 110.Then, by the second surface 122 of laser beam projects to dielectric layer 120, to be etched dielectric layer 120 until exposure
Sheet metal 110 out, and not undermine sheet metal 110 as principle.As shown in figure 5, the sectional area of the second opening 124 is, for example, to be less than
The surface area of sheet metal 110.In other embodiments, the sectional area of the second opening can be greater than or equal to the surface area of sheet metal,
Visual process requirement adjusts.
Then, referring to FIG. 6, the first chip 140 of configuration is on sheet metal 110, and so that the first chip 140 is located at second and open
In mouth 124.In the present embodiment, the active surface 141 of the first chip 140 can be exposed to the second surface 122 of dielectric layer 120,
In other words, the first chip 140 is fixed on sheet metal 110 with its back surface 142.In addition, the first chip 140 can pass through glue-line
150 (such as: heat-conducting glue) it sticks on sheet metal 110.Then, the engagement of conducting wire 160 is made to be located at the in such a way that routing engages
Connection pad (not shown) and patterned line layer 130 on the active surface 141 of one chip 140, so that the first chip 140 and pattern
Change line layer 130 to be electrically connected.Then, referring to FIG. 7, forming packing colloid 170 on the second surface 122 of dielectric layer 120,
And make first chip of the covering of packing colloid 170 140 and patterned line layer 130.On the other hand, packing colloid 170 can be further
The second opening 124 is filled up, to cover the part of the surface that sheet metal 110 is exposed to the second opening 124, and then fixes the first chip
140 in the second opening 124.Packing colloid 170 can be epoxy resin, with to avoid patterned line layer 130, the first chip 140
And conducting wire 160 is influenced by extraneous aqueous vapor or foreign matter.
Later, referring to FIG. 8, forming an at least external connection terminals 180 (schematically showing two) in the first opening
In 123.The quantity of these external connection terminals 180 is corresponding to the quantity of the first opening 123, and these external connection terminals 180
It is electrically connected patterned line layer 130.In the present embodiment, external connection terminals 180 are that part is embedded in the first opening 123
It is interior, and protruded compared with the first surface of dielectric layer 120 121, the present invention does not limit this.Typically, external connection terminal
Son 180 can be tin ball.So far, the production of semiconductor package 100 has been substantially completed.Not due to semiconductor package 100
With core layer, and each other, the first chip 140 with sheet metal 110 of thermal coupling are all embedded in the second opening 124 of dielectric layer 120
It is interior, therefore the integral thickness of semiconductor package 100 can be reduced significantly.On the other hand, due to the bottom surface of sheet metal 110
111 can be exposed to the first surface 121 of dielectric layer 120, therefore semiconductor package 100 can have good heat dissipation effect.
Other embodiments will be enumerated below using as explanation.It should be noted that, following embodiments continue to use aforementioned reality herein
The reference numerals and partial content of example are applied, wherein adopting the identical or approximate component that is denoted by the same reference numerals, and are omitted
The explanation of same technique content.Explanation about clipped can refer to previous embodiment, and following embodiment will not be repeated herein.
Fig. 9 is the diagrammatic cross-section of the semiconductor package of another embodiment of the present invention.Referring to FIG. 9, the present embodiment
Semiconductor package 100A production process substantially in the production process phase of the semiconductor package of above-described embodiment 100
Seemingly, difference between the two is: before being formed on second surface 122 of the packing colloid 170 in dielectric layer 120, this implementation
Regular meeting separately configures the second chip 190 in the top of the second surface 122 of dielectric layer 120, the active surface 191 of the second chip 190
Second surface 122 towards dielectric layer 120.Specifically, the present embodiment can make multiple convex blocks 181 by way of chip bonding
It is engaged between the active surface 191 and patterned line layer 130 of the second chip 190, so that the second chip 190 is electrically connected at
Patterned line layer 130.Convex block 181 can be plated bumps, electroless plating convex block, tie lines convex block, conducting polymer convex block or metal
Composite projection, and the material of convex block 181 can be selected from following group: copper, gold, silver, tin, indium, ni au, nickel/palladium/gold, copper/nickel/
Gold, copper/gold, aluminium and its alloy.On the other hand, when being formed on second surface 122 of the packing colloid 170 in dielectric layer 120, envelope
Dress colloid 170 can further cover the second chip 190 and these convex blocks 181.Therefore, it is packaged the figure that colloid 170 is covered
Case line layer 130, the first chip 140, conducting wire 160, convex block 181 and the second chip 190 are not easily susceptible to extraneous aqueous vapor or different
The influence of object.
In conclusion the production method of semiconductor package through the invention makes resulting semiconductor package
Without core layer, and each other, the chip Yu sheet metal of thermal coupling are all embedded in one of opening of dielectric layer.Another party
The external connection terminals that patterned line layer on face, with dielectric layer is electrically connected locally are embedded in other openings of dielectric layer
It is interior, and sheet metal can be exposed to a wherein surface for dielectric layer.Therefore, the integral thickness of semiconductor package of the invention can
It significantly reduces, and there is good heat dissipation effect simultaneously.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Middle those of ordinary skill, it is without departing from the spirit and scope of the present invention, therefore of the invention when can make a little change and retouching
Protection scope is subject to view appended claims confining spectrum.
Claims (10)
1. a kind of production method of semiconductor package characterized by comprising
Support plate is provided；
Sheet metal is configured on the support plate；
Dielectric layer is formed on the support plate, and the dielectric layer is made to coat the sheet metal, wherein the dielectric layer has phase
Pair first surface and second surface, and the dielectric layer is connected with the first surface with the support plate；
Patterned line layer is formed on the second surface of the dielectric layer；
The support plate is removed, so that the sheet metal is exposed to the first surface of the dielectric layer；
The part dielectric layer is removed, to form be located on the first surface at least one first opening and be located at described the
The second opening on two surfaces, wherein at least one first opening exposes the part patterned line layer, and described the
Two openings expose the sheet metal；
The first chip is configured in being located at first chip in second opening, and is electrically connected institute
State patterned line layer；And
Packing colloid is formed on the second surface of the dielectric layer, and the packing colloid is made to cover first chip
With the patterned line layer.
2. the production method of semiconductor package according to claim 1, which is characterized in that further include:
In a formation at least external connection terminals are open in described at least one first, and an at least external connection terminals are electrical
Connect the patterned line layer.
3. the production method of semiconductor package according to claim 1, which is characterized in that further include:
Before being formed on the second surface of the packing colloid in the dielectric layer, the second chip is configured in the dielectric
The top of the second surface of layer, and second chip is made to be electrically connected at the patterned line layer.
4. the production method of semiconductor package according to claim 3, which is characterized in that further include:
The packing colloid is set to cover second chip.
5. the production method of semiconductor package according to claim 1, which is characterized in that the packing colloid fills up
Second opening.
6. a kind of semiconductor package characterized by comprising
Sheet metal；
Dielectric layer coats the sheet metal, wherein the dielectric layer has opposite first surface and second surface, positioned at described
At least one first opening on first surface and the second opening on the second surface, wherein the sheet metal is located at
In second opening, and it is respectively exposed to the first surface and the second surface of the dielectric layer, wherein the gold
The bottom surface for belonging to piece is exposed to the first surface, and the bottom surface of the sheet metal is flushed with the first surface of the dielectric layer；
Patterned line layer is configured on the second surface of the dielectric layer, wherein at least one first opening exposure
The part patterned line layer；
First chip is configured on the sheet metal, wherein first chip is located in second opening, and is electrically connected
In the patterned line layer；And
Packing colloid is configured on the second surface of the dielectric layer, and covers first chip and the patterning
Line layer.
7. semiconductor package according to claim 6, which is characterized in that further include:
An at least external connection terminals are configured at least one first opening, and at least external connection terminals electricity
Property the connection patterned line layer.
8. semiconductor package according to claim 6, which is characterized in that further include:
Second chip, is configured at the top of the second surface of the dielectric layer, and is electrically connected at the patterned circuit
Layer.
9. semiconductor package according to claim 8, which is characterized in that second chip is by the packing colloid
It is covered.
10. semiconductor package according to claim 6, which is characterized in that the packing colloid fills up described second
Opening.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105107009 | 2016-03-08 | ||
| TW105107009A TWI596678B (en) | 2016-03-08 | 2016-03-08 | Semiconductor package structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107170715A CN107170715A (en) | 2017-09-15 |
| CN107170715B true CN107170715B (en) | 2019-08-27 |
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| CN201610397594.3A Active CN107170715B (en) | 2016-03-08 | 2016-06-07 | Semiconductor packaging structure and manufacturing method thereof |
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| TW (1) | TWI596678B (en) |
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| TWI720796B (en) * | 2020-01-21 | 2021-03-01 | 南茂科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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| CN101335217A (en) * | 2007-06-29 | 2008-12-31 | 矽品精密工业股份有限公司 | Semiconductor package and manufacturing method thereof |
| TW201248814A (en) * | 2011-05-24 | 2012-12-01 | Unimicron Technology Corp | Coreless package substrate and method of making same |
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| US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
| TW587317B (en) * | 2002-12-30 | 2004-05-11 | Via Tech Inc | Construction and manufacturing of a chip package |
| TWI290349B (en) * | 2005-12-30 | 2007-11-21 | Advanced Semiconductor Eng | Thermally enhanced coreless thin substrate with an embedded chip and method for manufacturing the same |
| US8237257B2 (en) * | 2008-09-25 | 2012-08-07 | King Dragon International Inc. | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
| TWI456715B (en) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | Chip package structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101335217A (en) * | 2007-06-29 | 2008-12-31 | 矽品精密工业股份有限公司 | Semiconductor package and manufacturing method thereof |
| TWI398933B (en) * | 2008-03-05 | 2013-06-11 | Advanced Optoelectronic Tech | Package structure of integrated circuit device and manufacturing method thereof |
| TW201248814A (en) * | 2011-05-24 | 2012-12-01 | Unimicron Technology Corp | Coreless package substrate and method of making same |
| CN103871998A (en) * | 2012-12-13 | 2014-06-18 | 珠海越亚封装基板技术股份有限公司 | Single Layer Coreless Substrate |
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| Publication number | Publication date |
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| TW201732962A (en) | 2017-09-16 |
| TWI596678B (en) | 2017-08-21 |
| CN107170715A (en) | 2017-09-15 |
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