CN106817258A - A kind of method and device chosen and verify PCIE link equalization parameters - Google Patents
A kind of method and device chosen and verify PCIE link equalization parameters Download PDFInfo
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- CN106817258A CN106817258A CN201710024897.5A CN201710024897A CN106817258A CN 106817258 A CN106817258 A CN 106817258A CN 201710024897 A CN201710024897 A CN 201710024897A CN 106817258 A CN106817258 A CN 106817258A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
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- General Physics & Mathematics (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The present invention relates to the communications field, disclose a kind of method and device chosen and verify PCIE link equalization parameters, method includes choosing the inclined parameter of multigroup drawing of PCIE links, inclined parameter round will be drawn to be written in the corresponding register of PCIE chip receiving terminals, receive the wrong parameter for drawing inclined parameter to be produced during operation, and record in error code register, Selection Center parameter judges the concentration degree of Center Parameter;Device includes that first chooses module, the inclined parameter of multigroup drawing for choosing PCIE links;Writing module, for inclined parameter round will to be drawn to be written in the corresponding register of PCIE chip receiving terminals;Logging modle, for receiving the wrong parameter for drawing inclined parameter to be produced during operation, and records in error code register;Second chooses module, for Selection Center parameter;Judge module, the concentration degree for judging Center Parameter.The effective decay for avoiding signal of the invention, improves the quality of signal transmission.
Description
Technical field
The present invention relates to the communications field, more particularly to a kind of method and dress chosen and verify PCIE link equalization parameters
Put.
Background technology
PCIE buses (quick peripheral component interconnection(Peripheral Component Interconnect
Express)) be widely used, the speed 5Gbps from speed 2.5Gbps to the PCIE2.0 of PCIE1.0 is again to PCIE3.0
Speed 8.0Gbps, transmission rate is more and more higher, to realize transmitting on original cheap PCB and connector
Also to solve the problems, such as that some are new, maximum of which problem is the loss of signal, in order to solve this problem, in PCIE1.0 and
Used in PCIE2.0 and postemphasised( De-emphasis)The transmitting terminal of technology, i.e. signal(TX)In sending signal to saltus step
Bit increases amplitude and sends, and so can partly compensate decay of the transmission line to radio-frequency component, relatively good so as to obtain
Eye pattern;And for PCIE3.0, because signal rate is higher, it is necessary to be postemphasised technology using 2 more complicated ranks.I.e.
In addition to saltus step bit increase amplitudes send the signal that postemphasises, amplitude is also increased in preceding 1 bit of saltus step bit
Send, this solves the problem of the transmitting terminal of PCIE3.08Gbps transmission rates, but pass through research and find, Jin Jin
Transmitting terminal is compensated to signal high frequency or not enough, specified in chip receiving terminal again in PCIE3.0 standards in this way(RX ends)Also
Equilibrium is done to signal( Equalization), that is, in chip internal one equalizing circuit of increase of chip receiving terminal, this
Individual equalizing circuit can raise the high fdrequency component in the signal for receiving, so as to the loss to circuit is further compensated,
Can consult a suitable parameter at link training phase transmission end and chip receiving terminal.Due to some chip strings and receive and dispatch equilibrium
Algorithm imperfection, if using adaptive mode fully according to PCIE3.0 protocol standard transmissions end, chip receiving terminal, may make
Cannot consult to suitable parameter into redirecting the time period in protocol state machine, so as to cause link unstable.Need searching one badly
Individual method effectively chooses the balance parameters of the chip receiving terminal of most suitable stabilization, and is fixed up.
The content of the invention
Explained below is made to the noun occurred in the present invention below:
PCIE:English full name Peripheral Component Interconnect Express, Chinese full name is quick peripheral hardware
Component interconnection, is newest bus and interface standard, belongs to the point-to-point binary channels high bandwidth transmission of high speed serialization, is connected
Equipment distribution exclusively enjoy bandwidth chahnel, not share bus bandwidth, mainly support active power management, error reporting is end-to-end
The functions such as reliability transmission, hot plug and service quality.
Self adaptation:Self adaptation herein refers to sef-adapting filter, and it is can be according to input signal adjust automatically
The digital filter of Digital Signal Processing can be carried out.
Eye pattern:It is, because the twilight sunset of oscillograph is acted on, each symbol waveform obtained by scanning to be overlaped, so that
Eye pattern is formed, it refers to that profit is experimentally estimated and improved(By adjustment)Observed on oscillograph during Transmission system performance
A kind of figure for arriving.Observing the method for eye pattern is:The output end of receiving filter is connected across with an oscillograph, then adjustment is shown
The ripple device scan period, make the cycle synchronisation in scope horizontal sweep cycle and receiving symbol, at this moment see in oscillograph screen
Figure is referred to as " eye pattern " as the eyes of people.
Postemphasis:English full name De-emphasis, the transmission signal that will have been aggravated reverts to the mistake of original signal form
Journey.Postemphasis is for preemphasis.Signal after preemphasis needs to carry out treatment of postemphasising after analyzing and processing,
Original characteristic is reduced into plus the frequency characteristic of -6dB/ octaves decline.
It is balanced:Refer to that the balanced device of chip receiving terminal produces the characteristic opposite with channel, for offsetting the time-varying multipath of channel
The intersymbol interference that propagation characteristic causes.Major obstacle when intersymbol interference is transmitting high speed data in mobile radio telecommunications channel,
And equilibrium is the effective means for tackling intersymbol interference.Because Mobile Fading Channels have randomness and time variation, this is required
Weighing apparatus allows for tracking in real time the time-varying characteristics of mobile telecommunication channel, and this balanced device is referred to as adaptive equalizer.
For above technical problem, it is an object of the invention to provide a kind of side for choosing and verifying PCIE link equalization parameters
Method and device, effectively have chosen the balance parameters of chip receiving terminal.
To achieve these goals, the present invention uses following technical scheme:
The present invention provides a kind of method chosen and verify PCIE link equalization parameters, including:
Choose the inclined parameter of multigroup drawing of PCIE links;
Inclined parameter round will be drawn to be written in the corresponding register of PCIE chip receiving terminals;
The wrong parameter for drawing inclined parameter to be produced during operation is received, and is recorded in error code register;
Selection Center parameter;
PCIE links are held consultation, the concentration degree of Center Parameter is judged, if concentration degree is concentrated, the Center Parameter effectively, should
Center Parameter is PCIE link equalization parameters, if concentration degree is disperseed, Selection Center parameter again.
Further, before the inclined parameter of multigroup drawing of PCIE links is chosen, also include:The initial ginseng of default PCIE links
Number.
Further, before the initial parameter of default PCIE links, also include:Close the adaptive of PCIE chip receiving terminals
Answer function.
Further, the inclined parameter of multigroup drawing of PCIE links is chosen, including:Choose the initial parameter of default PCIE links
The a range of multiple parameters in periphery.
Further, inclined parameter round will be drawn to be written in the corresponding register of PCIE chip receiving terminals, is specifically included:
Every group of inclined parameter of drawing is generated into different register files;
Register file round is written in the corresponding register of PCIE chip receiving terminals using the mode of automatized script.
Further, Selection Center parameter, specifically includes:
Derive the wrong parameter for receiving;
The wrong parameter that will be received is corresponding with inclined parameter is drawn, and forms visual form;
The multiple parameters of selection up and down for drawing inclined parameter a range of to visual form carry out eye pattern reading, record eye
Height, draws eye curve map high;
Choose eye curve map high and be in parameter centered on the parameter of ascent stage.
A kind of device chosen and verify PCIE link equalization parameters, including:
First chooses module, the inclined parameter of multigroup drawing for choosing PCIE links;
Writing module, for inclined parameter round will to be drawn to be written in the corresponding register of PCIE chip receiving terminals;
Logging modle, for receiving the wrong parameter for drawing inclined parameter to be produced during operation, and records in error code register
In;
Second chooses module, for Selection Center parameter;
Judge module, for being held consultation to PCIE links, judges the concentration degree of Center Parameter, if concentration degree is concentrated, in this
Effectively, the Center Parameter is PCIE link equalization parameters to heart parameter, if concentration degree is disperseed, Selection Center parameter again.
Further, also include:
Presetting module, presets the initial parameter of PCIE links.
Further, also include:
Switch module, the adaptation function for closing PCIE chip receiving terminals.
Further, also include:
Error code export module, for deriving the wrong parameter for receiving;
Preferably, also include:Table generation module, the wrong parameter for that will receive is corresponding with inclined parameter is drawn, and forms visual table
Lattice;
Preferably, also include:Eye Drawing of Curve module high, for drawing the upper and lower of inclined parameter to a range of in visual form
Left and right selection multiple parameters carry out eye pattern reading, and record eye is high, draws eye curve map high.
Compared with prior art, beneficial effects of the present invention are as follows:
1st, register file round is written in the corresponding register of PCIE chip receiving terminals using the mode of automatized script
Instead of register file round is written in the corresponding register of PCIE chip receiving terminals in a manual manner originally, people is reduced
Work labour intensity and risk, it is ensured that machinery, the precision of repetitive operation, save human cost;
The validity of the selection for the 2nd, being confirmed to draw inclined parameter by the concentration degree of parameter, has ensured minimum during PCIE link transmissions
The bit error rate, effectively avoids the decay of signal, improves the reliability of link transmission, improves the quality of signal transmission.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be to that will make needed for embodiment description
Accompanying drawing is briefly described.
Fig. 1 is that the present invention is a kind of to be chosen and verifies one of schematic flow sheet of method of PCIE link equalization parameters.
Fig. 2 is the two of a kind of schematic flow sheet of the method chosen and verify PCIE link equalization parameters of the present invention.
Fig. 3 is a kind of structural representation of the device chosen and verify PCIE link equalization parameters of the present invention.
Specific embodiment
In order that those skilled in the art more fully understand the present invention program, below in conjunction with the accompanying drawings and specific embodiment party
Formula, is clearly and completely described to the technical scheme in the embodiment of the present invention, it is clear that described embodiment is only this
The embodiment of a part is invented, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Embodiment 1
A kind of method chosen and verify PCIE link equalization parameters of the present invention, as shown in figure 1, including:
S101:Choose the inclined parameter of multigroup drawing of PCIE links;
S102:Inclined parameter round will be drawn to be written in the corresponding register of PCIE chip receiving terminals;
S103:The wrong parameter for drawing inclined parameter to be produced during operation is received, and is recorded in error code register;
S104:Selection Center parameter;
S105:PCIE links are held consultation, the concentration degree of Center Parameter is judged, if concentration degree is concentrated, the Center Parameter has
Effect, the Center Parameter is PCIE link equalization parameters, if concentration degree is disperseed, returns to S104 Selection Center parameters again.
Used as a kind of embodiment, PCIE links are PCIE3.0 links, and PCIE3.0 links need to choose 20 groups in advance
Inclined parameter is drawn, then the inclined parameter round of 20 groups of drawings chosen is written in the corresponding register of PCIE3.0 chip receiving terminals, connect
The wrong parameter that inclined parameter is produced during operation is reeled, and is recorded in error code register, be then led off the mistake for receiving
Parameter by mistake is right by the wrong parameter of reception and corresponding, the visual form of formation that obtains the drawing inclined parameter that this result run at that time
The inclined parameter of drawing in visual form in the range of +/- 6dB respectively selects 2 parameters to read eye pattern up and down, and record eye is high, draws eye
Curve map high, chooses eye curve map high and is in parameter centered on the parameter of ascent stage, experiment board is restarted, to PCIE3.0 links
Consulted repeatedly, judged the concentration degree of Center Parameter, if concentration degree is concentrated, effectively, the Center Parameter is the Center Parameter
It is PCIE3.0 link equalization parameters, if concentration degree is disperseed, needs to re-start the selection of Center Parameter, it is effective until selecting
Center Parameter.
Embodiment 2
Another method chosen and verify PCIE link equalization parameters of the invention, as shown in Fig. 2 including:
S201:Close the adaptation function of PCIE chip receiving terminals;
S202:Multigroup initial parameter of default PCIE links;
S203:The a range of multiple parameters in periphery of PCIE link initial parameters are chosen to draw inclined parameter;
S204:Every group of inclined parameter of drawing is generated into different register files;
S205:Register file round is written to the corresponding register of PCIE chip receiving terminals using the mode of automatized script
In;
S206:The wrong parameter for drawing inclined parameter to be produced during operation is received, and is recorded in error code register;
S207:The wrong parameter for receiving is derived, the wrong parameter that will be received is corresponding with inclined parameter is drawn, form visual form;
S208:Selecting a range of inclined parameter of drawing in visual form a number of parameter up and down carries out eye pattern reading
Take, record eye is high, draw eye curve map high;
S209:Choose eye curve map high and be in parameter centered on the parameter of ascent stage.
S210:PCIE links are held consultation, the concentration degree of Center Parameter is judged, if concentration degree is concentrated, Ze Gai centers ginseng
Number is effective, and the Center Parameter is i.e. PCIE link equalizations parameter, if concentration degree is disperseed, returns to S209 Selection Center ginsengs again
Number.
Used as a kind of embodiment, PCIE links are PCIE3.0 links, and certain limit refers to the model of +/- 4dB in step
Enclose;Firstly the need of the adaptation function having of first closing PCIE3.0 chip receiving terminals, and preset 20 groups of PCIE3.0 links
Initial parameter, chooses the parameter of the +/- 4dB in periphery of this 20 groups of initial parameters to draw inclined parameter, the 20 groups of inclined parameters of drawing that will be obtained
The different register file of generation, is written to PCIE3.0 chips and connects using the mode of automatized script by register file round
In the corresponding register of receiving end, mistake can be produced during drawing inclined parameter to run, the wrong parameter record that will be received is by mistake
In Code memory, be then led off receive wrong parameter, by the wrong parameter of reception with obtain what this result was run at that time
That group draws inclined parameter correspondence, forms visual form;To the inclined parameter of all drawings in the range of +/- 4dB in visual form up and down
Each 3 groups of parameters of selection read eye pattern, and record eye is high, draws eye curve map high;Choose the parameter that eye curve map high is in the ascent stage
Centered on parameter, restart experiment board, PCIE3.0 links are consulted repeatedly, judge the concentration degree of Center Parameter, if concentrate
Degree is concentrated, then effectively, the Center Parameter is PCIE3.0 link equalization parameters to the Center Parameter, if concentration degree is disperseed, returns
S209 Selection Center parameters again.
Embodiment 3
A kind of device chosen and verify PCIE link equalization parameters of the present invention, as shown in figure 3, including:First chooses module
101, writing module 102, logging modle 103, second chooses module 104, and judge module 105, switch module 106, error code is derived
Module 107, table generation module 108, eye Drawing of Curve module 109 high, presetting module 110.
Switch module 106 is used to close the adaptation function of PCIE chip receiving terminals;Presetting module 110 is used to preset PCIE
The initial parameter of link;First selection module 101 is used to choose a range of 20 of the periphery of PCIE link initial parameters
Parameter is the inclined parameter of drawing;Writing module 102 is used to that inclined parameter round will to be drawn to be written to the corresponding register of PCIE chip receiving terminals
In;Logging modle 103 is used to receive the wrong parameter for drawing inclined parameter to be produced during operation, and records in error code register
In;Error code export module 107 is used to derive the wrong parameter for receiving;Table generation module 108 is used for the wrong parameter that will be received
It is corresponding with inclined parameter is drawn, form visual form;Eye Drawing of Curve module 109 high:In the range of to +/- 4dB in visual form
The inclined parameter of drawing respectively select 3 groups of parameters to carry out eye pattern reading up and down, record eye is high, draws eye curve map high;Second chooses
Module 104 is used to choose parameter centered on parameter of the eye curve map high in the ascent stage;Judge module 105 is used to judge that center is joined
Several concentration degrees, if concentration degree is concentrated, effectively, the Center Parameter is PCIE link equalization parameters to the Center Parameter, if concentrating
Degree dispersion, then Selection Center parameter again.
One of ordinary skill in the art will appreciate that realizing that all or part of step of above-described embodiment can be by hardware
To complete, it is also possible to instruct the hardware of correlation to complete by program.It is last it should be noted that:The foregoing is only the present invention
Preferred embodiment, be merely to illustrate technical scheme, be not intended to limit the scope of the present invention.It is all in this hair
Any modification, equivalent substitution and improvements done within bright spirit and principle etc., are all contained in protection scope of the present invention.
Claims (10)
1. it is a kind of choose and checking PCIE link equalization parameters method, it is characterised in that including:
Choose the inclined parameter of multigroup drawing of PCIE links;
Inclined parameter round will be drawn to be written in the corresponding register of PCIE chip receiving terminals;
The wrong parameter for drawing inclined parameter to be produced during operation is received, and is recorded in error code register;
Selection Center parameter;
PCIE links are held consultation, the concentration degree of Center Parameter is judged, if concentration degree is concentrated, the Center Parameter effectively, should
Center Parameter is PCIE link equalization parameters, if concentration degree is disperseed, Selection Center parameter again.
2. it is according to claim 1 it is a kind of choose and checking PCIE link equalization parameters method, it is characterised in that choosing
Before taking the inclined parameter of multigroup drawing of PCIE links, also include:The initial parameter of default PCIE links.
3. it is according to claim 2 it is a kind of choose and checking PCIE link equalization parameters method, it is characterised in that pre-
If before the initial parameter of PCIE links, also including:Close the adaptation function of PCIE chip receiving terminals.
4. it is according to claim 2 it is a kind of choose and checking PCIE link equalization parameters method, it is characterised in that choose
The inclined parameter of multigroup drawing of PCIE links, including:Choose a range of multiple in periphery of the initial parameter of default PCIE links
Parameter.
5. it is according to claim 1 it is a kind of choose and checking PCIE link equalization parameters method, it is characterised in that will draw
Inclined parameter round is written in the corresponding register of PCIE chip receiving terminals, is specifically included:
Every group of inclined parameter of drawing is generated into different register files;
Register file round is written in the corresponding register of PCIE chip receiving terminals using the mode of automatized script.
6. it is according to claim 1 it is a kind of choose and checking PCIE link equalization parameters method, it is characterised in that choose
Center Parameter, specifically includes:
Derive the wrong parameter for receiving;
The wrong parameter that will be received is corresponding with inclined parameter is drawn, and forms visual form;
The multiple parameters of selection up and down for drawing inclined parameter a range of to visual form carry out eye pattern reading, record eye
Height, draws eye curve map high;
Choose eye curve map high and be in parameter centered on the parameter of ascent stage.
7. it is a kind of choose and checking PCIE link equalization parameters device, it is characterised in that including:
First chooses module, the inclined parameter of multigroup drawing for choosing PCIE links;
Writing module, for inclined parameter round will to be drawn to be written in the corresponding register of PCIE chip receiving terminals;
Logging modle, for receiving the wrong parameter for drawing inclined parameter to be produced during operation, and records in error code register
In;
Second chooses module, for Selection Center parameter;
Judge module, for being held consultation to PCIE links, judges the concentration degree of Center Parameter, if concentration degree is concentrated, in this
Effectively, the Center Parameter is PCIE link equalization parameters to heart parameter, if concentration degree is disperseed, Selection Center parameter again.
8. it is according to claim 7 it is a kind of choose and checking PCIE link equalization parameters device, it is characterised in that also wrap
Include:
Presetting module, presets the initial parameter of PCIE links.
9. it is according to claim 7 it is a kind of choose and checking PCIE link equalization parameters device, it is characterised in that also wrap
Include:
Switch module, the adaptation function for closing PCIE chip receiving terminals.
10. it is according to claim 7 it is a kind of choose and checking PCIE link equalization parameters device, it is characterised in that also
Including:
Error code export module, for deriving the wrong parameter for receiving;
Preferably, also include:Table generation module, the wrong parameter for that will receive is corresponding with inclined parameter is drawn, and forms visual table
Lattice;
Preferably, also include:Eye Drawing of Curve module high, for drawing the upper and lower of inclined parameter to a range of in visual form
Left and right selection multiple parameters carry out eye pattern reading, and record eye is high, draws eye curve map high.
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108763001A (en) * | 2018-05-25 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of test of universal serial bus is given out a contract for a project method |
CN109165046A (en) * | 2018-08-24 | 2019-01-08 | 郑州云海信息技术有限公司 | A kind of onboard SATA parameter optimization method and device |
CN109388607A (en) * | 2018-10-25 | 2019-02-26 | 江苏华存电子科技有限公司 | Method suitable for the transmission end peripheral hardware interconnection standard PCIe Coefficient Equilibrium mechanism |
CN111984477A (en) * | 2020-07-09 | 2020-11-24 | 瑞芯微电子股份有限公司 | PCIe equipment signal parameter dynamic correction device and method |
CN112737713A (en) * | 2020-12-30 | 2021-04-30 | 海光信息技术股份有限公司 | PCIe link equalization coefficient automatic adjustment method and device |
CN114443537A (en) * | 2022-01-28 | 2022-05-06 | 浪潮(山东)计算机科技有限公司 | Method, device, equipment and medium for configuring parameters of PCIE signal sending terminal |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103797732A (en) * | 2013-11-05 | 2014-05-14 | 华为技术有限公司 | Communication method, peripheral component interconnect express (PCIE) chip and PCIE devices |
CN103885911A (en) * | 2012-12-20 | 2014-06-25 | 辉达公司 | Multipass approach for performing channel equalization training |
CN103885907A (en) * | 2012-12-20 | 2014-06-25 | 辉达公司 | Equalization Coefficient Search Algorithm |
US20140281067A1 (en) * | 2013-03-15 | 2014-09-18 | Debendra Das Sharma | Apparatus, system, and method for performing link training and equalization |
US20140362901A1 (en) * | 2011-03-08 | 2014-12-11 | Tektronix, Inc. | Methods and systems for providing optimum decision feedback equalization of high-speed serial data links |
US9124455B1 (en) * | 2014-09-24 | 2015-09-01 | Intel Corporation | Link equalization mechanism |
-
2017
- 2017-01-13 CN CN201710024897.5A patent/CN106817258A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140362901A1 (en) * | 2011-03-08 | 2014-12-11 | Tektronix, Inc. | Methods and systems for providing optimum decision feedback equalization of high-speed serial data links |
CN103885911A (en) * | 2012-12-20 | 2014-06-25 | 辉达公司 | Multipass approach for performing channel equalization training |
CN103885907A (en) * | 2012-12-20 | 2014-06-25 | 辉达公司 | Equalization Coefficient Search Algorithm |
US20140281067A1 (en) * | 2013-03-15 | 2014-09-18 | Debendra Das Sharma | Apparatus, system, and method for performing link training and equalization |
CN103797732A (en) * | 2013-11-05 | 2014-05-14 | 华为技术有限公司 | Communication method, peripheral component interconnect express (PCIE) chip and PCIE devices |
US9124455B1 (en) * | 2014-09-24 | 2015-09-01 | Intel Corporation | Link equalization mechanism |
Cited By (9)
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CN108763001A (en) * | 2018-05-25 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of test of universal serial bus is given out a contract for a project method |
CN109165046A (en) * | 2018-08-24 | 2019-01-08 | 郑州云海信息技术有限公司 | A kind of onboard SATA parameter optimization method and device |
CN109388607A (en) * | 2018-10-25 | 2019-02-26 | 江苏华存电子科技有限公司 | Method suitable for the transmission end peripheral hardware interconnection standard PCIe Coefficient Equilibrium mechanism |
CN111984477A (en) * | 2020-07-09 | 2020-11-24 | 瑞芯微电子股份有限公司 | PCIe equipment signal parameter dynamic correction device and method |
CN111984477B (en) * | 2020-07-09 | 2022-05-17 | 瑞芯微电子股份有限公司 | PCIe equipment signal parameter dynamic correction device and method |
CN112737713A (en) * | 2020-12-30 | 2021-04-30 | 海光信息技术股份有限公司 | PCIe link equalization coefficient automatic adjustment method and device |
CN112737713B (en) * | 2020-12-30 | 2023-12-19 | 海光信息技术股份有限公司 | Automatic adjusting method and device for PCIe link equalization coefficient |
CN114443537A (en) * | 2022-01-28 | 2022-05-06 | 浪潮(山东)计算机科技有限公司 | Method, device, equipment and medium for configuring parameters of PCIE signal sending terminal |
CN114443537B (en) * | 2022-01-28 | 2023-12-19 | 浪潮(山东)计算机科技有限公司 | PCIE signal transmitting end parameter configuration method, device, equipment and medium |
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Application publication date: 20170609 |