CN106783887B - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN106783887B CN106783887B CN201710002822.7A CN201710002822A CN106783887B CN 106783887 B CN106783887 B CN 106783887B CN 201710002822 A CN201710002822 A CN 201710002822A CN 106783887 B CN106783887 B CN 106783887B
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- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 38
- 238000002161 passivation Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000003993 interaction Effects 0.000 claims description 6
- 238000012360 testing method Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000010408 film Substances 0.000 description 8
- 238000011161 development Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate, a preparation method thereof and a display device, relates to the technical field of display, and can improve the display effect. The array substrate includes: the thin film transistor comprises a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are sequentially arranged on a substrate; the array substrate further comprises a passivation layer and a conducting layer which are sequentially arranged on one side, far away from the substrate, of the source electrode and the drain electrode; wherein an orthographic projection of the conductive layer on the substrate overlaps with an orthographic projection of the active layer on the substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
With the development of display technology, especially the requirement of small-sized screens for narrow borders is higher and higher. With the continuous improvement of the switching characteristics of a Thin Film Transistor (TFT), in the prior art, a gate driver on Array (GOA) is often adopted to integrate a gate driver circuit in a peripheral area of an Array substrate, so as to reduce the use of Integrated Circuits (ICs), improve the integration of a display device, and reduce the manufacturing cost while realizing a narrow frame design.
In the prior art, as shown in fig. 1, an array substrate display area and a GOA area, the GOA area is provided with a thin film transistor, and the thin film transistor includes a gate electrode 11, a gate insulating layer 12, an active layer 13, a source electrode 14, and a drain electrode 15, which are sequentially disposed on a substrate 10; the array substrate further includes a passivation layer 16 sequentially disposed on the source electrode 14 and the drain electrode 15 at a side away from the substrate 10. The gate 11 forms a pre-gate channel 110 at the interface of the active layer 13 and the gate insulating layer 12 and a post-gate channel 120 at the interface of the active layer 13 and the passivation layer 16. When the TFT is turned off, the front channel 110 and the rear channel 120 may form a large GOA area channel leakage current, which may easily cause the display device to have poor display.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device, which can improve the display effect.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an array substrate is provided, which includes a GOA region, wherein the GOA region is provided with a thin film transistor, and the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, which are sequentially disposed on a substrate; the array substrate further comprises a passivation layer and a conducting layer which are sequentially arranged on one side, far away from the substrate, of the source electrode and the drain electrode; wherein an orthographic projection of the conductive layer on the substrate overlaps with an orthographic projection of the active layer on the substrate.
Optionally, the conductive layer covers the GOA region.
Optionally, the conductive layer includes a hollow portion, a conductive structure is disposed in the hollow portion, and the conductive structure is insulated from the conductive layer.
Preferably, a via hole is formed in the passivation layer, and the conductive structure is electrically connected to the drain electrode through the via hole.
Preferably, the conductive layer is a metal conductive layer.
Further preferably, the material of the metal conductive layer is a light-shielding material.
In a second aspect, a method for manufacturing an array substrate is provided, where the array substrate includes a GOA region, a thin film transistor is formed in the GOA region, and the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, which are sequentially formed on a substrate; the array substrate further comprises a passivation layer and a conducting layer which are sequentially formed on one sides, far away from the substrate, of the source electrode and the drain electrode; wherein an orthographic projection of the conductive layer on the substrate overlaps with an orthographic projection of the active layer on the substrate.
Optionally, the conductive layer covers the GOA region.
Optionally, the conductive layer includes a hollow portion, a conductive structure is formed in the hollow portion, and the conductive structure is insulated from the conductive layer.
In a third aspect, a display device is provided, which includes the array substrate of the first aspect.
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device. Inputting a low-voltage signal to the conductive layer, and when the thin film transistor is closed, the leakage current generated by the back channel of the conductive layer is counteracted by the interaction with the leakage current generated by the front channel of the grid; the leakage current generated by the front channel of the conductive layer is counteracted by the interaction with the leakage current generated by the back channel of the grid electrode. Therefore, the leakage current of the thin film transistor in the GOA area can be reduced, and the display effect of the display device can be ensured when the array substrate is applied to the display device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a GOA region of an array substrate provided in the prior art;
fig. 2 is a first schematic structural diagram of a GOA region of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a GOA region of an array substrate according to an embodiment of the present invention;
fig. 4(a) is a schematic structural diagram of a GOA region of an array substrate according to a third embodiment of the present invention;
fig. 4(b) is a schematic top view of a GOA region of an array substrate according to an embodiment of the present invention;
fig. 4(c) is a schematic structural diagram of a GOA region of an array substrate according to a fourth embodiment of the present disclosure;
fig. 5 is a flowchart of a method for manufacturing a conductive layer according to an embodiment of the invention;
fig. 6 is a first schematic diagram illustrating a method for manufacturing a conductive layer according to an embodiment of the present invention;
fig. 7 is a second schematic diagram illustrating a method for manufacturing a conductive layer according to an embodiment of the invention;
fig. 8 is a third schematic diagram illustrating a method for manufacturing a conductive layer according to an embodiment of the present invention;
fig. 9 is a fourth schematic view illustrating a method for manufacturing a conductive layer according to an embodiment of the present invention;
fig. 10 is a fifth schematic view illustrating a method for manufacturing a conductive layer according to an embodiment of the invention;
fig. 11 is a first schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 12 is a second schematic structural diagram of an array substrate according to an embodiment of the present invention.
Reference numerals:
10-a substrate; 11-a gate; 12-a gate insulating layer; 13-an active layer; 14-a source electrode; 15-a drain electrode; 16-a passivation layer; 17-a conductive layer; 171-conductive layer film; 18-a conductive structure; 191-photoresist; 19-a photoresist layer; 110-gate front channel; 120-gate back channel; 210-conductive layer back channel; 220-conductive layer front channel.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides an array substrate, which comprises a GOA (gate on array) region, wherein the GOA region is provided with a thin film transistor, and as shown in FIG. 2, the thin film transistor comprises a gate 11, a gate insulating layer 12, an active layer 13, a source 14 and a drain 15 which are sequentially arranged on a substrate 10; the array substrate further comprises a passivation layer 16 and a conductive layer 17 which are sequentially arranged on one side of the source electrode 14 and the drain electrode 15 away from the substrate 10; wherein the orthographic projection of the conductive layer 17 on the substrate 10 overlaps with the orthographic projection of the active layer 13 on the substrate 10.
First, the specific material of the conductive layer 17 is not limited, and the conductive layer 17 is connected to the VGL signal, as shown in fig. 2, the conductive layer 17 can form a conductive layer back channel 210 at the interface between the active layer 13 and the gate insulating layer 12, and a conductive layer front channel 220 at the interface between the active layer 13 and the passivation layer 16.
Secondly, the specific shape of the conductive layer 17 is not limited, and it is sufficient that it has an overlapping portion with the orthographic projection of the active layer 13 on the substrate 10.
The thickness of the conductive layer 17 is not limited, and may be set reasonably according to the process conditions.
Thirdly, the thin film transistor may be an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, a metal oxide thin film transistor, an organic thin film transistor, etc. according to the material of the semiconductor active layer. On the basis, the thin film transistor can be of a staggered type, an inverted staggered type, a coplanar type, an inverted coplanar type and the like.
The thin film transistor may be a symmetric thin film transistor having the source electrode 14 and the drain electrode 15, or may be a U-shaped thin film transistor. One thin film transistor can be used as a switch structure, or more than two thin film transistors can be connected in parallel to be used as a switch structure.
Fourth, the substrate 10 may be a flexible substrate, a glass substrate, or other substrates. If the substrate 10 is a flexible substrate, a carrier substrate is disposed below the flexible substrate.
The embodiment of the invention provides an array substrate, wherein a conductive layer 17 is arranged above a thin film transistor in a GOA region, so that the conductive layer 17 forms a conductive layer back channel 210 at the interface of an active layer 13 and a gate insulating layer 12 and a conductive layer front channel 220 at the interface of the active layer 13 and a passivation layer 16. Inputting a low voltage signal to the conductive layer 17, and when the tft is turned off, the leakage current generated in the conductive layer back channel 210 and the leakage current generated in the gate front channel 110 interact to cancel each other; the leakage current generated by the conductive layer front channel 220 and the leakage current generated by the gate back channel 120 are mutually counteracted. Therefore, the leakage current of the thin film transistor in the GOA area can be reduced, and the display effect of the display device can be ensured when the array substrate is applied to the display device.
In order to reduce the requirements on the pattern etching of the conductive layer 17, the process difficulty is reduced, and the cost is saved. Preferably, as shown in fig. 3, the conductive layer 17 covers the GOA region.
I.e. the entire GOA area is covered with a conductive layer 17.
Preferably, as shown in fig. 4(a) and 4(b), the conductive layer 17 includes a hollow portion, the hollow portion is provided with a conductive structure 18, and the conductive structure 18 is insulated from the conductive layer 17.
Wherein, the conductive structure 18 and the conductive layer 17 both have a conductive function, and the conductive structure 18 is disposed at the hollow portion, so that the conductive structure 18 and the conductive layer 17 are mutually insulated, and as shown in fig. 4(b), an orthographic projection of the conductive structure 18 on the substrate 10 falls within an orthographic projection range of the hollow portion on the substrate 10.
In addition, the specific pattern of the conductive structures 18 and the cutouts is not limited.
When the conductive structure 18 needs to be disposed on the passivation layer 16, the embodiment of the invention can avoid short circuit caused by contact between the conductive layer 17 and the conductive structure 18 by disposing the hollow portion on the conductive layer 17 and disposing the conductive structure 18 on the hollow portion, and can also reduce the thickness of the array substrate, so that the array substrate is light and thin.
It is further preferred that the passivation layer 16 is provided with a via through which the conductive structure 18 is electrically connected to the drain electrode 15, as shown in fig. 4(b) and 4 (c).
When a test electrode needs to be arranged in the GOA region to complete the performance test of the thin film transistor, the conductive structure 18 arranged in the hollow part of the conductive layer 17 in the embodiment of the present invention is used as the test electrode, which not only can reduce the production cost, but also can make the array substrate light and thin.
More preferably, the conductive layer 17 is a transparent conductive layer.
In the embodiment of the present invention, the conductive layer 17 is a transparent conductive layer, and the conductive layer 17, the conductive structure 18, and the electrode layer of the display region can be formed by the same patterning process, so that the process frequency can be reduced, and the production efficiency can be improved.
Optionally, the conductive layer 17 is a metal conductive layer.
Since the resistance of the metal conductive layer is small, in the embodiment of the present invention, the conductive layer 17 is set as the metal conductive layer, so that power consumption can be reduced, and production cost can be reduced.
Further preferably, the material of the metal conductive layer is a light-shielding material.
That is, the conductive layer 17 is a metal layer which is opaque to light.
In the embodiment of the invention, the material of the metal conducting layer is selected to be the metal shading material, so that light can be prevented from irradiating the channel region of the active layer 13, the influence of the light on the channel region of the active layer 13 is reduced, and the leakage current of the thin film transistor is further reduced.
The embodiment of the invention also provides a preparation method of the array substrate, wherein the array substrate comprises a GOA area, a thin film transistor is formed in the GOA area, and as shown in fig. 2-4 (a), the thin film transistor comprises a gate electrode 11, a gate insulating layer 12, an active layer 13, a source electrode 14 and a drain electrode 15 which are sequentially formed on a substrate 10; the array substrate further comprises a passivation layer 16 and a conductive layer 17 which are sequentially formed on the source electrode 14 and the drain electrode 15 at the side far away from the substrate 10; wherein the orthographic projection of the conductive layer 17 on the substrate 10 overlaps with the orthographic projection of the active layer 13 on the substrate 10.
As shown in fig. 5, the forming of the conductive layer 17 includes:
s10, as shown in fig. 6, the conductive layer film 171 is formed on the substrate 10 on which the passivation layer 16 is formed.
Note that the method of forming the conductive layer film 171 is not limited, and the method of forming the conductive layer film 171 is appropriately selected depending on the material of the conductive layer 17.
S20, as shown in fig. 7, a photoresist 191 is coated on the substrate 10 on which the conductive layer film 171 is formed.
The photoresist 191 is very diverse, and can be classified into a negative photoresist and a positive photoresist according to its chemical reaction mechanism and development principle. The insoluble matter formed after illumination is negative glue; on the contrary, the positive glue is insoluble in some solvents and becomes a soluble substance after being irradiated by light. Different kinds of photoresist correspond to different mask plates. The embodiment of the present invention does not limit the kind of the photoresist 191.
S30, as shown in fig. 8, the photoresist layer 19 is formed by the exposure and development technique on the basis of S20.
Wherein the pattern of the photoresist layer 19 is the same as the pattern of the conductive layer to be formed.
S40, as shown in fig. 9, the conductive layer film 171 is etched in S30 to form the conductive layer 17.
The conductive layer film 171 may be etched by dry etching or wet etching, and may be selected according to the material of the conductive layer film 171.
S40, as shown in fig. 10, the photoresist layer 19 is peeled off in S40.
The embodiment of the invention provides a preparation method of an array substrate, wherein a conductive layer 17 is formed above a thin film transistor in a GOA region, so that the conductive layer 17 forms a conductive layer back channel 210 at the interface of an active layer 13 and a gate insulating layer 12 and a conductive layer front channel 220 at the interface of the active layer 13 and a passivation layer 16. Inputting a low voltage signal to the conductive layer 17, and when the tft is turned off, the leakage current generated in the conductive layer back channel 210 and the leakage current generated in the gate front channel 110 interact to cancel each other; the leakage current generated by the conductive layer front channel 220 and the leakage current generated by the gate back channel 120 are mutually counteracted. Therefore, the leakage current of the thin film transistor in the GOA area can be reduced, and the display effect of the display device can be ensured when the array substrate is applied to the display device.
In order to reduce the requirements on the pattern etching of the conductive layer 17, the process difficulty is reduced, and the cost is saved. Preferably, as shown in fig. 11, the conductive layer 17 covers the GOA region.
Optionally, as shown in fig. 12, the conductive layer 17 includes a hollow portion, a conductive structure 18 is formed in the hollow portion, and the conductive structure 18 is insulated from the conductive layer 17.
When the conductive structure 18 needs to be formed on the passivation layer 16, the embodiment of the invention forms the hollow portion on the conductive layer 17 and forms the conductive structure 18 in the hollow portion, so as to prevent the conductive layer 17 from contacting the conductive structure 18 to cause short circuit, reduce the thickness of the array substrate, and make the array substrate light and thin.
The embodiment of the invention also provides a display device which comprises the array substrate.
The display device may be specifically an OLED display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, a navigator and other products or components with any display function.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. The array substrate comprises a GOA area, wherein the GOA area is provided with a thin film transistor, and the array substrate is characterized in that the thin film transistor comprises a grid electrode, a grid insulation layer, an active layer, a source electrode and a drain electrode which are sequentially arranged on a substrate; the array substrate further comprises a passivation layer and a conducting layer which are sequentially arranged on one side, far away from the substrate, of the source electrode and the drain electrode;
wherein an orthographic projection of the conductive layer on the substrate overlaps with an orthographic projection of the active layer on the substrate;
the conducting layer is provided with a conducting layer back channel at the interface of the active layer and the gate insulating layer, a conducting layer front channel is formed at the interface of the active layer and the passivation layer, a low-voltage signal is input into the conducting layer, when the thin film transistor is closed, leakage current generated by the conducting layer back channel is counteracted by interaction with leakage current generated by the gate front channel, and the leakage current generated by the conducting layer front channel is counteracted by interaction with the leakage current generated by the gate back channel so as to reduce the leakage current of the thin film transistor in the GOA region;
the conducting layer comprises a hollow part, a conducting structure is arranged in the hollow part, and the conducting structure is insulated from the conducting layer;
a through hole is formed in the passivation layer, and the conductive structure is electrically connected with the drain electrode through the through hole;
the conductive structure serves as a test electrode.
2. The array substrate of claim 1, wherein the conductive layer covers the GOA region.
3. The array substrate of claim 1 or 2, wherein the conductive layer is a metal conductive layer.
4. The array substrate of claim 3, wherein the metal conductive layer is made of a light-shielding material.
5. The array substrate comprises a GOA area, and a thin film transistor is formed in the GOA area and is characterized by comprising a grid electrode, a grid insulation layer, an active layer, a source electrode and a drain electrode which are sequentially formed on a substrate; the array substrate further comprises a passivation layer and a conducting layer which are sequentially formed on one sides, far away from the substrate, of the source electrode and the drain electrode;
wherein an orthographic projection of the conductive layer on the substrate overlaps with an orthographic projection of the active layer on the substrate;
the conducting layer forms a conducting layer back channel at the interface of the active layer and the gate insulating layer, a conducting layer front channel is formed at the interface of the active layer and the passivation layer, a low-voltage signal is input into the conducting layer, when the thin film transistor is closed, leakage current generated by the conducting layer back channel is counteracted by interaction with leakage current generated by the grid electrode front channel, and the leakage current generated by the conducting layer front channel is counteracted by interaction with the leakage current generated by the grid electrode back channel so as to reduce the leakage current of the thin film transistor in the GOA region;
the conducting layer comprises a hollow part, a conducting structure is formed in the hollow part, and the conducting structure is insulated from the conducting layer;
a through hole is formed in the passivation layer, and the conductive structure is electrically connected with the drain electrode through the through hole;
the conductive structure serves as a test electrode.
6. The method of claim 5, wherein the conductive layer covers the GOA region.
7. A display device comprising the array substrate according to any one of claims 1 to 4.
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| CN201710002822.7A CN106783887B (en) | 2017-01-03 | 2017-01-03 | Array substrate, preparation method thereof and display device |
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| CN201710002822.7A CN106783887B (en) | 2017-01-03 | 2017-01-03 | Array substrate, preparation method thereof and display device |
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| CN109903712A (en) * | 2019-04-30 | 2019-06-18 | 深圳市华星光电半导体显示技术有限公司 | Array substrate horizontal drive circuit and display panel |
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| CN102117836A (en) * | 2009-12-31 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor |
| CN102751295A (en) * | 2009-07-18 | 2012-10-24 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing semiconductor device |
| CN103474472A (en) * | 2013-09-10 | 2013-12-25 | 深圳市华星光电技术有限公司 | Thin film transistor, array substrate and display panel |
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| KR100801961B1 (en) * | 2006-05-26 | 2008-02-12 | 한국전자통신연구원 | Organic Inverter with Dual-Gate Organic Thin-Film Transistor |
| KR100975870B1 (en) * | 2008-10-17 | 2010-08-13 | 삼성모바일디스플레이주식회사 | Light sensing circuit, controlling method of the same, and touch panel comrprising the light sensing circuit |
| US8395156B2 (en) * | 2009-11-24 | 2013-03-12 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| CN102540595B (en) * | 2010-12-31 | 2015-04-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal panel |
| CN103927965B (en) * | 2014-03-21 | 2017-02-22 | 京东方科技集团股份有限公司 | Driving circuit, driving method, GOA unit, GOA circuit and display device |
| CN105870059A (en) * | 2016-06-24 | 2016-08-17 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and their manufacture methods, and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751295A (en) * | 2009-07-18 | 2012-10-24 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing semiconductor device |
| CN102117836A (en) * | 2009-12-31 | 2011-07-06 | 乐金显示有限公司 | Thin film transistor |
| CN103474472A (en) * | 2013-09-10 | 2013-12-25 | 深圳市华星光电技术有限公司 | Thin film transistor, array substrate and display panel |
| CN104821339A (en) * | 2015-05-11 | 2015-08-05 | 京东方科技集团股份有限公司 | TFT and manufacturing method, array substrate and manufacturing and driving methods, and display device |
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