CN106656190A - Continuous approximation type analog-to-digital conversion circuit and method therefor - Google Patents
Continuous approximation type analog-to-digital conversion circuit and method therefor Download PDFInfo
- Publication number
- CN106656190A CN106656190A CN201510740530.4A CN201510740530A CN106656190A CN 106656190 A CN106656190 A CN 106656190A CN 201510740530 A CN201510740530 A CN 201510740530A CN 106656190 A CN106656190 A CN 106656190A
- Authority
- CN
- China
- Prior art keywords
- digital
- continuous approximation
- signal
- sampling
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
- H03M1/403—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type using switched capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A continuous approximation type analog-to-digital conversion circuit and a method therefor are disclosed. The method comprises the following steps: a continuous approximation type analog-to-digital converter is used for performing a sampling operation and a comparison operation according to a conversion clock pulse so as to convert an analog input signal into a digital output signal; when a continuous approximation motion is completed during the comparison operation, and a sampling and digital-to-analog conversion circuit of the continuous approximation type analog-to-digital converter is reset. Via the continuous approximation type analog-to-digital conversion circuit and the method therefor disclosed in the invention, design costs of an input buffer device used for driving the continuous approximation type analog-to-digital converter and a reference buffer device used for pushing the sampling and digital-to-analog conversion circuit can be reduced.
Description
Technical field
The present invention relates to a kind of Analog-digital Converter technology, more particularly to a kind of Continuous Approximation formula simulation number
Word change-over circuit and its method.
Background technology
Analog-digital converter (analog-to-digital converter, ADC) has various frameworks and respectively has
Each advantage.Wherein, Continuous Approximation formula (Successive Approximation Register, SAR)
ADC has low-power consumption, compared with characteristics such as small area and lower costs, be widely used in electronics in recent years
On equipment.
With the improvement of framework and technique, SAR ADC also initially towards the application of Developing High-speed, especially
It is that timesharing run-in index (timing-interleaved, TI) SAR ADC are even more Jing and are often used.Due to
SAR ADC are obtained and simulation using binary search algorithm (binary search algorithm)
The digital output signal that input signal matches.Therefore, SAR ADC need one than sampling frequency more
High bit cyclic clock pulse (Bit cycling clock) is realizing.In general, SAR ADC's turns
Throw-over rate is controlled by the outside conversion clock pulse (conversion clock) for providing.Change the every of clock pulse
The individual change-over period is divided into sampling phase and bit cyclic phase place.In sampling phase, SAR ADC must take
Sample analog input signal, and continue into bit cyclic phase place.In bit cyclic phase place, SAR ADC
Minimum effective bit (the least are arrived from highest significant bit (the most significant bit, MSB)
Significant bit, LSB) produce corresponding digital output code bit by bit, that is, generate numeral output letter
Number.
Before next change-over period is carried out every time, SAR ADC have one idle (idle) time
(that is, SAR ADC do not carry out any action), and the length of this standby time can in response to process-voltage-
Temperature (PVT) make a variation with the factor such as noise (noise) and determine.In order to lift the effect of SAR ADC
Can, the design by extending sampling phase is developed, it is to be advanced to the initial time of sampling phase
The transition time point of last bit cyclic clock pulse.However, under the framework of TI SAR ADC, this
Design can cause sampling phase overlap between different ADC, so that the sample circuit of SAR ADC
The signal being sampled to is interfered, and then reduces sampling quality.
The content of the invention
In one embodiment, a kind of Continuous Approximation formula analog-digital conversion method, it includes：Using one
Continuous Approximation formula analog-digital converter compares behaviour according to conversion clock pulse one sampling operation of execution and one
Make for an analog input signal to be converted into a digital output signal, and in comparing the company in operation
It is continuous when approaching action and completing, reset a sampling and the digital simulation of Continuous Approximation formula analog-digital converter
Change-over circuit.
In one embodiment, a kind of Continuous Approximation formula analog-to-digital conversion circuit, it includes：One is continuous
Approximant analog-digital converter and a replacement decision unit.Continuous Approximation formula analog-digital converter
Compare operation to change an analog input signal according to conversion clock pulse one sampling operation of execution and one
Into a digital output signal.Wherein, Continuous Approximation formula analog-digital converter includes a sampling and numeral
Analog conversion circuit, a comparison circuit and a Continuous Approximation formula control circuit.Comparison circuit coupling takes
Sample and D/A conversion circuit, and Continuous Approximation formula control circuit coupling sampling and digital simulation turn
Change circuit and comparison circuit.Replacement decision unit couples Continuous Approximation formula control circuit and sampling and number
Word analog conversion circuit.The Continuous Approximation action in operation is compared in the detection of replacement decision unit, and
Sampling and D/A conversion circuit are reset when Continuous Approximation action is completed.
To sum up, Continuous Approximation formula analog-to-digital conversion circuit of the invention and its method are applied to and connect
Continue approximant analog-to-digital conversion circuit, with detecting Continuous Approximation release (last circulation
Clock signal pull-up) when into sampling and D/A conversion circuit Reset Status.Consequently, it is possible to
Idle (idle) time of traditional SAR ADC can bring allow sampling and D/A conversion circuit with
Reference buffer does sth. in advance action, thus when can reduce sampling and D/A conversion circuit replacement (reset)
Bandwidth requirements and reduce reference buffer promote when bandwidth requirements.Also, because sampling and number
The lower plate of word analog conversion circuit enters Reset Status ahead of time, so sampling and D/A conversion circuit
Upper plate will be returned to this sampling value, therefore when into next sampling phase, Continuous Approximation formula
The common mode electrical level of analog-digital converter has returned back to the common mode electrical level of input buffer, uses and avoids needing
Want extra turnaround time.Therefore, Continuous Approximation formula analog-to-digital conversion circuit of the invention and
Its method is minimized and promotes the input buffer of Continuous Approximation formula analog-digital converter and promote sampling
And the design cost of the reference buffer of D/A conversion circuit.
Description of the drawings
Fig. 1 is that the summary of the Continuous Approximation formula analog-to-digital conversion circuit according to one embodiment of the invention is shown
It is intended to.
Fig. 2 is the flow chart of the SAR analog-digital conversion methods according to one embodiment of the invention.
Fig. 3 is the schematic diagram of an embodiment of the Continuous Approximation formula control circuit in Fig. 1.
Fig. 4 is the schematic diagram of an embodiment of the replacement decision unit in Fig. 1.
Fig. 5 is the schematic diagram of an embodiment of the sampling in Fig. 1 and D/A conversion circuit.
Fig. 6 is the schematic diagram of another embodiment of the sampling in Fig. 1 and D/A conversion circuit.
Fig. 7 is the signal of an example of the Reset Status of the sampling in Fig. 6 and D/A conversion circuit
Figure.
Fig. 8 for Fig. 1 SAR analog-to-digital conversion circuits under the example of N=5, the sequential of each signal
Figure.
Description of reference numerals：
10 Continuous Approximation formula (SAR) analog-digital converters (ADC)
110 samplings and D/A conversion circuit
111st, 113 switched capacitor array
130 comparison circuits
150 Continuous Approximation formula control circuits
151 circulation clock pulse generators
153 Continuous Approximation buffers
155 output logical blocks
1551 logic elements
1553 output units
20 replacement decision units
Vin analog input signals
Vinp positive signals
Vinn negative signals
CKs changes clock pulse
B[1:N] digital output signal
B1～BN digital codes
OUTp comparative results
OUTn comparative results
Valid useful signals
The current potentials of V1 first
The current potentials of V2 second
CK1～CKN circulates clock signal
Sc control signals
DFF1 triggers
DFF2 triggers
CKc controls clock pulse
DR reset signals
Vref datums
S31 is using Continuous Approximation formula analog-digital converter in the sampling in each cycle of conversion clock pulse
Phase place carries out a sampling operation to analog input signal to form a sampled signal
S33 is using Continuous Approximation formula analog-digital converter in the bit in each cycle of conversion clock pulse
Cycle phase carries out one to sampled signal and compares operation to produce digital output signal
S35 in compare operation in last time compare complete when, reset Continuous Approximation formula simulation numeral
One sampling of converter and D/A conversion circuit
Specific embodiment
Fig. 1 is Continuous Approximation formula (the Successive Approximation according to one embodiment of the invention
Register, SAR) analog-to-digital conversion circuit schematic diagram.Fig. 2 is real according to the present invention one
Apply the flow chart of the SAR analog-digital conversion methods of example.
With reference to Fig. 1, SAR analog-to-digital conversion circuits include a SAR analog-digital converters
(analog-to-digital converter, ADC) 10 and one replacement decision unit 20.SAR ADC
10 coupling replacement decision units 20.SAR ADC 10 are according to conversion clock pulse CKs by analog input signal
Vin is converted into the digital output signal B [1 for matching:N].Conversion clock pulse CKs has the multicycle, and
And each cycle is divided into a sampling phase (sampling phase) and a bit cyclic phase place
(bit-cycling phase).With reference to Fig. 2, in sampling phase, SAR ADC 10 are to analog input signal
Vin carries out a sampling operation to produce a sampled signal (step S31).In bit cyclic phase place, SAR
ADC 10 carries out one to sampled signal and compares operation to produce the digital output signal B [1 for matching:N]
(step S33).In other words, SAR ADC 10 are sampled operation, and base based on sampling phase
Operation is compared in bit cyclic phase place.During operation is compared, SAR ADC 10 carry out N
It is secondary to compare (perform Continuous Approximation action) sequentially to determine digital output signal B [1:N] N number of numeral
Code.Replacement decision unit 20 resets sampling and the number of SAR ADC 10 when last time compares and completes
Word analog conversion circuit (step S35).Wherein, N is positive integer.
In certain embodiments, SAR ADC 10 include one sampling and D/A conversion circuit 110,
One comparison circuit 130 and a Continuous Approximation formula control circuit 150.Continuous Approximation formula control circuit 150
Including a circulation clock pulse generator 151, a Continuous Approximation buffer 153 and an output logical block
155.Sampling and D/A conversion circuit 110 couple two inputs of comparison circuit 130, and compare
Compared with the output end coupling circulation clock pulse generator 151 of circuit 130.The circulation coupling of clock pulse generator 151 connects
It is continuous to approach buffer 153, output logical block 155 and replacement decision unit 20.Continuous Approximation is temporary
The coupling of storage 153 output logical block 155 and sampling and D/A conversion circuit 110.
The running of SAR ADC 10 starts from sampling operation.During sampling operation, Continuous Approximation formula control
Circuit processed 150 is sampled and D/A conversion circuit 110 with digital controlled signal Sc controls, to cause
Sampling and D/A conversion circuit 110 are sampled operation to analog input signal Vin to form one
Sampled signal.
Then, SAR ADC 10 are entered and are compared operation.Bit cyclic phase place includes sequentially a sequence of N
During individual bit decision (that is, n times compare).In this, sample and D/A conversion circuit 110 exists
Same bit only changes a bit during determining, and by maximum significant bit (most significant
Bit, MSB) start to change to minimum significant bit (least significant bit, LSB).
During each bit is determined, Continuous Approximation formula control circuit 150 is with digital controlled signal Sc controls
Sample and D/A conversion circuit 110 are produced, to cause sampling and D/A conversion circuit 110 to cut
Change a bit switch and one first current potential V1 and one second current potential V2 is formed according to sampled signal.Than
Compared with circuit 130 be sampled and D/A conversion circuit 110 on the first current potential V1 with sampling and number
The comparison of the second current potential V2 on word analog conversion circuit 110 with obtain comparative result OUTp,
OUTn.Operating state (useful signal Valid) of the circulation clock pulse generator 151 according to comparison circuit 130
Produce orderly multi cycle clock signal CK1～CKN.Continuous Approximation buffer 153 is according to circulation clock pulse
Signal CK1～CKN and comparative result OUTp produces N number of digital code to determine as following bit
Control signal Sc of period.During each bit is determined, the temporary control letter of output logical block 155
Number Sc.
Also, output logical block 155 is according to conversion clock pulse CKs, comparative result OUTp and most
Latter circulation clock signal CKN exports temporary control signal Sc using as digital output signal
B[1:N]。
Fig. 3 is the schematic diagram of an embodiment of the Continuous Approximation formula control circuit 150 in Fig. 1.
In certain embodiments, with reference to Fig. 3, circulation clock pulse generator 151 can be by the N for sequentially concatenating
Individual trigger DFF1 is realized.In certain embodiments, comparison circuit 130 may include comparator and
Anti- and lock (NAND gate).Comparator compares the first current potential V1 (positive pole input) and the second current potential
V2 (negative pole input), and comparator output comparative result OUTp and compares knot at (positive pole output)
Fruit OUTn (negative pole output).Anti- and lock judges comparator according to comparative result OUTp, OUTn
Whether output is effective.In other words, comparative result OUTp, OUTn is via anti-and lock logical operation
Produce useful signal Valid.The trigger DFF1 of the first order is according to useful signal Valid and supply voltage
VDD produces circulation clock signal CK1.Follow-up trigger DFF1 is then according to useful signal Valid
And the circulation clock signal of the trigger DFF1 outputs of previous stage produces corresponding circulation clock signal
(CK2～CKN).
In certain embodiments, with reference to Fig. 3, Continuous Approximation buffer 153 can be by the N for sequentially concatenating
Individual trigger DFF2 is realized.N number of trigger DFF2 receives respectively circulation clock signal
CK1～CKN.Each trigger DFF2 is tied according to the comparison of the circulation clock signal and positive pole that receive
Fruit OUTp exports a digital code.Digital code B1～BN that N number of trigger DFF2 is exported as
Digital controlled signal Sc and the control end being input into sampling and D/A conversion circuit 110.
In certain embodiments, with reference to Fig. 3, output logical block 155 includes a logic element 1551
And an output unit 1553.The N number of of the coupling Continuous Approximation of output unit 1553 buffer 153 touches
Send out the output of device DFF2 and logic element 1551.The reception conversion clock pulse CKs of logic element 1551,
Useful signal Valid and last circulation clock signal CKN, and according to this output one controls clock pulse
CKc.Output unit 1553 is according to control clock pulse CKc record digital code B1～BN and according to during control
Digital code B1 of record～BN is output as output signal B [1 by arteries and veins CKc:N].In some embodiments
In, logic element 1551 can with or lock (OR gate) realize.In certain embodiments, output unit
1553 can be realized with displacement buffer (shift register).
Fig. 4 is the schematic diagram of an embodiment of the replacement decision unit 20 in Fig. 1.
In certain embodiments, with reference to Fig. 4, replacement decision unit 20 is according to conversion clock pulse CKs and most
Latter circulation clock signal CKN produces reset signal DR, and resets company with this reset signal DR
It is continuous to approach N number of trigger DFF2 of buffer 153, so that reset N number of trigger DFF2 being exported
Digital code B1～BN.In this, digital code B1 after replacement～BN is defeated as digital controlled signal Sc
Enter the control end to sampling and D/A conversion circuit 110, to reset sampling and digital-to-analogue conversion
Circuit 110.
In certain embodiments, replacement decision unit 20 can be a logic element, and this logic element is
Or lock.In other words, replacement decision unit 20 receives conversion clock pulse CKs with last circulation clock signal
CKN, and carry out changing the logical operation of clock pulse CKs and circulation clock signal CKN to export replacement
Signal DR.
Fig. 5 is the schematic diagram of an embodiment of the sampling in Fig. 1 and D/A conversion circuit 110.
Fig. 6 is the schematic diagram of another embodiment of the sampling in Fig. 1 and D/A conversion circuit 110.
In certain embodiments, with reference to the 5th and 6 figures, sampling and D/A conversion circuit 110 are wrapped
Include an at least switched capacitor array 111,113.Each switched capacitor array 111,113 includes multigroup string
The switch element and capacity cell of connection, and each switch element is according to corresponding in digital controlled signal Sc
Digital code (in B1～BN one) is by capacity cell coupling (electric connection) for coupling to datum
Vref or ground connection.In n times relatively in last time compare and complete and (that is, circulate clock signal CKN
During pull-up) when, replacement decision unit 20 is according to conversion clock pulse CKs and last circulation clock signal
CKN pull-up reset signal DR, to export the reset signal DR of high level.Continuous Approximation buffer 153
N number of trigger DFF2 replacement (reset) termination receive high level reset signal DR thus weight
Put.Digital controlled signal Sc (the digital codes after N number of trigger DFF2 output replacements after replacement
B1～BN) to the switch element in switched capacitor array 111,113, with controlling switch capacitor array 111,
The capacity cell of coupling is electrically connected to reference level Vref by the switch element in 113.In some enforcements
In example, analog input signal Vin can be single-ended signal.In certain embodiments, analog input signal
Vin may include positive signal Vinp and negative signal Vinn.
For example, by taking 5 bits as an example, when last circulation clock signal CK5 pull-ups, sampling
And D/A conversion circuit 110 enters Reset Status because of reset signal DR pull-ups, i.e. its switch
Capacitor array 111,113 is coupled to reference level Vref, but input switch still remains off state (OFF),
As shown in Figure 7.Wherein, the sequential of each signal is as shown in Figure 8.
To sum up, Continuous Approximation formula analog-to-digital conversion circuit of the invention and its method are applied to and connect
Continue approximant analog-to-digital conversion circuit, with detecting Continuous Approximation release (last circulation
Clock signal CKN pull-ups) when into sampling and D/A conversion circuit 110 Reset Status.Such as
This one, idle (idle) time of traditional SAR ADC can bring and allow sampling and digital simulation to turn
Change circuit 110 and do sth. in advance action with reference buffer, thus sampling and D/A conversion circuit can be reduced
Bandwidth requirements when bandwidth requirements and reduction reference buffer during 110 replacement (reset) are promoted.And
And, because the lower plate of sampling and D/A conversion circuit 110 enters Reset Status ahead of time, take
The upper plate of sample and D/A conversion circuit 110 will be returned to this sampling value, therefore under entrance
During one sampling phase, the common mode electrical level of Continuous Approximation formula analog-digital converter 10 returns back to input and delays
The common mode electrical level of device is rushed, is used and is avoided the need for extra turnaround time.Therefore, company of the invention
Continue approximant analog-to-digital conversion circuit and its method is minimized promotion Continuous Approximation formula simulation numeral and turns
The input buffer of parallel operation 10 and the reference buffer for promoting sampling and D/A conversion circuit 110
Design cost.
Claims (10)
1. a kind of Continuous Approximation formula analog-digital conversion method, it is characterised in that include：
Using a Continuous Approximation formula analog-digital converter according to one change clock pulse perform a sampling operation with
And one compare operation so that an analog input signal is converted into a digital output signal；And
When this compares the Continuous Approximation action in operation and completes, Continuous Approximation formula simulation number is reset
One sampling of word converter and D/A conversion circuit.
2. during Continuous Approximation formula analog-digital conversion method, the wherein conversion as claimed in claim 1
Arteries and veins includes that multiple cycles, each cycle include a sampling phase and a bit cyclic phase place, and
The switch process includes：
Using the Continuous Approximation formula analog-digital converter in the respectively sampling phase to the analog input signal
Carry out a sampling operation to form a sampled signal；And
Using the Continuous Approximation formula analog-digital converter in the respectively bit cyclic phase place to the sampled signal
Carry out one compare operation to produce the digital output signal, wherein the Continuous Approximation action for perform to
The n times for determining N number of digital code of the digital output signal compare, and N is positive integer.
3. Continuous Approximation formula analog-digital conversion method as claimed in claim 2, each of which ratio
Relatively include：
Under the control of a control signal, using the sampling and D/A conversion circuit according to the sampling
Signal produces one first current potential and one second current potential；
Compare first current potential and second current potential to produce a comparative result；
Orderly multi cycle clock signal is produced according to the comparative result；
N number of digital code is produced according to the multi cycle clock signal and the comparative result；
Using N number of digital code as next control signal that this compares；And
It is N number of this to be controlled according to the conversion clock pulse, the comparative result and last circulation clock signal
The output of digital code.
4. Continuous Approximation formula analog-digital conversion method as claimed in claim 3, wherein replacement step
Suddenly include：
A reset signal is produced according to the conversion clock pulse and last circulation clock signal；And
N number of digital code is reset according to the reset signal.
5. Continuous Approximation formula analog-digital conversion method as claimed in claim 4, wherein replacement letter
Number generation step include：
The conversion clock pulse is carried out with the logical operation of last circulation clock signal to export the replacement letter
Number.
6. a kind of Continuous Approximation formula analog-to-digital conversion circuit, it is characterised in that include：
One Continuous Approximation formula analog-digital converter, according to one change clock pulse perform a sampling operation and
One compares operation so that an analog input signal is converted into a digital output signal, the Continuous Approximation formula mould
Intending digital quantizer includes：
One sampling and D/A conversion circuit；
One comparison circuit, couples the sampling and D/A conversion circuit；And
One Continuous Approximation formula control circuit, couples the sampling and D/A conversion circuit and compares electric with this
Road；And
One replacement decision unit, couples the Continuous Approximation formula control circuit and the sampling and digital simulation
Change-over circuit, detects that this compares the Continuous Approximation action in operation, and in the Continuous Approximation action
The sampling and D/A conversion circuit are reset when completing.
7. Continuous Approximation formula analog-to-digital conversion circuit as claimed in claim 6, wherein this continuously force
Nearly formula control circuit includes：
One circulation clock pulse generator, when producing orderly multi cycle according to the comparative result of the comparison circuit
Arteries and veins signal；
One Continuous Approximation buffer, according to the multi cycle clock signal and the comparative result number is produced
N number of digital code of word output signal, wherein N is positive integer；And
One output logical block, according to when the conversion clock pulse, the comparative result and last circulation
Arteries and veins signal controls N number of digital code and is output as the digital output signal.
8. Continuous Approximation formula analog-to-digital conversion circuit as claimed in claim 7, wherein replacement is determined
Plan unit produces a reset signal according to the conversion clock pulse and last circulation clock signal, so that
The reset signal resets the sampling and digital-to-analogue conversion electricity via the Continuous Approximation buffer is reset
Road.
9. Continuous Approximation formula analog-to-digital conversion circuit as claimed in claim 7, wherein replacement is determined
Plan unit is a logic element, and the logic element carries out the conversion clock pulse and last circulation clock pulse letter
Number logical operation to export a reset signal so that the reset signal via reset the Continuous Approximation it is temporary
Storage and reset the sampling and D/A conversion circuit.
10. Continuous Approximation formula analog-to-digital conversion circuit as claimed in claim 6, wherein the sampling and
D/A conversion circuit includes an at least switched capacitor array, and the replacement decision unit is continuously forced in this
Nearly action produces a reset signal, and an at least switched capacitor array according to the replacement letter when completing
Number it is coupled to a datum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510740530.4A CN106656190B (en) | 2015-11-04 | 2015-11-04 | Successive approximation type analog-digital conversion circuit and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510740530.4A CN106656190B (en) | 2015-11-04 | 2015-11-04 | Successive approximation type analog-digital conversion circuit and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106656190A true CN106656190A (en) | 2017-05-10 |
| CN106656190B CN106656190B (en) | 2020-02-14 |
Family
ID=58851027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510740530.4A Active CN106656190B (en) | 2015-11-04 | 2015-11-04 | Successive approximation type analog-digital conversion circuit and method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106656190B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108964661A (en) * | 2017-05-17 | 2018-12-07 | 瑞昱半导体股份有限公司 | It can speed up the successive approximation register formula analog-to-digital converter of resetting |
| CN111435837A (en) * | 2019-01-11 | 2020-07-21 | 瑞昱半导体股份有限公司 | Analog-to-digital conversion device |
| CN111478702A (en) * | 2019-01-23 | 2020-07-31 | 创意电子股份有限公司 | Analog-to-digital converter device and clock skew correction method |
| WO2022269403A1 (en) * | 2021-06-22 | 2022-12-29 | International Business Machines Corporation | Successive-approximation analog-to-digital converters |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| US8456335B2 (en) * | 2010-11-26 | 2013-06-04 | Hitachi, Ltd. | Analog-to-digital converter |
| CN102386923B (en) * | 2011-09-21 | 2014-01-01 | 北京工业大学 | Asynchronous successive approximation analog-to-digital converter and conversion method |
| CN104168020A (en) * | 2014-08-19 | 2014-11-26 | 复旦大学 | Capacitive nonlinear calibration circuit of bit-by-bit approximation analog-digital converter and method |
| US8912942B2 (en) * | 2013-05-03 | 2014-12-16 | Realtek Semiconductor Corp. | Successive-approximation-register analog-to-digital converter (SAR ADC) and method thereof |
-
2015
- 2015-11-04 CN CN201510740530.4A patent/CN106656190B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8456335B2 (en) * | 2010-11-26 | 2013-06-04 | Hitachi, Ltd. | Analog-to-digital converter |
| CN102355266A (en) * | 2011-07-28 | 2012-02-15 | 上海宏力半导体制造有限公司 | Successive approximation register analog-digital converter |
| CN102386923B (en) * | 2011-09-21 | 2014-01-01 | 北京工业大学 | Asynchronous successive approximation analog-to-digital converter and conversion method |
| US8912942B2 (en) * | 2013-05-03 | 2014-12-16 | Realtek Semiconductor Corp. | Successive-approximation-register analog-to-digital converter (SAR ADC) and method thereof |
| CN104168020A (en) * | 2014-08-19 | 2014-11-26 | 复旦大学 | Capacitive nonlinear calibration circuit of bit-by-bit approximation analog-digital converter and method |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108964661A (en) * | 2017-05-17 | 2018-12-07 | 瑞昱半导体股份有限公司 | It can speed up the successive approximation register formula analog-to-digital converter of resetting |
| CN108964661B (en) * | 2017-05-17 | 2022-03-22 | 瑞昱半导体股份有限公司 | Successive approximation register type analog-to-digital converter capable of accelerating reset |
| CN111435837A (en) * | 2019-01-11 | 2020-07-21 | 瑞昱半导体股份有限公司 | Analog-to-digital conversion device |
| CN111435837B (en) * | 2019-01-11 | 2023-01-31 | 瑞昱半导体股份有限公司 | Analog-to-digital conversion device |
| CN111478702A (en) * | 2019-01-23 | 2020-07-31 | 创意电子股份有限公司 | Analog-to-digital converter device and clock skew correction method |
| CN111478702B (en) * | 2019-01-23 | 2023-06-23 | 创意电子股份有限公司 | Analog-to-digital converter device and clock skew correction method |
| WO2022269403A1 (en) * | 2021-06-22 | 2022-12-29 | International Business Machines Corporation | Successive-approximation analog-to-digital converters |
| US11652493B2 (en) | 2021-06-22 | 2023-05-16 | International Business Machines Corporation | Successive-approximation analog-to-digital converters |
| US12088316B2 (en) | 2021-06-22 | 2024-09-10 | International Business Machines Corporation | Successive-approximation analog-to-digital converters |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106656190B (en) | 2020-02-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103905049B (en) | A kind of high-speed flash adds alternately comparison expression gradually-appoximant analog-digital converter | |
| US9685973B2 (en) | Successive approximation register (SAR) analog-to-digital converting circuit and method thereof | |
| CN102386923B (en) | Asynchronous successive approximation analog-to-digital converter and conversion method | |
| Jiang et al. | A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS | |
| KR102103933B1 (en) | Successive approximation analog to digital converter and method of analog to digital conversion | |
| CN105007079B (en) | The fully differential increment method of sampling of gradual approaching A/D converter | |
| US9432046B1 (en) | Successive approximation analog-to-digital converter | |
| CN105811986B (en) | A kind of Approach by inchmeal adc circuit of high-speed transitions | |
| CN104967451A (en) | Successive approximation type analog-to-digital converter | |
| CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
| TWI524679B (en) | Successive-approximation-register analog-to-digital converter (sar adc) and method therefor | |
| CN105187065A (en) | Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof | |
| CN106656190A (en) | Continuous approximation type analog-to-digital conversion circuit and method therefor | |
| CN103441765A (en) | Successive approximation register analog to digital converter and method thereof | |
| CN110768674A (en) | Analog-to-digital conversion device, analog-to-digital conversion equipment and analog-to-digital conversion method | |
| CN104143983B (en) | Continuous Approximation formula analog-digital converter and its method | |
| US8860598B2 (en) | Bit error rate timer for a dynamic latch | |
| US8928516B2 (en) | Method and apparatus for conversion of voltage value to digital word | |
| CN104518798B (en) | Analog-digital commutator and its method | |
| CN112994699B (en) | Offset calibration device, successive approximation type analog-to-digital conversion device and offset calibration method | |
| CN108649956A (en) | A kind of gradual approaching A/D converter based on asymmetric differential capacitance array | |
| Kościelnik et al. | A clockless time-to-digital converter | |
| JP2014236373A (en) | A/d conversion device | |
| CN109412598B (en) | Successive approximation type analog-to-digital conversion device | |
| CN103124177A (en) | Circular A/D (Analog/Digital) converter and digital calibration method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |