CN106409883A - High voltage LDMOS device and the manufacturing method thereof - Google Patents
High voltage LDMOS device and the manufacturing method thereof Download PDFInfo
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- CN106409883A CN106409883A CN201610929239.6A CN201610929239A CN106409883A CN 106409883 A CN106409883 A CN 106409883A CN 201610929239 A CN201610929239 A CN 201610929239A CN 106409883 A CN106409883 A CN 106409883A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 238000002360 preparation method Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 9
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- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000009826 distribution Methods 0.000 description 13
- 230000005684 electric field Effects 0.000 description 13
- 230000008859 change Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 5
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- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides a high voltage LDMOS device and the manufacturing method thereof, wherein the device comprises a first doped type substrate; a second doped type drift region located inside the first doped type substrate; a drain electrode located inside the second doped type drift region; a source electrode located inside the first doped type substrate; a polysilicon gate electrode located on the surface of the first doped type substrate between the drain electrode and the source electrode; and a first doped type embedding layer located inside the second doped type drift region between the source electrode and the drain electrode. The first doped type embedding layer is divided into two or more than two sections with equal distance from each other along the source electrode to the drain electrode direction. Compared with a traditional high-voltage LDMOS device, the high voltage LDMOS device boasts a shorter drift region length and a higher drift region concentration degree under the same voltage standing condition, therefore, possessing lower conductive resistance.
Description
Technical field
The invention belongs to technical field of semiconductors, more particularly to a kind of high-voltage LDMOS device and preparation method thereof.
Background technology
High-voltage LDMOS device (Lateral Diffused MOSFET, LDMOS) has work
Make the characteristics such as voltage is high, technique is relatively easy, switching frequency is high, and the drain electrode of described high-voltage LDMOS device, source electrode and grid
It is respectively positioned on its surface it is easy to (Complenentary Metal Oxide Semiconductor, complementary type is golden with low voltage CMOS
Belong to oxide semiconductor) and device phase in technique such as BJT (Bipolar Junction Transistor, bipolar transistor)
Compatibility, particularly AC/DC, DC/DC power management, LED drive and motor driving chip in can to carry out device integrated, thus
High-voltage LDMOS device receives significant attention, and is considered particularly suitable in high voltage integrated circuit and power integrated circuit
High voltage power device.
In the prior art, RESURF (reduction surface field) technology or laterally varying doping is typically adopted to improve height
Press the pressure of LDMOS device.Traditional RESURF technology is by the drift region (such as N-type drift region) of the first doping type note
Enter the buried regions (such as p type buried layer) of corresponding second doping type, to improve the resistance to of high-voltage LDMOS device by exhausting mutually
Pressure；However, improving pressure is contradiction with reduction than conducting resistance (conducting resistance × area), and, traditional RESURF knot
The surface field of structure generally only two peak values, have a certain distance with preferable rectangle Electric Field Distribution；Traditional horizontal change is mixed
Acrobatics art is that the pressure of high-voltage LDMOS device is improved in the drift region of the first doping type being adulterated by difference, but this structure
An only conductive channel is it is difficult to obtain high concentration drift region and low conducting resistance.
Content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of high-voltage LDMOS device and its
Preparation method, for solve in prior art using traditional RESURF technology improve pressure presence raising pressure with reduce ratio lead
Energising resistance contradicts, and surface field generally only has two peak values, has the problem of a certain distance with preferable rectangle Electric Field Distribution,
And an only conductive channel of pressure presence is improved it is difficult to obtain high concentration drift using traditional laterally varying doping
Area and the problem of low conducting resistance.
For achieving the above object and other related purposes, the present invention provides a kind of high-voltage LDMOS device, described high pressure
LDMOS device includes：
The substrate of the first doping type；
The drift region of the second doping type, in the substrate of described first doping type；
Drain electrode, in the drift region of described second doping type；
Source electrode, in the substrate of described first doping type；
Polysilicon gate, positioned at the substrate surface of described first doping type between described drain electrode and described source electrode；
The buried regions of the first doping type, the drift of described second doping type between described source electrode and described drain electrode
In area；The buried regions of described first doping type is divided into phase two across a certain distance along the direction from described source electrode to described drain electrode
Section or many cross-talks buried regions, the doping content of each section of described sub- buried regions is incomplete same.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, described high-voltage LDMOS device is included described in multilayer
The buried regions of the first doping type, the depth of the drift region along described second doping type for the buried regions of the first doping type described in multilayer
Direction parallel interval arrangement.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, described in neighboring layers, the first doping type buries
Spacing between layer is equal.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, described in neighboring layers, the first doping type buries
Spacing between layer.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, from described source electrode to described drain electrode, described in each layer
In the buried regions of the first doping type, the width of each cross-talk buried regions is gradually reduced.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, in the buried regions of described first doping type of each layer,
Spacing between adjacent each cross-talk buried regions is equal.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, in the buried regions of described first doping type of each layer,
Spacing between adjacent each cross-talk buried regions.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, in the buried regions of described first doping type of each layer,
Being smaller than between adjacent each cross-talk buried regions or be equal to 3 μm.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, described high-voltage LDMOS device also includes：
Field oxide, between the substrate and described polysilicon gate of described first doping type, and is located at described leakage
The substrate surface of described first doping type between pole and described source electrode；
The body area of the first doping type, in the substrate of described first doping type, and is located at described second doping class
The drift region of type is away from the side of described drain electrode；Described source electrode is located in the body area of described first doping type；
The heavily doped region of the first doping type, in the body area of described first doping type and adjacent with described source electrode
Connect.
As a kind of preferred version of the high-voltage LDMOS device of the present invention, described high-voltage LDMOS device also includes；
Dielectric layer, positioned at described field oxide and described polysilicon gate surface, described dielectric layer correspond to described drain electrode,
The position of the heavily doped region of described source electrode and described first doping type is formed with opening, described opening expose described drain electrode,
Described source electrode and the heavily doped region of described first doping type；
Drain electrode, in described opening and described dielectric layer surface, and is contacted with described drain electrode；
Source electrode, in described opening and described dielectric layer surface, and with described source electrode and described first doping class
The heavily doped region of type contacts.
The present invention also provides a kind of preparation method of high-voltage LDMOS device, the preparation method bag of described high-voltage LDMOS device
Include following steps：
1) substrate of the first doping type is provided；
2) form the drift region of the second doping type in the substrate of described first doping type；
3) buried regions of the first doping type, described first doping type are formed in the drift region of described second doping type
The length direction of the drift region along described second doping type for the buried regions be divided into mutually two sections across a certain distance or many cross-talks and bury
Layer, the doping content of each section of described sub- buried regions is incomplete same；
4) form polysilicon gate above the drift region of described second doping type；
5) form drain electrode in the drift region of described second doping type of described polysilicon gate side, in described polycrystalline
Form source electrode in the substrate of described first doping type of silicon gate opposite side.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, step 2) in, described first
The drift region forming described second doping type in the substrate of doping type comprises the steps：
The ion of the second doping type 2-1) is injected in the substrate of described first doping type using ion implantation technology；
2-2) form the drift region of described second doping type by high temperature knot.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, step 2-1) in, ion implanting
Dosage be 2 × 1012/cm2～8 × 1012/cm2；Step 2-2) in, the knot of the drift region of described second doping type of formation
Deeply it is 4 μm -16 μm, the length of the drift region of described second doping type of formation is 10 μm -100 μm.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, step 3) in, using ion note
Enter each cross-talk buried regions that technique forms described first doping type in the drift region of described second doping type, each section of described son
The dosage of the ion implanting of buried regions is 1 × 1012/cm2～7 × 1012/cm2.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, in ion implantation process, adopt
Form each cross-talk of the first doping type described in multilayer with ion implantation technology in the drift region of described second doping type to bury
Layer, the depth direction parallel interval row of the drift region along described second doping type for the buried regions of the first doping type described in multilayer
Cloth.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, from described source electrode to described leakage
Pole, in the buried regions of described first doping type of each layer, the width of each cross-talk buried regions is gradually reduced.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, in step 2) and step 3) it
Between, it is additionally included in the step that the substrate surface of described first doping type forms field oxide, now, step 4) in, described many
Polysilicon gate is located at the described field oxide surface above the drift region of described second doping type.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, in step 3) and step 4) it
Between, the drift region being additionally included in described second doping type is away from the body area of side formation first doping type of described drain electrode
Step；Step 5) in, described source electrode is located in the body area of described first doping type.
As a kind of preferred version of the preparation method of the high-voltage LDMOS device of the present invention, step 5) after also include as
Lower step：
6) heavily doped region of the first doping type, described first doping class are formed in the body area of described first doping type
The heavily doped region of type is adjacent with described source electrode；
7) form dielectric layer in described field oxide and described polysilicon gate surface；
8) position of the heavily doped region of described drain electrode, described source electrode and described first doping type is corresponded in described dielectric layer
Put and be formed with opening, described opening exposes the heavily doped region of described drain electrode, described source electrode and described first doping type；
9) in the described opening corresponding to described drain electrode and described dielectric layer surface formed drain electrode, corresponding to institute
Form source electrode in the described opening of the heavily doped region stating source electrode and described first doping type.
As described above, high-voltage LDMOS device of the present invention and preparation method thereof, have the advantages that：By by
The buried regions piecewise of one doping type is placed in the drift region of the second doping type so that the acquisition of described high-voltage LDMOS device is many
Peak surface Electric Field Distribution, and have two conductive channels；Compared with traditional high-voltage LDMOS device, the high pressure of the present invention
LDMOS device obtain identical pressure on the premise of, have shorter drift region length and higher drift region concentration, thus having
There is lower conducting resistance.
Brief description
Fig. 1 is shown as the cross section structure schematic diagram of the high-voltage LDMOS device of offer in the embodiment of the present invention one.
Fig. 2 is shown as the high-voltage LDMOS device provide in the embodiment of the present invention one and LDMOS device of the prior art
Surface electric field distribution figure.
Fig. 3 is shown as the cross section structure schematic diagram of the high-voltage LDMOS device of offer in the embodiment of the present invention two.
The flow chart that Fig. 4 is shown as the preparation method of high-voltage LDMOS device of offer in the embodiment of the present invention three.
Fig. 5 to Figure 16 is shown as in each step of preparation method of high-voltage LDMOS device provide in the embodiment of the present invention three
Cross section structure schematic diagram.
Component label instructions
The substrate of 10 first doping types
The drift region of 11 second doping types
12 drain electrodes
13 source electrodes
14 field oxides
15 polysilicon gates
The buried regions of 16 first doping types
161 sub- buried regions
The body area of 17 first doping types
The heavily doped region of 18 first doping types
19 dielectric layers
191 openings
20 drain electrodes
21 source electrodes
S1～S6 step
Specific embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by addition different concrete realities
The mode of applying is carried out or applies, and the every details in this specification can also be based on different viewpoints and application, without departing from
Carry out various modifications and changes under the spirit of the present invention.
Refer to Fig. 1 to Figure 16 it should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show the assembly relevant with the present invention rather than according to package count during actual enforcement in diagram
Mesh, shape and size are drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its
Assembly layout form is likely to increasingly complex.
Embodiment one
Refer to Fig. 1, the present invention provides a kind of high-voltage LDMOS device, described high-voltage LDMOS device includes：First doping
The substrate 10 of type；The drift region 11 of the second doping type, the drift region 11 of described second doping type is mixed positioned at described first
In the substrate 10 of miscellany type, described second doping type is different from described first doping type；Drain electrode 12, described drain electrode 12 is located at
In the drift region 11 of described second doping type；Source electrode 13, described source electrode 13 is located in the substrate 10 of described first doping type；
Polysilicon gate 15, described polysilicon gate 15 is located at described first doping type between described drain electrode 12 and described source electrode 13
Substrate 10 surface；The buried regions 16 of the first doping type, the buried regions 16 of described first doping type is located at described source electrode 13 and institute
State in the drift region 11 of described second doping type between drain electrode 12；The buried regions 16 of described first doping type is along from described source
Pole 13 is divided into mutually two sections or many cross-talks buried regions 161 across a certain distance, each section of described sub- buried regions to the direction of described drain electrode 12
161 doping content is incomplete same；Specifically, from left to right, the doping content of each section of described sub- buried regions 161 can be become with gradient
Change it is also possible to alternately change, can also random change.
As an example, described first doping type can be p-type, and described second doping type can be N-type.
As an example, described first doping type can be N-type, and described second doping type can be p-type.
As an example, the width of each section of described sub- buried regions 161 being divided in the buried regions 16 of described first doping type can
With identical it is also possible to different；Preferably, each section of described sub- buried regions 161 being divided in the buried regions 16 of described first doping type
Width different；It is further preferable that in the present embodiment, from described source electrode 13 to described drain electrode 12, described first doping type
In buried regions 16, the width of each section of described sub- buried regions 161 is gradually reduced.Certainly, in other examples, from described source electrode 13 to described
Drain electrode 12, in the buried regions 16 of described first doping type of each layer, the width of each section of described sub- buried regions 161 can also be gradually increased.
" each section of described sub- buried regions 161 in the buried regions 16 of described first doping type of each layer it should be noted that so-called
Width " refers to along from described source electrode 13 to the size in described drain electrode 12 directions.
As an example, described sub- buried regions 161 hop count of buried regions 16 segmentation of described first doping type can be according to reality
Needs are set it is preferable that in the present embodiment, the buried regions 16 of described first doping type is along from described source electrode 13 to described leakage
The direction of pole 12 is divided into 2～10 sections.
As an example, in the buried regions 16 of described first doping type of each layer, between adjacent each section of described sub- buried regions 161 between
Away from can equal it is also possible to.In the buried regions 16 of described first doping type of each layer, adjacent each section of described sub- buried regions 161 it
Between spacing can be set it is preferable that in the present embodiment according to actual needs, the buried regions of described first doping type of each layer
In 16, being smaller than between adjacent each section of described sub- buried regions 161 or be equal to 3 μm.
As an example, described high-voltage LDMOS device also includes：Field oxide 14, described field oxide 14 is located at described the
Between the substrate 10 of one doping type and described polysilicon gate 15, and it is located at the institute between described drain electrode 12 and described source electrode 13
State the substrate surface of the first doping type 10, that is, described polysilicon gate 15 is located between described drain electrode 12 and described source electrode 13
Described field oxide 14 surface；The body area 17 of the first doping type, the body area 17 of described first doping type is located at the first doping
In the substrate 10 of type, and it is located at the side away from described drain electrode 12 for the drift region 11 of the second doping type；Described source electrode is located at
In the body area 17 of described first doping type；The heavily doped region 18 of the first doping type, the heavy doping of described first doping type
Area 18 is located in the body area 17 of described first doping type, and adjacent with described source electrode 13.
As an example, described high-voltage LDMOS device also includes；Dielectric layer 19, described dielectric layer 19 is located at the oxidation of described field
Layer 14 and described polysilicon gate 15 surface, described dielectric layer 19 corresponds to described drain electrode 12, described source electrode 13 and described first
The position of the heavily doped region 18 of doping type is formed with opening (not shown), and described opening exposes described drain electrode 12, described source
Pole 13 and the heavily doped region 18 of described first doping type；Drain electrode 20, described drain electrode 20 be located at described opening in and
Described dielectric layer 19 surface, and contact with described drain electrode 12；Source electrode 21, described source electrode 21 is located in described opening
And described dielectric layer 19 surface, and contact with the heavily doped region 18 of described source electrode 13 and described first doping type；Positioned at institute
State the described drain electrode 20 on dielectric layer 19 surface and the described source electrode 21 positioned at described dielectric layer 19 surface is separated by necessarily
Spacing.
The high LDMOS device of the present invention is by being placed in the second doping class by buried regions 16 piecewise of described first doping type
In the drift region 11 of type, under high pressure so that described high-voltage LDMOS device obtains multi-peak surface electric field distribution, as Fig. 2 institute
Show, wherein, the 1. surface electric field distribution figure of the high-voltage LDMOS device described in the present embodiment, 2. for height of the prior art
The surface electric field distribution figure of pressure LDMOS device, lateral coordinates X are the distance from described source electrode 13 to described drain electrode 12.Due to resistance to
Pressure is the integration along depletion region direction for the electric field, that is, along from described source electrode 13 to the integration in described drain electrode 12 directions, therefore, multi-peak
The distribution of surface field obtains than the breakdown voltage of the distribution of few peak surface electric field of high-voltage LDMOS device of the prior art
To lifting, that is, under the conditions of pressure on an equal basis, the high-voltage LDMOS device of the present invention can have shorter drift region length Ldrift,
Higher drift region concentration, thus reducing the conducting resistance of high-voltage LDMOS device, reduces device area；In the present embodiment,
Described drift region length LdriftFor 10 μm -100 μm.
Embodiment two
Refer to Fig. 3, the present embodiment also provides a kind of high-voltage LDMOS device, the high-voltage LDMOS device described in the present embodiment
The structure of part is roughly the same with the structure of the high-voltage LDMOS device described in embodiment one, and the difference of the two is：Embodiment one
In, the quantity of the buried regions 16 of the first doping type described in described high-voltage LDMOS device is one layer, and in the present embodiment, described
The quantity of the buried regions 16 of the first doping type is two-layer or multilayer, and described in two-layer or multilayer, the buried regions 16 of the first doping type is along institute
State the depth direction parallel interval arrangement of the drift region 11 of the second doping type.
As an example, the spacing between the buried regions 16 of the first doping type described in neighboring layers can equal can not also
Deng not limiting herein.
The other structures of the high-voltage LDMOS device described in the present embodiment and the high-voltage LDMOS device described in embodiment one
The other structures of part are identical, specifically refer to embodiment one, are not repeated herein.
Embodiment three
Refer to Fig. 4, the present invention also provides a kind of preparation method of high-voltage LDMOS device, described high-voltage LDMOS device
Preparation method comprises the steps：
1) substrate of the first doping type is provided；
2) form the drift region of the second doping type in the substrate of described first doping type；
3) buried regions of the first doping type, described first doping type are formed in the drift region of described second doping type
The length direction of the drift region along described second doping type for the buried regions be divided into mutually two sections across a certain distance or many cross-talks and bury
Layer, the doping content of each section of described sub- buried regions is incomplete same；
4) form polysilicon gate above the drift region of described second doping type；
5) form drain electrode in the drift region of described second doping type of described polysilicon gate side, in described polycrystalline
Form source electrode in the substrate of described first doping type of silicon gate opposite side.
In step 1) in, refer to S1 step and the Fig. 5 in Fig. 4, the substrate 10 of the first doping type is provided.
As an example, a substrate is provided first, then the first doping is injected in described substrate by ion implantation technology
The ion of type is to form the substrate 10 of described first doping type.
As an example, described first doping type can be p-type or N-type.
In step 2) in, refer to S2 step and the Fig. 6 in Fig. 4, formed in the substrate 10 of described first doping type
The drift region 11 of the second doping type.
As an example, the drift region 11 forming described second doping type in the substrate 10 of described first doping type is wrapped
Include following steps：
2-1) using ion implantation technology inject in the substrate 10 of described first doping type the second doping type from
Son, the dosage of ion implanting is 2 × 1012/cm2～8 × 1012/cm2；
2-2) form the drift region 11 of described second doping type, described second doping type of formation by high temperature knot
The junction depth of drift region 11 be 4 μm -16 μm, the length of the drift region 11 of described second doping type of formation is 10 μm of -100 μ
m.
As an example, when described first doping type is p-type, described second doping type is N-type；When described second mixes
When miscellany type is N-type, described first doping type is p-type.
As an example, refer to Fig. 7, in step 2) after be additionally included in the substrate 10 surface shape of described first doping type
The step becoming field oxide 14.
As an example, can be mixed described first using thermal oxidation method, physical vaporous deposition or chemical vapour deposition technique
Substrate 10 surface of miscellany type forms described field oxide 14 it is preferable that in the present embodiment, using thermal oxidation method described first
Substrate 10 surface of doping type forms described field oxide 14.
In step 3) in, refer to S3 step and the Fig. 8 to Fig. 9 in Fig. 4, in the drift region 11 of described second doping type
The interior buried regions 16 forming the first doping type, the buried regions 16 of described first doping type is along the drift region of described second doping type
11 length direction is divided into mutually two sections or many cross-talks buried regions 161 across a certain distance, the i.e. buried regions of described first doping type
16 are divided into mutually two sections or sub- buried regions 161 described in multistage across a certain distance along being subsequently formed the direction extremely draining from source electrode,
The doping content of each section of described sub- buried regions 161 is incomplete same.
As an example, according to patterned mask plate, (described mask plate defines the buried regions 16 of described first doping type
Shape) burying of described first doping type is formed in the drift region 11 of described second doping type using ion implantation technology
Layer 16, the dosage of ion implanting is 1 × 1012/cm2～7 × 1012/cm2；The i.e. agent of the ion implanting of each section of described sub- buried regions 161
Measure as 1 × 1012/cm2～7 × 1012/cm2.
As an example, the buried regions 16 of described first doping type being formed in the drift region 11 of described second doping type
The number of plies can set according to actual needs, the number of plies of the buried regions 16 of described first doping type can be one layer, both sides or many
Layer, wherein, the number of plies of the buried regions 16 of the first doping type described in Fig. 8 is one layer, the buried regions of the first doping type described in Fig. 9
16 number of plies is multilayer.
As an example, when the number of plies of the buried regions 16 of described first doping type is multilayer, due to the depth of ion implanting
There is direct relation with ion implantation energy, in ion implantation process, can be by adjusting the energy of ion implanting, using not
Same ion implantation energy forms the buried regions of the first doping type described in multilayer in the drift region 11 of described second doping type
16, the depth direction parallel interval of the drift region 11 along described second doping type for the buried regions 16 of the first doping type described in multilayer
Arrangement.
As an example, the spacing between the buried regions 16 of the first doping type described in neighboring layers can equal can not also
Deng not limiting herein.
As an example, the width of each section of described sub- buried regions 161 being divided in the buried regions 16 of described first doping type of each layer
Degree can identical it is also possible to different；Preferably, each section of described son being divided in the buried regions 16 of described first doping type of each layer
The width of buried regions 161 is different；It is further preferable that in the present embodiment, from described source electrode 13 to described drain electrode 12, each layer described first
In the buried regions 16 of doping type, the width of each section of described sub- buried regions 161 is gradually reduced.Certainly, in other examples, from described source
To described drain electrode 12, in the buried regions 16 of each Zeng Suoshu first doping type, the width of each section of described sub- buried regions 161 can also for pole 13
It is gradually increased.
" each section of described sub- buried regions 161 in the buried regions 16 of described first doping type of each layer it should be noted that so-called
Width " refers to along from described source electrode 13 to the size in described drain electrode 12 directions.
As an example, the hop count of buried regions 16 segmentation of described first doping type of each layer can be set according to actual needs
Fixed it is preferable that in the present embodiment, the buried regions 16 of described first doping type of each layer is along from described source electrode 13 to described drain electrode 12
Direction is divided into 2～10 sections.
As an example, from left to right, the doping content of each section of described sub- buried regions 161 can be with graded it is also possible to replace
Change, can also random change.
As an example, in the buried regions 16 of described first doping type of each layer, between adjacent each section of described sub- buried regions 161 between
Away from can equal it is also possible to.In the buried regions 16 of described first doping type of each layer, adjacent each section of described sub- buried regions 161 it
Between spacing can be set it is preferable that in the present embodiment according to actual needs, the buried regions of described first doping type of each layer
In 16, being smaller than between adjacent each section of described sub- buried regions 161 or be equal to 3 μm.
Need explanation, in other examples, can first be formed described in the drift region 11 of described second doping type
The buried regions 16 of the first doping type, then forms described field oxide 14 on substrate 10 surface of described first doping type again.
As an example, refer to Figure 10, step 3) after be additionally included in the drift region 11 of described second doping type away from
The step that the side of described drain electrode 12 forms the body area 17 of the first doping type.Specifically, using ion implantation technology described
Injection the in the substrate 10 of described first doping type of the side away from described drain electrode 12 for the drift region 11 of the second doping type
The ion of one doping type, to form the body area 17 of described first doping type in the substrate 10 of described first doping type.
It should be noted that in other examples, can also first be formed in the drift region 11 of described second doping type
The buried regions 16 of described first doping type；Then the drift region 11 of described second doping type away from described drain electrode 12 side
Form the body area 17 of the first doping type；Finally form described field oxide on substrate 10 surface of described first doping type again
14.
In step 4) in, refer to S4 step and the Figure 11 in Fig. 4, above the drift region 11 of described second doping type
Form polysilicon gate 15.
Specifically, described field oxide 14 surface above the drift region 11 of described second doping type forms polysilicon
Grid 15.
As an example, using physical vaporous deposition or chemical vapour deposition technique in the drift region of described second doping type
The described field oxide 14 surface deposit polycrystalline silicon layer of 11 tops, etches described polysilicon layer by lithographic etch process and is formed
Described polysilicon gate 15.
In step 5) in, refer to S5 step and the Figure 12 in Fig. 4, described the second of described polysilicon gate 15 side
Form drain electrode 12, in the lining of described first doping type of described polysilicon gate 15 opposite side in the drift region 11 of doping type
Form source electrode 13 in bottom 10.
As an example, using self-registered technology described second doping type in described polysilicon gate 15 side drift
In area 11, the ion of injection the first doping type is to form described drain electrode 12；Using self-registered technology in described polysilicon gate 15
Injection the first doping type to form described source electrode 13 in the substrate 10 of described first doping type of opposite side.
As an example, described source electrode 13 and described drain electrode 12 are heavily doped region, are forming described drain electrode 12 and described
During source electrode 13, the implantation dosage of described first doping type ion is 1 × 1015/cm2To 1 × 1016/cm2.
As an example, step 5) also comprise the steps afterwards：
6) form the heavily doped region 18 of the first doping type in the body area 17 of described first doping type, described first mixes
The heavily doped region 18 of miscellany type is adjacent with described source electrode 13, as shown in figure 13；Specifically, using ion implantation technology described
The ion implanting carrying out the first doping type in the body area 17 of the first doping type is to form the heavily doped of described first doping type
Miscellaneous area 18；
7) form dielectric layer 19 in described field oxide 14 and described polysilicon gate 15 surface, as shown in figure 14；Specifically
, using physical vaporous deposition or chemical vapour deposition technique in described field oxide 14 and described polysilicon gate 15 surface shape
Become described dielectric layer 19；
8) lithographic etch process is adopted to correspond to described drain electrode 12, described source electrode 13 and described first in described dielectric layer 19
The position of the heavily doped region 18 of doping type is formed with opening 191, and described opening 191 exposes described drain electrode 12, described source electrode
13 and the heavily doped region 18 of described first doping type, as shown in figure 15；
9) corresponding to described drain electrode 12 described opening 191 in and described dielectric layer 19 surface formation drain electrode 20,
Form source electrode in the described opening 191 corresponding to described source electrode 13 and the heavily doped region 18 of described first doping type
21, as shown in figure 16；Specifically, described drain electrode 12, described is corresponded to using physical vaporous deposition or chemical vapour deposition technique 9
The interior and described dielectric layer 19 surface deposition of electrode material of opening 191 of the heavily doped region 18 of source electrode 13 and described first doping type
Layer, forms described drain electrode 20 and described source electrode by lithographic etch process.
The preparation method of the described high-voltage LDMOS device of the present embodiment is passed through 16 points of the buried regions of described first doping type
It is placed in the drift region 11 of the second doping type to section, under high pressure so that described high-voltage LDMOS device obtains multi-peak surface
Electric Field Distribution, due to pressure be the integration along depletion region direction for the electric field, that is, along from described source electrode 13 to described drain electrode 12 directions
Integration, therefore, the distribution of multi-peak surface field is than few peak surface electric field of high-voltage LDMOS device of the prior art
The breakdown voltage of distribution gets a promotion, that is, under the conditions of pressure on an equal basis, the high-voltage LDMOS that the preparation method in the present embodiment makes
Device can have shorter drift region length Ldrift, higher drift region concentration, thus reduce leading of high-voltage LDMOS device
Energising resistance, reduces device area；In the present embodiment, described drift region length LdriftFor 10 μm -100 μm.
In sum, the present invention provides a kind of high-voltage LDMOS device and preparation method thereof, described high-voltage LDMOS device bag
Include：The substrate of the first doping type；The drift region of the second doping type, in the substrate of described first doping type；Drain electrode,
In the drift region of described second doping type；Source electrode, in the substrate of described first doping type；Polysilicon gate,
Substrate surface positioned at described first doping type between described drain electrode and described source electrode；The buried regions of the first doping type, position
In the drift region of described second doping type between described source electrode and described drain electrode；The buried regions edge of described first doping type
It is divided into mutually two sections or many cross-talks buried regions across a certain distance, each section of described sub- buried regions from the direction of described source electrode extremely described drain electrode
Doping content incomplete same.The present invention by being placed in the drift of the second doping type by the buried regions piecewise of the first doping type
Move so that described high-voltage LDMOS device obtains multi-peak surface electric field distribution in area, and have two conductive channels；With tradition
High-voltage LDMOS device compare, the high-voltage LDMOS device of the present invention obtain identical pressure on the premise of, have shorter drift
Move section length and higher drift region concentration, thus having lower conducting resistance.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any ripe
The personage knowing this technology all can carry out modifications and changes without prejudice under the spirit and the scope of the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete with institute under technological thought without departing from disclosed spirit such as
All equivalent modifications becoming or change, must be covered by the claim of the present invention.
Claims (19)
1. a kind of high-voltage LDMOS device is it is characterised in that described high-voltage LDMOS device includes：
The substrate of the first doping type；
The drift region of the second doping type, in the substrate of described first doping type；
Drain electrode, in the drift region of described second doping type；
Source electrode, in the substrate of described first doping type；
Polysilicon gate, positioned at the substrate surface of described first doping type between described drain electrode and described source electrode；
The buried regions of the first doping type, the drift region of described second doping type between described source electrode and described drain electrode
Interior；The buried regions of described first doping type is divided into mutually two sections across a certain distance along the direction from described source electrode to described drain electrode
Or many cross-talks buried regions, the doping content of each section of described sub- buried regions is incomplete same.
2. high-voltage LDMOS device according to claim 1 it is characterised in that：Described high-voltage LDMOS device includes multilayer institute
State the buried regions of the first doping type, the depth of the drift region along described second doping type for the buried regions of the first doping type described in multilayer
The parallel interval arrangement of degree direction.
3. high-voltage LDMOS device according to claim 2 it is characterised in that：First doping type described in neighboring layers
Spacing between buried regions is equal.
4. high-voltage LDMOS device according to claim 2 it is characterised in that：First doping type described in neighboring layers
Spacing between buried regions.
5. high-voltage LDMOS device according to any one of claim 1 to 4 it is characterised in that：Extremely described from described source electrode
Drain electrode, in the buried regions of described first doping type of each layer, the width of each cross-talk buried regions is gradually reduced.
6. high-voltage LDMOS device according to any one of claim 1 to 4 it is characterised in that：Each layer described first adulterates
In the buried regions of type, the spacing between adjacent each cross-talk buried regions is equal.
7. high-voltage LDMOS device according to any one of claim 1 to 4 it is characterised in that：Each layer described first adulterates
Spacing in the buried regions of type, between adjacent each cross-talk buried regions.
8. high-voltage LDMOS device according to any one of claim 1 to 4 it is characterised in that：Each layer described first adulterates
In the buried regions of type, being smaller than between adjacent each cross-talk buried regions or be equal to 3 μm.
9. high-voltage LDMOS device according to claim 1 it is characterised in that：Described high-voltage LDMOS device also includes：
Field oxide, between the substrate and described polysilicon gate of described first doping type, and be located at described drain electrode with
The substrate surface of described first doping type between described source electrode；
The body area of the first doping type, in the substrate of described first doping type, and is located at described second doping type
Drift region is away from the side of described drain electrode；Described source electrode is located in the body area of described first doping type；
The heavily doped region of the first doping type, in the body area of described first doping type and adjacent with described source electrode.
10. high-voltage LDMOS device according to claim 9 it is characterised in that：Described high-voltage LDMOS device also includes；
Dielectric layer, positioned at described field oxide and described polysilicon gate surface, described dielectric layer corresponds to described drain electrode, described
The position of the heavily doped region of source electrode and described first doping type is formed with opening, and described opening exposes described drain electrode, described
Source electrode and the heavily doped region of described first doping type；
Drain electrode, in described opening and described dielectric layer surface, and is contacted with described drain electrode；
Source electrode, in described opening and described dielectric layer surface, and with described source electrode and described first doping type
Heavily doped region contacts.
A kind of 11. preparation methods of high-voltage LDMOS device are it is characterised in that described preparation method comprises the steps：
1) substrate of the first doping type is provided；
2) form the drift region of the second doping type in the substrate of described first doping type；
3) form the buried regions of the first doping type in the drift region of described second doping type, the burying of described first doping type
Layer is divided into mutually two sections or many cross-talks buried regions across a certain distance along the length direction of the drift region of described second doping type, respectively
The doping content of the sub- buried regions of Duan Suoshu is incomplete same；
4) form polysilicon gate above the drift region of described second doping type；
5) form drain electrode in the drift region of described second doping type of described polysilicon gate side, in described polysilicon gate
Form source electrode in the substrate of described first doping type of pole opposite side.
The preparation method of 12. high-voltage LDMOS devices according to claim 11 it is characterised in that：Step 2) in, described
The drift region forming described second doping type in the substrate of the first doping type comprises the steps：
The ion of the second doping type 2-1) is injected in the substrate of described first doping type using ion implantation technology；
2-2) form the drift region of described second doping type by high temperature knot.
The preparation method of 13. high-voltage LDMOS devices according to claim 12 it is characterised in that：Step 2-1) in, ion
The dosage of injection is 2 × 1012/cm2～8 × 1012/cm2；Step 2-2) in, the drift region of described second doping type of formation
Junction depth be 4 μm -16 μm, the length of the drift region of described second doping type of formation is 10 μm -100 μm.
The preparation method of 14. high-voltage LDMOS devices according to claim 11 it is characterised in that：Step 3) in, using from
Sub- injection technology forms each cross-talk buried regions of described first doping type, each section of institute in the drift region of described second doping type
The dosage stating the ion implanting of sub- buried regions is 1 × 1012/cm2～7 × 1012/cm2.
The preparation method of 15. high-voltage LDMOS devices according to claim 14 it is characterised in that：In ion implantation process
In, form each section of the first doping type described in multilayer in the drift region of described second doping type using ion implantation technology
Sub- buried regions, the depth direction parallel interval of the drift region along described second doping type for the buried regions of the first doping type described in multilayer
Arrangement.
The preparation method of 16. high-voltage LDMOS devices according to any one of claim 11 to 15 it is characterised in that：From
To described drain electrode, in the buried regions of described first doping type of each layer, the width of each cross-talk buried regions is gradually reduced described source electrode.
The preparation method of 17. high-voltage LDMOS devices according to claim 11 it is characterised in that：In step 2) and step
3), between, it is additionally included in the step that the substrate surface of described first doping type forms field oxide, now, step 4) in, institute
State polysilicon gate and be located at the described field oxide surface above the drift region of described second doping type.
The preparation method of 18. high-voltage LDMOS devices according to claim 17 it is characterised in that：In step 3) and step
4) between, it is additionally included in the body away from side formation first doping type of described drain electrode for the drift region of described second doping type
The step in area；Step 5) in, described source electrode is located in the body area of described first doping type.
The preparation method of 19. high-voltage LDMOS devices according to claim 18 it is characterised in that：Step 5) also wrap afterwards
Include following steps：
6) form the heavily doped region of the first doping type in the body area of described first doping type, described first doping type
Heavily doped region is adjacent with described source electrode；
7) form dielectric layer in described field oxide and described polysilicon gate surface；
8) the position shape of the heavily doped region of described drain electrode, described source electrode and described first doping type is corresponded in described dielectric layer
Become to have opening, described opening exposes the heavily doped region of described drain electrode, described source electrode and described first doping type；
9) in the described opening corresponding to described drain electrode and described dielectric layer surface formed drain electrode, corresponding to described source
Form source electrode in the described opening of the heavily doped region of pole and described first doping type.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493248A (en) * | 2018-03-05 | 2018-09-04 | 上海华虹宏力半导体制造有限公司 | Level shift structure and its manufacturing method |
| CN108717946A (en) * | 2018-07-05 | 2018-10-30 | 长沙理工大学 | A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device |
| CN111146281A (en) * | 2018-11-05 | 2020-05-12 | 上海晶丰明源半导体股份有限公司 | Semiconductor device structure and preparation method thereof |
| CN111697058A (en) * | 2020-06-09 | 2020-09-22 | 杰华特微电子（杭州）有限公司 | Semiconductor device with a plurality of transistors |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007324361A (en) * | 2006-05-31 | 2007-12-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and its method for manufacturing |
| US20110233672A1 (en) * | 2010-03-29 | 2011-09-29 | Yih-Jau Chang | Semiconductor structure and fabrication method thereof |
| CN102403350A (en) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor) high-voltage device structure and preparation method |
| CN103904121A (en) * | 2014-03-31 | 2014-07-02 | 电子科技大学 | Lateral high-voltage device and manufacturing method thereof |
| CN206179871U (en) * | 2016-10-31 | 2017-05-17 | 上海晶丰明源半导体股份有限公司 | High -voltage LDMOS (high -voltage -lateral diffused metal oxide semiconductor) component |
-
2016
- 2016-10-31 CN CN201610929239.6A patent/CN106409883A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007324361A (en) * | 2006-05-31 | 2007-12-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and its method for manufacturing |
| US20110233672A1 (en) * | 2010-03-29 | 2011-09-29 | Yih-Jau Chang | Semiconductor structure and fabrication method thereof |
| CN102403350A (en) * | 2010-09-07 | 2012-04-04 | 上海华虹Nec电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor) high-voltage device structure and preparation method |
| CN103904121A (en) * | 2014-03-31 | 2014-07-02 | 电子科技大学 | Lateral high-voltage device and manufacturing method thereof |
| CN206179871U (en) * | 2016-10-31 | 2017-05-17 | 上海晶丰明源半导体股份有限公司 | High -voltage LDMOS (high -voltage -lateral diffused metal oxide semiconductor) component |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493248A (en) * | 2018-03-05 | 2018-09-04 | 上海华虹宏力半导体制造有限公司 | Level shift structure and its manufacturing method |
| CN108717946A (en) * | 2018-07-05 | 2018-10-30 | 长沙理工大学 | A kind of high voltage with segmentation p type buried layer is low than leading lateral super junction power device |
| CN111146281A (en) * | 2018-11-05 | 2020-05-12 | 上海晶丰明源半导体股份有限公司 | Semiconductor device structure and preparation method thereof |
| CN112018176A (en) * | 2019-05-30 | 2020-12-01 | 苏州捷芯威半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN112349764A (en) * | 2019-08-08 | 2021-02-09 | 天津大学 | RESURF LDMOS device with field limiting ring structure |
| CN111697058A (en) * | 2020-06-09 | 2020-09-22 | 杰华特微电子（杭州）有限公司 | Semiconductor device with a plurality of transistors |
| CN111697058B (en) * | 2020-06-09 | 2023-06-23 | 杰华特微电子股份有限公司 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
| CN115020478B (en) * | 2022-08-08 | 2022-10-04 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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