CN106027349B - A kind of PCI-E bus interface transmission card and the data transmission method based on the transmission card - Google Patents
A kind of PCI-E bus interface transmission card and the data transmission method based on the transmission card Download PDFInfo
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- CN106027349B CN106027349B CN201610278267.6A CN201610278267A CN106027349B CN 106027349 B CN106027349 B CN 106027349B CN 201610278267 A CN201610278267 A CN 201610278267A CN 106027349 B CN106027349 B CN 106027349B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40123—Interconnection of computers and peripherals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/6215—Individual queue per QOS, rate or priority
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Abstract
The present invention proposes a kind of PCI-E bus interface transmission card and the data transmission method based on the transmission card.The transmission card includes PCI-E interface IP kernel, register, register Read-write Catrol module, TLP data packet analysis module, sending module and/or receiving module；Sending module include transmitting line and send DMA control module, receiving module include receiving circuit and receive DMA control module, transmitting line, receiving circuit quantity be nonnegative integer；PCI-E interface IP kernel and TLP data packet analysis module communicate to connect, TLP data packet analysis the first output end of module connects transmitting line input terminal, transmitting line output end is connect with transmitting line, TLP data packet analysis module second output terminal connects register Read-write Catrol module input, Read-write Catrol module is bi-directionally connected with register, and register is bi-directionally connected with DMA control module is sent.The transmission card can fast and accurately carry out sending and receiving data.
Description
Technical field
The present invention relates to computer fields, and in particular to a kind of PCI-E bus interface transmission card and based on the transmission card
Data transmission method.
Background technique
PCI-Express is newest bus and interface standard, often referred to simply as PCI-E, is by Intel in 2001
It proposes.PCI-E belongs to the point-to-point binary channels high bandwidth transmission of high speed serialization, and the equipment distribution connected exclusively enjoys bandwidth chahnel,
Bus bandwidth is not shared, mainly supports active power management, error reporting, end-to-end reliability transmission, hot plug and clothes
The functions such as business quality (QOS).
PCI-E uses at present the point-to-point serial connection of prevalence in the industry, compared with PCI and the computer bus of more early stage
Shared and framework, each equipment has the dedicated connection of oneself, do not need to entire bus request bandwidth, and can be number
It is increased to a very high frequency according to transmission rate, reaches the high bandwidth that PCI cannot be provided.Relative to traditional PCI bus in list
One-way transmission can only be realized in a period of time, double either simplex connection of PCI-E can provide higher efficiency of transmission and quality, it
Between difference it is similar with full duplex with half-duplex.The main advantage of PCI-E is exactly message transmission rate height, and there are also phases
When big development potentiality.
But at present PCI-E data transmission bauds still limited by transmission card, thus lead system data transmission cannot
Preferably play the high advantage of its transmission rate.
Also, it when investigating the Optimality of transmission of data, other than the comparison to message transmission rate, also relates to pair
The safety of data is considered.PCI-E interface data transmission device is directed in Information Security at present, is mostly to pass through letter
Single transmission data-interface receives data-interface, sends caching, receiving caching and data command configuration interface etc. is realized pair
The monitoring of transmission and the safety of data, as shown in 2013106645871 disclosure of that of application number.However, in information
Security requirement higher and higher today, this data transmission device are no longer satisfied people and want to the height of Information Security
It asks.
Summary of the invention
In order to overcome above-mentioned defect existing in the prior art, the object of the present invention is to provide a kind of security performance height, energy
The PCI-E bus interface transmission card quickly completely carried out data transmission and the data transmission method based on the transmission card.
In order to realize above-mentioned purpose of the invention, the present invention provides a kind of PCI-E bus interface transmission cards, including PCI-
E interface IP kernel and register further include register Read-write Catrol module, TLP data packet analysis module, sending module and/or are connect
Receive module；
The sending module include transmitting line and send DMA control module, the receiving module include receiving circuit and
Receive DMA control module, the transmitting line, receiving circuit quantity be nonnegative integer；
The PCI-E interface IP kernel and the TLP data packet analysis module communicate to connect, the TLP data packet analysis mould
The first output end of block connects the transmitting line input terminal, and the transmitting line output end is connect with transmitting line, the TLP number
Connect the register Read-write Catrol module input according to packet analysis module second output terminal, the Read-write Catrol module with it is described
Register is bi-directionally connected, and the register is bi-directionally connected with the transmission DMA control module；
The receiving circuit input terminal is connect with receiving circuit, and the receiving circuit output end connects the reception DMA control
Module input processed, the DMA control module are bi-directionally connected with the register, and the reception DMA control module output end connects
It is connected to the PCI-E interface IP kernel；
When data are sent, host first by the buffer area for needing the data sent to be written in memory, then will include number
It is written in the register according to the control word that length, log-on data send mark；The transmission DMA control module passes through PCI-E
Interface sends read request TLP data packet to the TLP data packet analysis module, and the TLP data packet analysis module judgement is received
To TLP data packet whether be read request TLP data packet, if it is, the register Read-write Catrol module is according to read request
The data in the readout register of address in TLP data packet, and pass through PCI-E interface to plus the packet header for running through TLP data
It is then forwarded to the TLP data packet analysis module, whether the TLP data packet analysis module judges received TLP data packet
To run through TLP data packet, data transmission is carried out if it is, this is run through TLP data packet and is sent to the transmitting line；
When data receiver, the data received are sent to the reception DMA control module, institute by the data reception lines
It states and receives DMA control module by PCI-E interface transmission write request TLP data packet to the TLP data packet analysis module, institute
State whether the received TLP data packet of TLP data packet analysis module judgement is write request TLP data packet, if it is, described
Register Read-write Catrol module reads address and data in write request TLP data packet, and writes data into address part and refer to
In fixed register, host memory is then written by PCI-E interface.
By the analytical judgment of TLP data packet analysis module, can be accurately judged to that the transmission card needs to be implemented is to send
Or received task, and combine register Read-write Catrol module, send DMA control module and receive DMA control module and make
The transmission card can more fast and accurately carry out sending and receiving data.Simultaneously as point of TLP data packet analysis module
Analysis judgement ensure that the safety of data, to write request TLP data packet, read request TLP data packet and run through TLP data packet
The identification and processing of these three data packets, ensure that the safety of data.
Further, which further includes that TLP data packet receives buffer area, and the TLP data packet receives buffering and distinguishes
It is not communicated to connect with the PCI-E interface IP kernel and the TLP data packet analysis module.TLP data packet receives buffer area and is used for
The TLP data packet received by PCI-E interface is cached, the loss of TLP data packet is avoided, ensure that and receive or send number
According to integrality.
Further, which further includes that the first TLP data packet sends buffer area, the 2nd TLP data packet sends buffering
Area and the 3rd TLP data packet send buffer area, and the first TLP data packet sends buffer area and reads and writes control with the register respectively
Molding block and the communication connection of PCI-E interface IP kernel, the 2nd TLP data packet send buffer area and control respectively with the transmission DMA
Molding block and the communication connection of PCI-E interface IP kernel, the 3rd TLP data packet send buffer area and control respectively with the reception DMA
Molding block and the communication connection of PCI-E interface IP kernel.
What the first TLP data packet sent that buffer cache corresponds to register read request runs through TLP data packet, the 2nd TLP
Data packet sends the TLP data packet that buffer cache sends DMA request, i.e. read request TLP data packet, the 3rd TLP data packet hair
The TLP data packet for sending buffer cache to receive DMA request, i.e. write request TLP data packet.It ensure that mass data receive or
The integrality that data are transmitted when transmission, avoids the loss of data.
Further, which further includes sending buffer area selecting module, and the first TLP data packet sends buffering
The output end that area, the 2nd TLP data packet transmission buffer area and the 3rd TLP data packet send buffer area is connected to described send and delays
Area's selecting module input terminal is rushed, the transmission buffer area selecting module and the PCI-E interface IP kernel communicate to connect；
The transmission buffer area selecting module is controlled to send the first TLP data packet according to priority criteria and be buffered
The data packet that area, the 2nd TLP data packet are sent in buffer area and the 3rd TLP data packet transmission buffer area is transferred to PCIE interface.
Priority criteria is preset criterion, selects read request according to the priority level of data sent and received
TLP data packet, write request TLP data packet and run through the sequencing that TLP data packet is admitted to PCI-E interface.
Further, the transmitting line includes running through TLP data packet handing module, transmitting line buffer area, coding
Device and transmission LVDS interface；
TLP data packet handing module input terminal is run through described in the connection of the first output end of the TLP data packet analysis module,
Described to run through TLP data packet handing module output end connection transmitting line buffer area input terminal, the transmitting line is slow
It rushes area's output end and connects the encoder input terminal, the encoder is connected by the transmission LVDS interface and the transmitting line
It connects；
The TLP data packet handing module that runs through is by the data run through in TLP data packet the write-in transmitting line
In buffer area, then encoded and be inserted into control character by the encoder, then by the transmission LVDS interface to data into
It is sent in transmitting line after row serial to parallel conversion.
Running through TLP data packet handing module, transmitting line buffer area, encoder and transmission LVDS interface ensure that data
Integrality and confidentiality in transmission process.
Further, the receiving circuit includes receiving LVDS interface, decoder and receiving circuit buffer area；
The reception LVDS interface is connect with receiving circuit and the decoder respectively, and the decoder output connects institute
Receiving circuit buffer area input terminal is stated, receiving circuit buffer area output end is connected to the reception DMA control module input
End；
The reception LVDS interface receives data from receiving circuit, and serial to parallel conversion and control character are carried out to it
Detection, control character sends the data to the decoder and carries out data decoding after detecting, then decoded data are sent
To in the receiving circuit buffer area and to the reception DMA control module transmitting line data accepted flag, the reception DMA
For control module after detecting the received mark of track data effectively, starting receives DMA process, transfers data in host
In the buffer area deposited.
Receive LVDS interface, decoder and receiving circuit buffer area ensure that integrality in DRP data reception process and accurate
Property.
There is the transmission card independent hardware to migrate control logic, no OS and any " soft " control, autonomous completion data
Migration, system is only responsible for the buffer area write data in the transmission card, automatically complete according to hardware control logic by the transmission card
At Data Migration, automaticdata completeness check is realized at the both ends of the transmission card.Carried out data transmission based on the transmission card, because
Without data exchange and access based on network protocol or other modes between sending device and receiving device, thus from hard
Part level ensure that the security isolation between sending device and receiving device.
Based on above-mentioned PCI-E bus interface transmission card, the invention also provides a kind of data transmission methods.
The first transmission card and the second transmission card are used in data transmission procedure, first transmission card and the second transmission card are equal
For the PCI-E bus interface transmission card, first transmission card and the communication connection of the second transmission card, the data transmission method
The following steps are included:
When S1, data are sent, the data of transmission are first written in the buffer area in memory by sending device, then will include
The control word that data length, log-on data send mark is write in the transmission control register of the first transmission card；
S2, the first transmission card judge the transmitting line of the first transmission card after detecting that log-on data sends mark effectively
Whether connect and whether the transmitting line of the first transmission card caching can be used, the log-on data transmission process if available, otherwise etc.
Route to be sent and caching are available；
After S3, data transmission procedure starting, start DMA transfer, the transmission DMA control module of the first transmission card will be comprising reading
The read request TLP data packet of the data address and data length that take is sent to the TLP data of the first transmission card by PCI-E interface
Packet analysis module；
S4, the TLP data packet that the TLP data packet analysis module judgement of the first transmission card is received are specially read request TLP
Data packet still runs through TLP data packet, if it is read request TLP data packet, thens follow the steps S5, if it is running through TLP
Data packet thens follow the steps S6；
S5, the first transmission card register Read-write Catrol module according in read request TLP data packet address read deposit
Data in device, and the TLP data packet of the first transmission card is sent to plus the packet header for running through TLP data by PCI-E interface
Then analysis module executes step S4；
The TLP data packet analysis module hair that will run through TLP data packet and be sent to the first transmission card of S6, the first transmission card
Line sending road carries out data transmission；
S7, second transmission card receive data, and the receiving circuit of second transmission card receives data, and will
The data received are sent to the reception DMA control module of the second transmission card；
S8, the second transmission card reception DMA control module by PCI-E interface send write request TLP data packet to second
The TLP data packet analysis module of transmission card；
Whether S9, the TLP data packet that the TLP data packet analysis module judgement of the second transmission card is received are write request
TLP data packet, if so, thening follow the steps S10；
S10, the second transmission card register Read-write Catrol module read write request TLP data packet in address and data,
And write data into the specified register of address part, receiving device memory is then written by PCI-E interface.
The data transmission method can fast and accurately send and receive data, ensure that the quick of data
Property, integrality, accuracy and security transmissions.
Using this data transmission method the network of sending device and receiving device is not directly connected, has blocked two sides
Internetwork TCP/IP connection is allowed to not can be carried out network protocol communication, has carried out way gate technology control to the data of transmitting
System, thoroughly prevents data backflow.
Further, in the step S3, before DMA transfer, DMA control module is sent according to data length and calculates need
Carry out the number of DMA transfer；
In the step S7, before receiving DMA control module reception data, it is long according to data to receive DMA control module
Degree calculates the number of DMA transfer.It ensure that data can be completely transmitted or received, the integrality of data ensure that.
Further, when sending data, transmitting line need to be encoded to data and be inserted into alignment, beginning or end
Control character；
When data receiver, receiving circuit need to carry out the detection and decoding of control character to data.It ensure that the peace of data
Full property and accuracy.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is transmission card structural block diagram；
Fig. 2 is that data send DMA flow chart；
Fig. 3 is route side data transmission flow figure；
Fig. 4 is line side data receiver flow chart；
Fig. 5 is data receiver DMA process；
Fig. 6 is to receive TLP data packet process flow diagram；
Fig. 7 is data transmission schematic diagram.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In the description of the present invention, unless otherwise specified and limited, it should be noted that term " installation ", " connected ",
" connection " shall be understood in a broad sense, for example, it may be mechanical connection or electrical connection, the connection being also possible to inside two elements can
, can also indirectly connected through an intermediary, for the ordinary skill in the art to be to be connected directly, it can basis
Concrete condition understands the concrete meaning of above-mentioned term.
As shown in Figure 1, the present invention provides a kind of PCI-E bus interface transmission card, including PCI-E interface IP kernel, deposit
Device, register Read-write Catrol module, TLP data packet analysis module, sending module and/or receiving module.The sending module packet
It includes transmitting line and sends DMA control module, the receiving module includes receiving circuit and reception DMA control module, the hair
Line sending road, receiving circuit quantity be nonnegative integer.
PCI-E interface IP kernel is used to complete the physical layer, data link layer and transaction layer of PCI-E interface
The processing of (Transaction Layer Protocol, TLP) three layer protocols.Required for register transmits for storing data
Control and status information, including host receive and dispatch buffer zone address, send and receive control word, send and receive status word etc..
PCI-E interface IP kernel and TLP data packet analysis module communicate to connect, TLP data packet analysis the first output end of module
Transmitting line input terminal is connected, transmitting line output end is connect with transmitting line, and TLP data packet analysis module second output terminal connects
Register Read-write Catrol module input is connect, Read-write Catrol module is bi-directionally connected with register, and register and transmission DMA control mould
Block is bi-directionally connected.
Receiving circuit input terminal is connect with receiving circuit, and the connection of receiving circuit output end receives DMA control module input terminal,
DMA control module is bi-directionally connected with register, is received DMA control module output end and is connected to PCI-E interface IP kernel.
In order to guarantee that the integrality and accuracy of data transmission, read request TLP data packet run through TLP data packet and write
Request TLP data packet can buffer into TLP data packet receive buffer area, TLP data packet receive buffer area respectively with PCI-E interface IP
Core and the communication connection of TLP data packet analysis module.
Meanwhile the transmission card further includes sending buffer area selecting module, the transmission of the first TLP data packet buffer area, the 2nd TLP
Data packet sends buffer area and the 3rd TLP data packet and sends buffer area, the first TLP data packet send buffer area respectively with register
Read-write Catrol module and the communication connection of PCI-E interface IP kernel, the 2nd TLP data packet send buffer area and control respectively with transmission DMA
Module and PCI-E interface IP kernel communication connection, the 3rd TLP data packet send buffer area respectively with receive DMA control module and
The communication connection of PCI-E interface IP kernel.
What the first TLP data packet sent that buffer cache corresponds to register read request runs through TLP data packet, the 2nd TLP
Data packet sends the TLP data packet that buffer cache sends DMA request, i.e. read request TLP data packet, the 3rd TLP data packet hair
The TLP data packet for sending buffer cache to receive DMA request, i.e. write request TLP data packet.First TLP data packet transmission buffer area,
2nd TLP data packet sends buffer area and the output end of the 3rd TLP data packet transmission buffer area is connected to the choosing of transmission buffer area
Module input is selected, buffer area selecting module is sent and PCI-E interface IP kernel communicates to connect.
Buffer area selecting module is sent to be controlled according to priority criteria by the transmission of the first TLP data packet buffer area, the 2nd TLP
The data packet that data packet is sent in buffer area and the 3rd TLP data packet transmission buffer area is transferred to PCIE interface.
Host to the control of transmission card is realized by the control register group in read-write card, and read write command is all logical
The TLP data packet for crossing PCI-E interface is sent to transmission card.In addition, the data requested during sending DMA are also to pass through PCI-E
The TLP packet that runs through of interface is transmitted.Transmission card only handles these three types TLP data packet, i.e., read request TLP data packet, write and ask
It seeks TLP data packet, run through TLP data packet, other packets are not dealt with.
As shown in fig. 6, which kind of the judgement of analysis packet header is first after transmission card receives TLP data packet from PCI-E interface
TLP data packet.For write request TLP data packet, transmission card by packet address and data take out, and write data into address
In the specified register in part.For read request TLP data packet, transmission card takes out the address in packet, reads post accordingly accordingly
The data of storage, and plus the packet header for running through TLP, it is written to the first TLP data packet and sends in buffer area, by PCI-E interface
Pass to host.For running through TLP data packet, transmission card buffers the transmitting line that the data in packet are written to line side
Qu Zhong.
When data are sent, host first by the buffer area for needing the data sent to be written in memory, then will include number
It is sent in the control word write-in register of mark according to length, log-on data.DMA control module is sent to send by PCI-E interface
Read request TLP data packet gives the TLP data packet analysis module, and TLP data packet analysis module judges received TLP data packet
It whether is read request TLP data packet, if it is, register Read-write Catrol module is according to the address in read request TLP data packet
Data in readout register, and TLP data packet is then forwarded to by PCI-E interface to plus the packet header for running through TLP data
Analysis module, TLP data packet analysis module judge received TLP data packet whether be run through TLP data packet, if so,
This is then run through into TLP data packet and is sent to transmitting line progress data transmission.
When data receiver, the data received are sent to and receive DMA control module by data reception lines, receive DMA control
Molding block sends write request TLP data packet by PCI-E interface and gives TLP data packet analysis module, TLP data packet analysis module
Whether the received TLP data packet of judgement is write request TLP data packet, if it is, register Read-write Catrol module is read
Address and data in write request TLP data packet, and write data into the specified register of address part, then pass through
Host memory is written in PCI-E interface.
In concrete application, transmitting line may include running through TLP data packet handing module, transmitting line buffer area, coding
Device and transmission LVDS interface.The connection of TLP data packet analysis the first output end of module runs through the input of TLP data packet handing module
End runs through TLP data packet handing module output end connection transmitting line buffer area input terminal, transmitting line buffer area output end
Encoder input terminal is connected, encoder is connect by sending LVDS interface with transmitting line.Run through TLP data packet processing mould
The data run through in TLP data packet are written in transmitting line buffer area block, are then encoded by encoder and are inserted into control
Character processed, then be sent in transmitting line after carrying out serial to parallel conversion to data by transmission LVDS interface.
Receiving circuit includes receiving LVDS interface, decoder and receiving circuit buffer area.Receive LVDS interface respectively with connect
Take-up road is connected with decoder, and decoder output connects receiving circuit buffer area input terminal, receiving circuit buffer area output end
It is connected to and receives DMA control module input terminal.It receives LVDS interface and receives data from receiving circuit, and it is gone here and there simultaneously
The detection of transformation and control character, control character send the data to decoder and carry out data decoding after detecting, then will decoding
Data afterwards are sent in receiving circuit buffer area and to DMA control module transmitting line data accepted flag are received, and receive DMA
For control module after detecting the received mark of track data effectively, starting receives DMA process, transfers data in host
In the buffer area deposited.
A kind of data transmission method based on above-mentioned PCI-E transmission card, as shown in fig. 7, using the in data transmission procedure
One transmission card and the second transmission card, the first transmission card and the second transmission card are above-mentioned PCI-E bus interface transmission card, institute
The first transmission card and the communication connection of the second transmission card are stated, method includes the following steps:
When S1, data are sent, as shown in Fig. 2, Fig. 3 and Fig. 6, the data of transmission are first written in memory by sending device
In buffer area, then the control word for sending mark comprising data length, log-on data is write to the transmission control deposit of transmission card
In device.
S2, the first transmission card judge the transmitting line of the first transmission card after detecting that log-on data sends mark effectively
Whether connect and whether the transmitting line of the first transmission card caching can be used, the log-on data transmission process if available, otherwise etc.
Route to be sent and caching are available, start data when connection and available transmitting line caching and send.
After data transmission procedure starting, according to the facilities of sending device, a data transmission may need multiple DMA
It could complete, therefore, the transmission DMA control module of transmission card calculates time for needing to carry out DMA transfer according to data length first
Number, then starts DMA transfer again.
When S3, DMA transfer, the transmission DMA control module of the first transmission card is long by the data address comprising reading and data
The read request TLP data packet of degree is sent to the TLP data packet analysis module of the first transmission card by PCI-E interface.
S4, the TLP data packet that the TLP data packet analysis module judgement of the first transmission card is received are specially read request TLP
Data packet still runs through TLP data packet, if it is read request TLP data packet, thens follow the steps S5, if it is running through TLP
Data packet thens follow the steps S6.
S5, the first transmission card register Read-write Catrol module according in read request TLP data packet address read deposit
Data in device, and the TLP data packet of the first transmission card is sent to plus the packet header for running through TLP data by PCI-E interface
Then analysis module executes step S4.
The TLP data packet analysis module hair that will run through TLP data packet and be sent to the first transmission card of S6, the first transmission card
Line sending road carries out data transmission.
When data are from the transmitting line that sending device is transferred to the first transmission card, the transmitting line of the first transmission card
TLP data packet handing module is run through to buffer the transmitting line that the first transmission card is written in the data run through in TLP data packet
Qu Zhong starts route after all data after in the transmitting line buffer area that sending device is transferred to the first transmission card and passes
It is defeated.Serial transmission mode, electric interfaces LVDS are used on transmission line.In order to enable receiving end to be properly received, on route
Data need to be encoded by 8B10B.In line idle, transmission carries out control word alignment in serial to parallel conversion for receiving end on route
Control word.When data transmission starts, first sends data packet and start control character, then transmit data.After data end of transmission,
Data packet finishing control character is sent, designation date is transmitted.
S7, the second transmission card receive data, as Figure 4-Figure 6, firstly, the reception LVDS interface of the second transmission card
Serial to parallel conversion is carried out to data are received, it needs to be determined that the beginning boundary of word, this word sent by detection transmitting terminal in transformation
Alignment control word is realized.If not detecting the control word, control serial-parallel converter slides one, so repeats until detection
To word alignment control word.Since in line idle, transmitting terminal persistently sends the control word, if receiving continuously to monitor
The control word shows that connection is normal, and the word of serial to parallel conversion has been aligned.
After word alignment, line receiver part continues to monitor packet and starts control word, such as detects, shows that subsequent word is effective
Data.Receiving end receives the data, and carries out 8B10B decoding, and the data after decoding are written to receiving circuit buffer area.It is receiving
During data, need to be made whether as the detection of end-of-packet control word each reception data.It such as detects, then data
End-of-packet, data receive control register from finishing receiving on route, by the length write-in of data, and data are received
Flag set.
The transmission of data may need multiple DMA process, so needing first to calculate the number of DMA process.It is receiving
In the available situation in equipment buffer area, the data of DMA transfer are encapsulated into write request TLP packet by the second transmission card passes through PCIE
Host memory is written in interface.
After detecting the received mark of track data effectively, starting connects the reception DMA control module of second transmission card
DMA process is received, the reception DMA that the data received are sent to the second transmission card is controlled mould by the receiving circuit of the second transmission card
Block.The transmission of data may need multiple DMA process, so needing first to calculate the number of DMA process.
S8, the second transmission card reception DMA control module by PCI-E interface send write request TLP data packet to second
The TLP data packet analysis module of transmission card.
Whether S9, the TLP data packet that the TLP data packet analysis module judgement of the second transmission card is received are write request
TLP data packet, if it is, the register Read-write Catrol module of the second transmission card reads the address in write request TLP data packet
And data, and write data into the specified register of address part, then receiving device memory is written by PCI-E interface
In.
Here sending device and receiving device can be host, be also possible to server.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that: not
A variety of change, modification, replacement and modification can be carried out to these embodiments in the case where being detached from the principle of the present invention and objective, this
The range of invention is defined by the claims and their equivalents.
Claims (9)
1. a kind of PCI-E bus interface transmission card, including PCI-E interface IP kernel and register, which is characterized in that further include deposit
Device Read-write Catrol module, TLP data packet analysis module, sending module and receiving module；
The sending module includes transmitting line and sends DMA control module, and the receiving module includes receiving circuit and reception
DMA control module, the transmitting line, receiving circuit quantity be nonnegative integer；
The PCI-E interface IP kernel and the TLP data packet analysis module communicate to connect, the TLP data packet analysis module the
One output end connects the transmitting line input terminal, and the TLP data packet analysis module second output terminal connects the register
Read-write Catrol module input, the Read-write Catrol module are bi-directionally connected with the register, the register and the transmission
DMA control module is bi-directionally connected；
The receiving circuit output end connects the reception DMA control module input terminal, the DMA control module and the deposit
Device is bi-directionally connected, and the reception DMA control module output end is connected to the PCI-E interface IP kernel；
When data are sent, host first will in the buffer area that the data sent be needed to be written in memory, then will include that data will be long
The control word that degree, log-on data send mark is written in the register；The transmission DMA control module passes through PCI-E interface
Send what read request TLP data packet was received to the TLP data packet analysis module, the TLP data packet analysis module judgement
Whether TLP data packet is read request TLP data packet, if it is, the register Read-write Catrol module is according to read request TLP number
It is retransmited according to the data in the address readout register in packet, and to plus the packet header for running through TLP data by PCI-E interface
To the TLP data packet analysis module, the TLP data packet analysis module judges whether received TLP data packet is to run through
At TLP data packet, data transmission is carried out if it is, this is run through TLP data packet and is sent to the transmitting line；
When data receiver, the data received are sent to the reception DMA control module by the data reception lines, described to connect
It receives DMA control module and write request TLP data packet is sent to the TLP data packet analysis module, the TLP by PCI-E interface
Whether the received TLP data packet of data packet analysis module judgement is write request TLP data packet, if it is, the deposit
Device Read-write Catrol module reads address and data in write request TLP data packet, and writes data into what address part was specified
In register, host memory is then written by PCI-E interface.
2. PCI-E bus interface transmission card according to claim 1, which is characterized in that further include that the reception of TLP data packet is slow
Area is rushed, it is logical with the PCI-E interface IP kernel and the TLP data packet analysis module respectively that the TLP data packet receives buffer area
Letter connection.
3. PCI-E bus interface transmission card according to claim 1, which is characterized in that further include the first TLP data packet hair
Buffer area, the 2nd TLP data packet is sent to send buffer area and the 3rd TLP data packet transmission buffer area, the first TLP data packet hair
Buffer area is sent to communicate to connect respectively with the register Read-write Catrol module and PCI-E interface IP kernel, the 2nd TLP data packet
It sends buffer area to communicate to connect with the transmission DMA control module and PCI-E interface IP kernel respectively, the 3rd TLP data packet
Buffer area is sent to communicate to connect with the reception DMA control module and PCI-E interface IP kernel respectively.
4. PCI-E bus interface transmission card according to claim 3, which is characterized in that further include sending buffer area selection
Module, the first TLP data packet sends buffer area, the 2nd TLP data packet sends buffer area and the 3rd TLP data packet sends and delays
The output end for rushing area is connected to transmission buffer area selecting module input terminal, the transmission buffer area selecting module with it is described
The communication connection of PCI-E interface IP kernel；
The transmission buffer area selecting module is controlled according to priority criteria will the first TLP data packet transmission buffer area, the
The data packet that two TLP data packets are sent in buffer area and the 3rd TLP data packet transmission buffer area is transferred to PCIE interface.
5. PCI-E bus interface transmission card according to claim 1, which is characterized in that the transmitting line includes: described
Transmitting line includes running through TLP data packet handing module, transmitting line buffer area, encoder and sending LVDS interface；
TLP data packet handing module input terminal is run through described in the connection of the first output end of the TLP data packet analysis module, it is described
Run through TLP data packet handing module output end connection transmitting line buffer area input terminal, the transmitting line buffer area
Output end connects the encoder input terminal, and the encoder is connect by the transmission LVDS interface with the transmitting line；
The TLP data packet handing module that runs through buffers the data run through in TLP data packet the write-in transmitting line
Then Qu Zhong is encoded and is inserted by the encoder control character, then gone here and there by the transmission LVDS interface to data
And it is sent in transmitting line after converting.
6. PCI-E bus interface transmission card according to claim 1, which is characterized in that the receiving circuit includes receiving
LVDS interface, decoder and receiving circuit buffer area；
The reception LVDS interface is connect with receiving circuit and the decoder respectively, is connect described in the decoder output connection
Take-up road buffer area input terminal, receiving circuit buffer area output end are connected to the reception DMA control module input terminal；
The reception LVDS interface receives data from receiving circuit, and the inspection of serial to parallel conversion and control character is carried out to it
It surveys, control character sends the data to the decoder and carries out data decoding after detecting, then decoded data are sent to
In the receiving circuit buffer area and to the reception DMA control module transmitting line data accepted flag, the reception DMA is controlled
For molding block after detecting the received mark of track data effectively, starting receives DMA process, transfers data to host memory
In buffer area in.
7. a kind of data transmission method based on PCI-E bus interface transmission card described in claim 1, which is characterized in that number
According to the first transmission card and the second transmission card is used in transmission process, first transmission card and the second transmission card are claim
PCI-E bus interface transmission card described in 1, first transmission card and the communication connection of the second transmission card, comprising the following steps:
When S1, data are sent, the data of transmission are first written in the buffer area in memory by sending device, then will include data
The control word that length, log-on data send mark is write in the transmission control register of the first transmission card；
S2, the first transmission card detect log-on data send mark effectively after, judge the first transmission card transmitting line whether
Whether the transmitting line of connection and the first transmission card caching can be used, and the log-on data transmission process if available otherwise waits for sending out
Line sending road and caching are available；
After S3, data transmission procedure starting, start DMA transfer, the transmission DMA control module of the first transmission card will include reading
Data address and the read request TLP data packet of data length are sent to the TLP data packet point of the first transmission card by PCI-E interface
Analyse module；
S4, the TLP data packet that the TLP data packet analysis module judgement of the first transmission card is received are specially read request TLP data
Packet still runs through TLP data packet, if it is read request TLP data packet, thens follow the steps S5, if it is running through TLP data
Packet, thens follow the steps S6；
S5, the first transmission card register Read-write Catrol module according in the address readout register in read request TLP data packet
Data, and the TLP data packet analysis of the first transmission card is sent to plus the packet header for running through TLP data by PCI-E interface
Then module executes step S4；
The TLP data packet analysis module transmission line that will run through TLP data packet and be sent to the first transmission card of S6, the first transmission card
Road carries out data transmission；
S7, second transmission card receive data, and the receiving circuit of second transmission card receives data, and will receive
To data be sent to the reception DMA control module of the second transmission card；
S8, the second transmission card reception DMA control module by PCI-E interface send write request TLP data packet to second transmission
The TLP data packet analysis module of card；
Whether S9, the TLP data packet that the TLP data packet analysis module judgement of the second transmission card is received are write request TLP number
According to packet, if so, thening follow the steps S10；
S10, the second transmission card register Read-write Catrol module read write request TLP data packet in address and data, and will
Data are written in the specified register of address part, and receiving device memory then is written by PCI-E interface.
8. the data transmission method according to claim 7 based on PCI-E bus interface transmission card, which is characterized in that institute
It states in step S3, before DMA transfer, sends DMA control module and calculate time for needing to carry out DMA transfer according to data length
Number；
In the step S7, before receiving DMA control module reception data, DMA control module is received according to data length meter
Calculate the number of DMA transfer.
9. the data transmission method according to claim 7 based on PCI-E bus interface transmission card, which is characterized in that hair
When sending data, transmitting line need to be encoded to data and be inserted into the control character of alignment, beginning or end；Data receiver
When, receiving circuit need to carry out the detection and decoding of control character to data.
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| CN108199864A (en) * | 2017-12-06 | 2018-06-22 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of bandwidth allocation methods based on the transmission of PCIe transaction layer data |
| CN112433962A (en) * | 2019-08-24 | 2021-03-02 | 北京希姆计算科技有限公司 | Data transmission circuit and method, core, chip, electronic device, and storage medium |
| CN113297022B (en) * | 2021-06-09 | 2023-03-24 | 海光信息技术股份有限公司 | Method and device for testing expansion bus of high-speed serial computer |
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