CN105448845B - Three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof - Google Patents
Three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 106
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 105
- 239000010703 silicon Substances 0.000 claims abstract description 105
- 239000013078 crystal Substances 0.000 claims abstract description 83
- 230000000873 masking effect Effects 0.000 claims abstract description 70
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 238000005516 engineering process Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 313
- 239000000463 material Substances 0.000 claims description 57
- 238000004519 manufacturing process Methods 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- 229910052681 coesite Inorganic materials 0.000 claims description 18
- 229910052906 cristobalite Inorganic materials 0.000 claims description 18
- 229910052682 stishovite Inorganic materials 0.000 claims description 18
- 229910052905 tridymite Inorganic materials 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 15
- 238000003701 mechanical milling Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 19
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 12
- 230000010354 integration Effects 0.000 abstract description 7
- 238000012995 silicone-based technology Methods 0.000 abstract description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 4
- 229910052732 germanium Inorganic materials 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 8
- 230000008901 benefit Effects 0.000 description 5
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Abstract
The present invention provides three layers of crystallographic orientation semiconductor-on-insulator structure of one kind and preparation method thereof, it include: substrate, the first masking layer, the first groove, GaN layer, the second groove, the first sidewall structure, monocrystalline silicon layer, third groove, the second sidewall structure and GeSi layers, wherein, the upper surface of GeSi layers described, GaN layer and monocrystalline silicon layer maintains an equal level in the same plane.GaN layer surface prepares high frequency (super) high voltage gan device for subsequent, (110) crystal face germanium silicon surface prepares high frequency (super) low pressure SiGe device for subsequent, in favor of sufficiently increasing hole carrier mobility, (100) crystal face monocrystalline surface is for the conventional silicon-based devices of subsequent preparation, to make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies are by high frequency, (super) high pressure, (super) low pressure, high reliability and conventional silicon-based nano grade device integration are designed into a planar-type semiconductor integrated circuit and provide a kind of advanced structure, technology.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, more particularly to a kind of three layers of crystallographic orientation semiconductor-on-insulator
Structure and preparation method thereof.
Background technique
At present, it is generally the case that crystallographic orientation SOI refers to the different soi structure of the crystal face of substrate silicon and top layer silicon,
Purpose is prepared in NMOSFET and PMOSFET respectively in the silicon substrate of (100) crystal face and (110) crystal face, thus keeping
In NMOSFET under the mobility of electronic carrier, sufficiently increase the mobility of holoe carrier in PMOSFET, so that NMOSFET
It is sufficiently balanced with PMOSFET operating current, increases cmos circuit function, simplify cmos circuit design.
Based on above-mentioned conventional crystallographic orientation soi structure, Huang dawn big shield etc. is published in " semiconductor technology " 2012Vol.37No.8
Paper " localization mixed crystal orientation strain silicon CMOS structure and preparation method thereof " on phase proposes a kind of localization crystallographic orientation
Strain silicon CMOS structure and preparation method thereof leads to the works such as hard mask deposit, photoetching, dry etching, extension, CMP, wet etching
Sequence so that planarization is realized in (110) silicon face and (100) silicon face, then prepare respectively in the same plane NMOSFET and
PMOSFET, as shown in Figure 1.
Meanwhile the research and application of germanium silicon material and germanium material just become the hot spot of semiconducter research at present, are primarily due to
Germanium has the advantages that 1) hole mobility is maximum, is four times of silicon；Electron mobility is twice of silicon.2) forbidden bandwidth ratio
It is smaller, be conducive to develop voltage devices.3) alms giver/acceptor activationary temperature is far below silicon, is conducive to save heat budget.4) small
Bohr exciton radii, help to improve its field emission characteristic.5) small forbidden bandwidth helps to combine dielectric material, drop
Low-leakage current.But the shortcomings that germanium, it is also obvious that germanium belongs to more active material, the interface of it and dielectric material is easy to happen oxygen
Change reduction reaction, generate GeO, generates more defect, and then influence the performance of material.But with the development of semiconductor technology, germanium
The shortcomings that silicon materials and germanium material, is just gradually overcome, and advantage can be utilized very well, currently, industry is in exploitation with germanium silicon
Or it makes great progress in terms of ultralow pressure high-frequency element of the germanium material as substrate material.
In addition, the research of GaN material and application are forward position and the hot spot of current global semiconductor research, it is to develop microelectronics
The novel semiconductor material of device, opto-electronic device, and together with the semiconductor materials such as SIC, diamond, it is known as being after first
For the third generation semiconductor material after Ge, Si semiconductor material, second generation GaAs, InP compound semiconductor materials.It has
Properties such as wide direct band gap, strong atom key, high thermal conductivity, chemical stability good (hardly by any acid corrosion) and strong
Radiation hardness, have wide prospect in photoelectron, high temperature high power device and high-frequency microwave device application aspect.It is logical
Often, since lattice structure is close, the stable GaN of lattice structure is generally generated by the silicon crystal lattice surface extension in (111) crystal face
Material.
Due to the difference of substrate material, how to make full use of SOI technology, germanium silicon technology, GaN technology by high frequency, (super)
High pressure, (super) low pressure, high reliability nanoscale devices Integration Design into a planar-type semiconductor integrated circuit, industry is still
There is no correlative study.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of three layers of crystallographic orientation insulators
The production method of upper semiconductor structure, to be SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies by high frequency, (super) height
Pressure, (super) low pressure, high reliability and conventional silicon-based nano grade device integration are designed into a planar-type semiconductor integrated circuit
In a kind of advanced structure and technology are provided.
In order to achieve the above objects and other related objects, the present invention provides a kind of three layers of crystallographic orientation semiconductor-on-insulator
The production method of structure, comprising steps of a) provide a substrate, the substrate include the first crystal orientation stacked gradually silicon bottom,
The silicon top layer of first insulating layer, the silicon middle layer of the second crystal orientation, second insulating layer and third crystal orientation；B) on the silicon top layer
It is rectangular at the first masking layer, the first groove until the silicon top layer is formed in the position for being intended to prepare the first device area, in institute
It states in the first groove and forms GaN layer；C) the second groove until silicon bottom is formed in the position for being intended to prepare the second device area, in
The first sidewall structure is formed in second groove, then forms the monocrystalline silicon with the first crystal orientation in second groove
Layer；D) the third groove until silicon middle layer, the shape in the third groove are formed in the position of third device area to be prepared
At the second sidewall structure, GeSi material is then formed in the third groove, and keep Ge dense downwards using oxidation concentration technology
It contracts and diffuses into silicon middle layer, so that being respectively formed GeSi layers in silicon interlayer region and third groove.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, institute
State in production method, step a), b), c), d) execute sequence are as follows: a), b), c), d) or a), b), d), c) or a), c), b),
D) or a), c), d), b) or a), d), b), c) or a), d), c), b).
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, institute
The growth thickness for stating GaN layer, monocrystalline silicon layer and GeSi layers is the upper table at least so that the GaN layer, monocrystalline silicon layer and GeSi layers
Face maintains an equal level in the same plane.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, step
It is rapid b) in, so that the upper surface for the GaN layer to be formed is higher by first masking layer, included later using chemical mechanical milling tech
Extra GaN material is removed, the upper surface of GaN layer and first masking layer upper surface is made to maintain an equal level；In step c), pass through to be formed
The second masking layer with etching window forms second groove, and is higher by the upper surface for the monocrystalline silicon layer to be formed
Second masking layer removes extra single crystal silicon material using chemical mechanical milling tech later, makes the upper table of monocrystalline silicon layer
Face and second masking layer upper surface maintain an equal level；In step d), by being formed there is the third masking layer of etching window to be formed
Second groove, and the GeSi layers that be formed of upper surface is made to be higher by the third masking layer, chemical machinery is used later
Grinding technics removes extra GeSi material, and the upper surface and third masking layer upper surface for making GeSi layers maintain an equal level.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, institute
The material for stating the first masking layer, the second masking layer and third masking layer includes Si3N4And SiO2One of or combinations thereof, it is described
The material of first sidewall structure and the second sidewall structure includes Si3N4And SiO2One of or combinations thereof.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, also
Comprising steps of using being generated in chemical mechanical milling tech removal technical process positioned at GaN layer and/or monocrystalline silicon layer, and/
Or the extra masking layer of GeSi layers of top, and the GaN layer, monocrystalline silicon layer and GeSi layer surface is made to maintain an equal level；Or first using wet
What is generated in method erosion removal technical process is located at the extra masking of GaN layer and/or monocrystalline silicon layer and/or GeSi layers of top
Layer, then so that the GaN layer, monocrystalline silicon layer and GeSi layer surface is maintained an equal level using chemical mechanical milling tech.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, step
It is rapid d) in uses with oxidation concentration technology for globalization wafer surface dry-oxygen oxidation technique.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, institute
Stating third crystal orientation is (111) crystal orientation.
A kind of preferred embodiment of production method as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, institute
Stating the first crystal orientation is (100), and the second crystal orientation is (110)；Or first crystal orientation is (110), the second crystal orientation is (100).
The present invention also provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structures, comprising: substrate, the substrate include
Silicon bottom, the first insulating layer, the silicon middle layer of the second crystal orientation, second insulating layer and the third of the first crystal orientation stacked gradually are brilliant
To silicon top layer；First masking layer is formed in the silicon topsheet surface；First groove is formed in first masking layer, and
Exposing has silicon topsheet surface；GaN layer is formed in first groove；Second groove extends to institute from the structure upper surface
It states in substrate, and its bottom contacts silicon bottom surface；；First sidewall structure is formed in second recess sidewall；First crystal orientation
Monocrystalline silicon layer, be formed in second groove；Third groove extends in the substrate from the structure upper surface, and
Its bottom contacts silicon middle layer；Second sidewall structure is formed in the third recess sidewall；GeSi layers, it is formed in the third
The silicon interlayer region to connect in groove and with the third groove.
As a kind of preferred embodiment of three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, the GaN layer, list
Crystal silicon layer and GeSi layers of upper surface maintain an equal level in the same plane.
As a kind of preferred embodiment of three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, the third crystal orientation
For (111) crystal orientation.
As a kind of preferred embodiment of three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, first crystal orientation
For (100), the second crystal orientation is (110)；Or first crystal orientation is (110), the second crystal orientation is (100).
As a kind of preferred embodiment of three layers of crystallographic orientation semiconductor-on-insulator structure of the invention, first masking
The material of layer includes Si3N4And SiO2One of or combinations thereof, the material packet of first sidewall structure and the second sidewall structure
Include Si3N4And SiO2One of or combinations thereof.
As described above, three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof of the invention, has following
The utility model has the advantages that the present invention provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof, GaN layer surface
High frequency (super) high voltage gan device is prepared for subsequent, (110) crystal face germanium silicon surface prepares high frequency (super) low pressure germanium for subsequent
Silicon device, in favor of sufficiently increasing hole carrier mobility, (100) crystal face monocrystalline surface is for the conventional silicon of subsequent preparation
Base device, to make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies by high frequency, (super) high pressure, (super)
Low pressure, high reliability and conventional silicon-based nano grade device integration are designed into a planar-type semiconductor integrated circuit and provide one
The advanced structure of kind, technology.Structure of the invention and method are simple, significant effect, have in field of semiconductor manufacture extensive
Application prospect.
Detailed description of the invention
Fig. 1 is shown as a kind of schematic diagram of mixed crystal orientation strain silicon CMOS structure that localizes in the prior art.
Fig. 2 is shown as the production method steps flow chart signal of three layers of crystallographic orientation semiconductor-on-insulator structure of the invention
Figure.
Fig. 3~Figure 13 is shown as each step of production method of three layers of crystallographic orientation semiconductor-on-insulator structure of the invention
The structural schematic diagram presented.Wherein, Figure 13 is shown as three layers of crystallographic orientation semiconductor-on-insulator structure of the invention most
Whole structural schematic diagram.
Component label instructions
101 silicon bottoms
102 first insulating layers
103 silicon middle layers
104 second insulating layers
105 silicon top layers
106 first masking layers
107 GaN layers
108 second masking layers
109 first sidewall structures
110 monocrystalline silicon layers
111 third masking layers
112 second sidewall structures
113 GeSi layers
114 SiO2Layer
S11~S14 step 1)~step 4)
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 2~Figure 13.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in diagram then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment 1
As shown in Fig. 2~Figure 13, the present embodiment provides a kind of production of three layers of crystallographic orientation semiconductor-on-insulator structure
Method, comprising steps of
As shown in Figures 2 and 3, step 1) S11 is carried out first, a substrate is provided, and the substrate includes the stacked gradually
The silicon bottom 101 of one crystal orientation, the first insulating layer 102, the silicon middle layer 103 of the second crystal orientation, second insulating layer 104 and third are brilliant
To silicon top layer 105.
In the present embodiment, first crystal orientation is (100), and the second crystal orientation is (110), and third crystal orientation is (111), specifically
Ground, the substrate include the silicon bottom 101 of (100) crystal orientation stacked gradually, the first silicon dioxide layer, (110) crystal orientation silicon in
The silicon top layer 105 of interbed 103, the second silicon dioxide layer and (111) crystal orientation.
As shown in Fig. 2 and Fig. 4~Fig. 5, step 2) S12 is then carried out, forms the first masking above the silicon top layer 101
Layer 106, and the first groove until the silicon top layer 105 is formed in the position for being intended to prepare the first device area, in described first
GaN layer 107 is formed in groove.
As an example, first masking layer 106 is hard exposure mask, material can be SiO2Or Si3N4.In this implementation
In example, the material of first masking layer 106 is Si3N4。
Specifically, comprising the following steps:
Step 2-1), Si is deposited in 105 surface of silicon top layer3N4Layer；
Step 2-2), in the Si3N4Layer surface spin coating photoresist, and using photoetching process in being intended to prepare the first device region
Window is opened in the position in domain, forms litho pattern；
Step 2-3), it is based on the litho pattern, the Si is etched using dry etch process3N4Layer is to exposing the silicon
Top layer 105 forms the first groove；
Step 2-4), using epitaxy technique, with (111) silicon top layer 105 in the first groove for seed layer, grow GaN layer
107, growing height requires more than the upper surface of first masking layer；Due to lattice structure close to the silicon wafer in (111) crystal face
The epitaxial growth of lattice surface can obtain that lattice structure is stable and the higher GaN material of quality；
Step 2-5), extra GaN is removed using CMP (chemical mechanical grinding) technique, shelters the upper surface GaN and first
The upper surface of layer maintains an equal level.
As shown in Fig. 2 and Fig. 6~Fig. 9, step 3) S13 is then carried out, makes the second masking layer 108, and in being intended to prepare the
The position of two device areas forms the second groove until silicon bottom 101, forms the first sidewall structure in second groove
109, the monocrystalline silicon layer 110 with the first crystal orientation is then formed in second groove.
As an example, it is hard exposure mask that second masking layer 108, which is selected, material can be SiO2Or Si3N4.At this
In embodiment, the material of second masking layer 108108 is Si3N4。
Specifically, comprising the following steps:
Step 3-1), Si is deposited in the GaN layer 107 and 106 surface of the first masking layer3N4Layer；
Step 3-2), in the Si3N4Layer surface spin coating photoresist, and using photoetching process in being intended to prepare the second device region
Window is opened in the position in domain, forms litho pattern；
Step 3-3), it is based on the litho pattern, the Si is etched using dry etch process3N4Layer and the substrate are extremely
Expose the silicon bottom 101, forms the second groove；
Step 3-4), the first sidewall structure 109 is prepared in second groove by the techniques such as depositing, etching, it is described
First sidewall structure, 109 material can be Si3N4Or SiO2Or both combination or other spacer materials, and make the second groove
Interior (100) silicon bottom 101 exposes；
Step 3-5), using epitaxy technique, with (100) silicon bottom 101 in the second groove for seed layer, grow (100)
Monocrystalline silicon layer 110, growth thickness require more than the second masking layer upper surface；
Step 3-6), extra (100) monocrystalline silicon is then removed using CMP (chemical mechanical grinding) technique, keeps (100) single
The upper surface of crystal silicon and the upper surface of the second masking layer maintain an equal level,
Step 3-7) removal extra (100) monocrystalline silicon and the second masking layer 108, make the upper surface of (100) monocrystalline silicon
Maintain an equal level with the upper surface of the GaN layer 107.
As shown in Fig. 2 and Figure 10~Figure 13, step 4) S14 is finally carried out, makes third masking layer 111, and in being intended to prepare
The position of third device area forms the third groove until silicon middle layer 103, forms the second side wall in the third groove
Structure 112, then in the third groove and 111 surface of third masking layer formed GeSi material, and using oxidation concentration work
Skill is concentrated Ge downwards and diffuses into silicon middle layer 103, so that being respectively formed GeSi layers in silicon interlayer region and third groove
113。
As an example, it is hard exposure mask that the third masking layer 111, which is selected, material can be SiO2Or Si3N4.At this
In embodiment, the material of the third masking layer 111 is Si3N4.The third device substrate material is the monocrystalline of (110) crystal orientation
Silicon.
Specifically, comprising the following steps:
Step 4-1), Si is deposited in the GaN layer 107, the first masking layer 106 and (100) monocrystalline silicon surface3N4Layer；
Step 4-2), in the Si3N4Layer surface spin coating photoresist, and using photoetching process in third device region to be prepared
Window is opened in the position in domain, forms litho pattern；
Step 4-3), it is based on the litho pattern, the Si is etched using dry etch process3N4Layer and the substrate are extremely
Expose the silicon middle layer 103, forms third groove；
Step 4-4), the second sidewall structure 112 is prepared in the third groove by the techniques such as depositing, etching, it is described
Second sidewall structure, 112 material can be Si3N4Or SiO2Or both combination or other spacer materials, and make third groove
Interior (110) silicon middle layer 103 is exposed；
Step 4-5), using epitaxy technique, with (110) silicon bottom 101 in third groove for seed layer, grow GeSi material
Material, growth thickness requires more than third masking layer upper surface, also, has segment thickness to be covered in table on the third masking layer
Face；
Step 4-6), globalization wafer surface dry-oxygen oxidation is carried out, at this moment, the top of GeSi material is what oxidation was formed
SiO2Layer, GeSi material, which gradually aoxidizes concentration, to be concentrated Ge downwards and diffuses into silicon middle layer 103, so that silicon interlayer region
And GeSi layer 113 is respectively formed in third groove；
Step 4-7), using wet etching or the removal globalization of dry etching and CMP (chemical mechanical grinding) technique
The SiO that surface oxidation generates2Layer and hard exposure mask, so that 113 upper surface of GeSi layer and the upper surface of third masking layer maintain an equal level；
Step 4-8), extra GeSi material and third masking layer 111 are removed, upper surface and the institute of GeSi layer 113 are made
The upper surface of the upper surface and (100) monocrystalline silicon of stating GaN layer 107 maintains an equal level in the same plane.
Certainly, above-mentioned steps 3-7) and step 4-8) can be first without in this way, being walked after the completion of all steps
It is rapid 5) to be located at GaN layer 107 and/or monocrystalline silicon layer 110 using what is generated in chemical mechanical milling tech removal technical process,
And/or the extra masking layer of 113 top of GeSi layer, and make the upper surface of the GeSi layer 113 and the upper table of the GaN layer 107
Face and the upper surface of (100) monocrystalline silicon maintain an equal level in the same plane；It can also be first using in wet etching removal technical process
What is generated is located at the extra masking layer of GaN layer 107 and/or monocrystalline silicon layer 110 and/or 113 top of GeSi layer, then using chemistry
Mechanical milling tech make the upper surface of the GeSi layer 113 and the GaN layer 107 upper surface and (100) monocrystalline silicon it is upper
Surface maintains an equal level in the same plane.To complete the substrate planarization technology method of three kinds of different materials substrate devices.
Finally, GaN base high frequency (super) high voltage gan device can be made in the GaN layer 107, in (110) crystal face
113 surface of GeSi layer prepares high frequency (super) low pressure SiGe device, in favor of sufficiently increasing hole carrier mobility, described
(100) conventional silicon-based devices are made on the monocrystalline silicon of crystal orientation, to make full use of SOI technology, germanium silicon technology, GaN technology, routine
High frequency, (super) high pressure, (super) low pressure, high reliability and conventional silicon-based nano grade device integration are designed into one by silicon-based technologies
A kind of advanced structure, technology are provided in planar-type semiconductor integrated circuit.
As shown in figure 13, the present embodiment also provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure, comprising: base
Bottom, the substrate include the silicon bottom 101 of the first crystal orientation stacked gradually, the first insulating layer 102, the second crystal orientation silicon middle layer
103, the silicon top layer 105 of second insulating layer 104 and third crystal orientation；First masking layer 106, the first groove, GaN layer 107, second
Groove, the first sidewall structure 109, the monocrystalline silicon layer 110 of the first crystal orientation, third groove, the second sidewall structure 112, GeSi layers
113, the silicon interlayer region for being formed in the third groove and connecting with the third groove, wherein GeSi layers described
The upper surface of the monocrystalline silicon of 113 upper surface, the upper surface of GaN layer 107 and the first crystal orientation maintains an equal level in the same plane.
The substrate include the silicon bottom 101 of the first crystal orientation stacked gradually, the first insulating layer 102, the second crystal orientation silicon
The silicon top layer 105 of middle layer 103, second insulating layer 104 and third crystal orientation.In the present embodiment, first crystal orientation is
(100), the second crystal orientation is (110), and third crystal orientation is (111), and specifically, the substrate includes (100) crystal orientation stacked gradually
Silicon bottom 101, the first silicon dioxide layer, the silicon middle layer 103 of (110) crystal orientation, the second silicon dioxide layer and (111) it is brilliant
To silicon top layer 105.
First masking layer 106 is formed in 105 surface of silicon top layer, and first groove is formed in described first and covers
It covers in layer 106, and exposing has 105 surface of silicon top layer；The GaN layer 107 is formed in first groove.As an example, institute
The material for stating the first masking layer 106 includes Si3N4And SiO2One of or combinations thereof, in the present embodiment, first masking
The material selection of layer 106 is Si3N4。
Second groove extends in the substrate from the structure upper surface, and its bottom contacts silicon bottom, 101 tables
Face；First sidewall structure 109 is formed in second recess sidewall；The monocrystalline silicon layer 110 of first crystal orientation is formed in
In second groove；As an example, the material of first sidewall structure 109 includes Si3N4And SiO2One of or its group
It closes, in the present embodiment, the material of first sidewall structure 109 is first with for Si3N4, the monocrystalline silicon layer 110 is that (100) are brilliant
To monocrystalline silicon.
The third groove extends in the substrate from the structure upper surface, and its bottom contacts silicon middle layer 103；
Second sidewall structure 112 is formed in the third recess sidewall；The GeSi layer 113 be formed in the third groove with
And the silicon interlayer region to connect with the third groove, i.e., be formed with GeSi material in the described third groove, and with it is described
The silicon middle layer 103 that third groove connects is converted to GeSi material, and the two is formed together GeSi layer 113.As an example, described
The material of second sidewall structure 112 includes Si3N4And SiO2One of or combinations thereof, in the present embodiment, second side wall
The material of structure 112 is first with for Si3N4。
In addition, can be used for making GaN base high frequency (super) high voltage gan device in the GaN layer 107, (110) crystal face
113 surface of GeSi layer can be used for making high frequency (super) low pressure SiGe device, in favor of sufficiently increasing hole carrier mobility, institute
The monocrystalline silicon for stating (100) crystal orientation can be used for making conventional silicon-based devices, to make full use of SOI technology, germanium silicon technology, GaN skill
Art, conventional silicon-based technologies set high frequency, (super) high pressure, (super) low pressure, high reliability and conventional silicon-based nano grade device integration
It counts into a planar-type semiconductor integrated circuit and a kind of advanced structure, technology is provided.
Embodiment 2
The present embodiment provides a kind of production methods of three layers of crystallographic orientation semiconductor-on-insulator structure, and basic step is such as
Embodiment 1, wherein the execution sequence of each step in embodiment 1 is first progress step 1), rear to carry out step 2), then into
Row step 4) finally carries out step 3) again, i.e. step 3) is exchanged with the execution of step 4) sequence.
Embodiment 3
The present embodiment provides a kind of production methods of three layers of crystallographic orientation semiconductor-on-insulator structure, and basic step is such as
Embodiment 1, wherein the execution sequence of each step in embodiment 1 is first progress step 1), rear to carry out step 3), then into
Row step 2) finally carries out step 4) again.It is worth noting that the production method of this sequence is needed through control described first
The thickness of masking layer 106, the second masking layer 108 and third masking layer 111 come guarantee the GeSi layer 113, GaN layer 107,
And the growth thickness of monocrystalline silicon layer 110, so that the upper table of GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110
Face can maintain an equal level in the same plane.
In addition, the execution sequence of each step in embodiment 1 may be first to be walked based on described in the present embodiment 3
It is rapid to carry out step 3) 1), afterwards, then carry out step 4), finally carry out step 2)；
Or step 1) is first carried out, rear progress step 4), step 2) is then carried out, finally carries out step 3)；
Or step 1) is first carried out, rear progress step 4), step 3) is then carried out, finally carries out step 2).
The example of above several production methods, it is only necessary to by control first masking layer 106, the second masking layer 108,
And the thickness of third masking layer 111 is thick come the growth for guaranteeing the GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110
Degree, just allows the upper surface of the GeSi layer 113, GaN layer 107 and monocrystalline silicon layer 110 to maintain an equal level in the same plane.
As described above, three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof of the invention, has following
The utility model has the advantages that the present invention provides a kind of three layers of crystallographic orientation semiconductor-on-insulator structure and preparation method thereof, GaN layer 107
Surface prepares high frequency (super) high voltage gan device for subsequent, and (110) crystal face germanium silicon surface is used for that subsequent to prepare high frequency (super) low
SiGe device is pressed, in favor of sufficiently increasing hole carrier mobility, 110 surface of (100) crystal face monocrystalline silicon layer is used for subsequent system
Standby routine silicon-based devices, to make full use of SOI technology, germanium silicon technology, GaN technology, conventional silicon-based technologies by high frequency, (super) height
Pressure, (super) low pressure, high reliability and conventional silicon-based nano grade device integration are designed into a planar-type semiconductor integrated circuit
In a kind of advanced structure, technology are provided.Structure of the invention and method are simple, significant effect, in field of semiconductor manufacture
It is with a wide range of applications.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (14)
1. a kind of production method of three layers of crystallographic orientation semiconductor-on-insulator structure, which is characterized in that comprising steps of
A) substrate is provided, the substrate includes the silicon bottom, the first insulating layer, the second crystal orientation of the first crystal orientation stacked gradually
The silicon top layer of silicon middle layer, second insulating layer and third crystal orientation；
B) the first masking layer is formed above the silicon top layer to be formed in the position for being intended to prepare the first device area until the silicon
First groove of top layer forms GaN layer in first groove；
C) the second groove until silicon bottom is formed in the position for being intended to prepare the second device area, is formed in second groove
Then first sidewall structure forms the monocrystalline silicon layer with the first crystal orientation in second groove；
D) the third groove until silicon middle layer, the shape in the third groove are formed in the position of third device area to be prepared
At the second sidewall structure, GeSi material is then formed in the third groove, and keep Ge dense downwards using oxidation concentration technology
It contracts and diffuses into silicon middle layer, so that being respectively formed GeSi layers in silicon interlayer region and third groove.
2. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
In the production method, step a), b), c), d) execute sequence are as follows: a), b), c), d) or a), b), d), c) or a), c),
B), d) or a), c), d), b) or a), d), b), c) or a), d), c), b).
3. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
The GaN layer, monocrystalline silicon layer and GeSi layers of growth thickness is at least so that the GaN layer, monocrystalline silicon layer and GeSi layers upper
Surface maintains an equal level in the same plane.
4. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
In step b), so that the upper surface for the GaN layer to be formed is higher by first masking layer, include ground using chemical machinery later
Grinding process removes extra GaN material, and the upper surface of GaN layer and first masking layer upper surface is made to maintain an equal level；
In step c), by being formed there is the second masking layer of etching window to form second groove, and make the institute to be formed
The upper surface for stating monocrystalline silicon layer is higher by second masking layer, removes extra monocrystalline silicon using chemical mechanical milling tech later
Material makes the upper surface of monocrystalline silicon layer and second masking layer upper surface maintain an equal level；
In step d), by being formed there is the third masking layer of etching window to form second groove, and make the institute to be formed
It states GeSi layers of upper surface and is higher by the third masking layer, extra GeSi material is removed using chemical mechanical milling tech later
Material, the upper surface and third masking layer upper surface for making GeSi layers maintain an equal level.
5. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 4, it is characterised in that:
The material of first masking layer, the second masking layer and third masking layer includes Si3N4And SiO2One of or combinations thereof, institute
The material for stating the first sidewall structure and the second sidewall structure includes Si3N4And SiO2One of or combinations thereof.
6. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
It further comprises the steps of: and is located at GaN layer and/or monocrystalline silicon layer using what is generated in chemical mechanical milling tech removal technical process,
And/or the extra masking layer of GeSi layers of top, and the step for keeping the GaN layer, monocrystalline silicon layer and GeSi layer surface fair；Or
It is first more above GaN layer and/or monocrystalline silicon layer and/or GeSi layers using being generated in wet etching removal technical process
Remaining masking layer, then so that the GaN layer, monocrystalline silicon layer and GeSi layer surface is maintained an equal level using chemical mechanical milling tech.
7. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
Uses in step d) with oxidation concentration technology for globalization wafer surface dry-oxygen oxidation technique.
8. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
The third crystal orientation is (111) crystal orientation.
9. the production method of three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 1, it is characterised in that:
First crystal orientation is (100), and the second crystal orientation is (110)；Or first crystal orientation is (110), the second crystal orientation is (100).
10. a kind of three layers of crystallographic orientation semiconductor-on-insulator structure characterized by comprising
Substrate, the substrate include the silicon bottom of the first crystal orientation stacked gradually, the first insulating layer, the second crystal orientation silicon among
The silicon top layer of layer, second insulating layer and third crystal orientation；
First masking layer is formed in the silicon topsheet surface；
First groove is formed in first masking layer, and exposing has silicon topsheet surface；
GaN layer is formed in first groove；
Second groove extends in the substrate from the structure upper surface, and its bottom contacts silicon bottom surface；
First sidewall structure is formed in second recess sidewall；
The monocrystalline silicon layer of first crystal orientation is formed in second groove；
Third groove extends in the substrate from the structure upper surface, and its bottom contacts silicon middle layer；
Second sidewall structure is formed in the third recess sidewall；
It GeSi layers, is formed in the third groove, and Ge is concentrated downwards by oxidation concentration technology and diffuses into silicon
Interbed, so that being respectively formed GeSi layers in silicon interlayer region and third groove.
11. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, it is characterised in that: the GaN
Layer, monocrystalline silicon layer and GeSi layers of upper surface maintain an equal level in the same plane.
12. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, it is characterised in that: the third
Crystal orientation is (111) crystal orientation.
13. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, it is characterised in that: described first
Crystal orientation is (100), and the second crystal orientation is (110)；Or first crystal orientation is (110), the second crystal orientation is (100).
14. three layers of crystallographic orientation semiconductor-on-insulator structure according to claim 10, it is characterised in that: described first
The material of masking layer includes Si3N4And SiO2One of or combinations thereof, the material of first sidewall structure and the second sidewall structure
Material includes Si3N4And SiO2One of or combinations thereof.
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| CN102194830A (en) * | 2010-01-28 | 2011-09-21 | 英特赛尔美国股份有限公司 | Monolithic integration of gallium nitride and silicon devices and circuits, structure and method |
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| CN102194830A (en) * | 2010-01-28 | 2011-09-21 | 英特赛尔美国股份有限公司 | Monolithic integration of gallium nitride and silicon devices and circuits, structure and method |
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