CN105355593B - Tft基板的制作方法及tft基板 - Google Patents
Tft基板的制作方法及tft基板 Download PDFInfo
- Publication number
- CN105355593B CN105355593B CN201510894341.2A CN201510894341A CN105355593B CN 105355593 B CN105355593 B CN 105355593B CN 201510894341 A CN201510894341 A CN 201510894341A CN 105355593 B CN105355593 B CN 105355593B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon germanium
- germanium layer
- amorphous silicon
- crystallization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 118
- 238000000034 method Methods 0.000 claims abstract description 72
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 150000002500 ions Chemical class 0.000 claims abstract description 37
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 242
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 239000011229 interlayer Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- -1 phosphonium ion Chemical class 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000002425 crystallisation Methods 0.000 abstract description 52
- 230000008025 crystallization Effects 0.000 abstract description 52
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 7
- 239000007790 solid phase Substances 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 22
- 239000004973 liquid crystal related substance Substances 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 238000004151 rapid thermal annealing Methods 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000007715 excimer laser crystallization Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提供一种TFT基板的制作方法及TFT基板。本发明的TFT基板的制作方法,通过在基板上沉积缓冲层与非晶硅锗层,在所述非晶硅锗层的上部植入掺杂离子,形成掺杂非晶硅锗层,然后采用快速热退火工艺对所述掺杂非晶硅锗层和未掺杂非晶硅锗层进行晶化处理,由于该晶化过程是从掺杂非晶硅锗层开始,且掺杂非晶硅锗层的晶化温度较低,因此该晶化过程可以在较低的温度下进行,而与掺杂非晶硅锗层接触的未掺杂非晶硅锗层在该低温下可以继续结晶,从而得到掺杂多晶硅锗层和未掺杂多晶硅锗层,相较于现有的固相晶化等结晶工艺来说,本发明的结晶制程可以在更低的温度下进行,并且能够缩短结晶时间,改善结晶效果,可制得更大更均匀的晶粒。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT基板的制作方法及TFT基板。
背景技术
随着显示技术的发展,液晶显示器(Liquid Crystal Display,LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点,而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品,成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器,其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子,两片玻璃基板中间有许多垂直和水平的细小电线,通过通电与否来控制液晶分子改变方向,将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF,Color Filter)基板、薄膜晶体管(TFT,Thin FilmTransistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC,Liquid Crystal)及密封胶框(Sealant)组成,其成型工艺一般包括:前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中,前段Array制程主要是形成TFT基板,以便于控制液晶分子的运动;中段Cell制程主要是在TFT基板与CF基板之间添加液晶;后段模组组装制程主要是驱动IC压合与印刷电路板的整合,进而驱动液晶分子转动,显示图像。
如图1所示,现有的TFT基板的制作方法为:先在基板100上沉积缓冲层200、及非晶硅(a-Si)层,所述非晶硅层经由结晶制程转变为多晶硅(poly-Si)层300,然后经过光刻制程得到所需多晶硅层300的图形,最后在多晶硅层300上依次制作栅极绝缘层400、栅极500、层间绝缘层600、及源/漏极700等结构,得到如图1所示的TFT基板。
目前常用的非晶硅(a-Si)的结晶制程有化学气相沉积(CVD)、准分子激光晶化(ELA)、固相晶化(SPC)、金属诱导晶化(MIC)、金属横向诱导法(MILC)等,然而,采用CVD结晶制程制得的poly-Si晶粒尺寸特别小,且沉积速率低;采用传统的SPC结晶制程需要高温且耗时长,导致基板易变形,成本高;采用MIC、MILC结晶制程制得的poly-Si层金属残留大,导致TFT特性变差;采用ELA结晶制程制得的poly-Si缺隙态密度低,设备昂贵且难以制作大面积poly-Si薄膜。
发明内容
本发明的目的在于提供一种TFT基板的制作方法,采用快速热退火工艺对非晶硅锗层进行晶化处理制得多晶硅锗层,与现有的结晶工艺相比,该结晶制程在较低的温度下进行,且结晶时间更短,结晶效果好。
本发明的目的在于还提供一种TFT基板,采用掺杂多晶硅锗层作为有源层的源、漏极接触区,从而具有较好的电学性能。
为实现上述目的,本发明提供一种TFT基板的制作方法,包括如下步骤:
步骤1、提供一基板,在所述基板上依次沉积缓冲层、及非晶硅锗层;
步骤2、从所述非晶硅锗层的上表面对所述非晶硅锗层进行离子掺杂,从而在所述非晶硅锗层中形成位于上方的掺杂非晶硅锗层及位于下方的未掺杂非晶硅锗层;
步骤3、采用快速热退火工艺对所述掺杂非晶硅锗层与未掺杂非晶硅锗层进行晶化处理,使得所述掺杂非晶硅锗层与未掺杂非晶硅锗层分别转化为掺杂多晶硅锗层与未掺杂多晶硅锗层,所述掺杂多晶硅锗层与未掺杂多晶硅锗层共同构成有源层;
步骤4、采用一道光刻制程对所述掺杂多晶硅锗层进行图案化处理,形成间隔设置的源极接触区与漏极接触区;
步骤5、采用一道光刻制程对所述未掺杂多晶硅锗层进行图案化处理,使其左、右两侧分别与源极接触区的左侧、及漏极接触区的右侧相对应,所述未掺杂多晶硅锗层上对应所述源极接触区与漏极接触区之间的部分形成沟道区;
步骤6、在所述有源层上沉积栅极绝缘层,在所述栅极绝缘层上沉积第一金属层,采用一道光刻制程对所述第一金属层进行图案化处理,得到对应沟道区上方的栅极;
步骤7、在所述栅极、及栅极绝缘层上沉积层间绝缘层,采用一道光刻制程对所述层间绝缘层与栅极绝缘层进行图案化处理,在所述层间绝缘层与栅极绝缘层上形成分别对应于源极接触区、及漏极接触区的第一、第二过孔;
步骤8、在所述层间绝缘层上沉积第二金属层,采用一道光刻制程对所述第二金属层进行图案化处理,得到源极与漏极,所述源极、及漏极分别经由第一、第二过孔与源极接触区、及漏极接触区相接触。
所述基板为玻璃基板;所述缓冲层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层。
在所述非晶硅锗层中掺杂的离子为N型离子或P型离子,所述离子掺杂的方式为离子植入机植入掺杂或者气相沉积掺杂。
所述N型离子为磷离子或砷离子;所述P型离子为硼离子或镓离子。
所述层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述第一金属层、第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种TFT基板,包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的有源层、设于所述有源层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层、及设于所述层间绝缘层上的源极与漏极;
其中,所述有源层包括未掺杂多晶硅锗层、及位于所述未掺杂多晶硅锗层上方的掺杂多晶硅锗层,所述掺杂多晶硅锗层包括分别对应所述未掺杂多晶硅锗层两侧的源极接触区与漏极接触区,所述层间绝缘层与栅极绝缘层上设有分别对应于源极接触区、及漏极接触区的第一、第二过孔,所述源极、及漏极分别经由第一、第二过孔与源极接触区、及漏极接触区相接触。
所述未掺杂多晶硅锗层上对应所述源极接触区与漏极接触区之间的部分形成沟道区,所述栅极对应沟道区上方设置。
所述基板为玻璃基板;所述缓冲层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层。
所述掺杂多晶硅锗层为N型掺杂多晶硅锗层或P型掺杂多晶硅锗层;所述N型掺杂多晶硅锗层中掺杂的离子为磷离子或砷离子;所述P型掺杂多晶硅锗层中掺杂的离子为硼离子或镓离子。
所述层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述栅极、源极、及漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果:本发明提供的一种TFT基板的制作方法,通过在基板上沉积缓冲层与非晶硅锗层,在所述非晶硅锗层的上部植入掺杂离子,形成掺杂非晶硅锗层,然后采用快速热退火工艺对所述掺杂非晶硅锗层和未掺杂非晶硅锗层进行晶化处理,由于该晶化过程是从掺杂非晶硅锗层开始,且掺杂非晶硅锗层的晶化温度较低,因此该晶化过程可以在较低的温度下进行,而与掺杂非晶硅锗层接触的未掺杂非晶硅锗层在该低温下可以继续结晶,从而得到掺杂多晶硅锗层和未掺杂多晶硅锗层,相较于现有的固相晶化等结晶工艺来说,本发明的结晶制程可以在更低的温度下进行,并且能够缩短结晶时间,改善结晶效果,可制得更大更均匀的晶粒。本发明提供的一种TFT基板,采用掺杂多晶硅锗层作为有源层的源、漏极接触区,导电性能好,可以与源、漏极之间形成良好的欧姆接触,提高了TFT基板的电学性能。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为采用现有技术制得的TFT基板的结构示意图;
图2为本发明的TFT基板的制作方法的示意流程图;
图3为本发明的TFT基板的制作方法的步骤1的示意图;
图4为本发明的TFT基板的制作方法的步骤2的示意图;
图5为本发明的TFT基板的制作方法的步骤3的示意图;
图6为本发明的TFT基板的制作方法的步骤4的示意图;
图7为本发明的TFT基板的制作方法的步骤5的示意图;
图8为本发明的TFT基板的制作方法的步骤6的示意图;
图9为本发明的TFT基板的制作方法的步骤7的示意图;
图10为本发明的TFT基板的制作方法的步骤8的示意图暨本发明的TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2,本发明提供一种TFT基板的制作方法,包括如下步骤:
步骤1、如图3所示,提供一基板10,在所述基板10上依次沉积缓冲层20、及非晶硅锗(a-SiGe)层30。
优选的,所述基板10为玻璃基板。
优选的,所述缓冲层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
步骤2、如图4所示,从所述非晶硅锗层30的上表面对所述非晶硅锗层30进行离子掺杂,从而在所述非晶硅锗层30中形成位于上方的掺杂非晶硅锗层31及位于下方的未掺杂非晶硅锗层32。
具体的,在所述非晶硅锗层30中掺杂的离子为N型离子或P型离子。具体的,所述N型离子可以为磷(P)离子或砷(As)离子;所述P型离子可以为硼(B)离子或镓(Ga)离子。
具体的,所述离子掺杂的方式可以为离子植入机植入掺杂或者气相沉积掺杂。
步骤3、如图5所示,采用快速热退火(RTA)工艺对所述掺杂非晶硅锗层31与未掺杂非晶硅锗层32进行晶化处理,使得所述掺杂非晶硅锗层31与未掺杂非晶硅锗层32分别转化为掺杂多晶硅锗(poly-SiGe)层33与未掺杂多晶硅锗(poly-SiGe)层34,所述掺杂多晶硅锗层33与未掺杂多晶硅锗层34共同构成有源层40。
具体的,本发明采用快速热退火(RTA)工艺对所述掺杂非晶硅锗层31与未掺杂非晶硅锗层32进行晶化处理,由于该晶化过程是从掺杂非晶硅锗层31开始,且掺杂非晶硅锗层31的晶化温度较低,因此该晶化过程可以在较低的温度下进行,而与掺杂非晶硅锗层31接触的未掺杂非晶硅锗层32在该低温下可以继续结晶,从而得到掺杂多晶硅锗层33和未掺杂多晶硅锗层34,相较于现有的固相晶化(SPC)等结晶工艺来说,本发明的结晶制程可以在更低的温度下进行,并且能够缩短结晶时间,改善结晶效果,可制得更大更均匀的晶粒。
步骤4、如图6所示,采用一道光刻制程对所述掺杂多晶硅锗层33进行图案化处理,形成间隔设置的源极接触区41与漏极接触区42。
值得一提的是,该步骤4中也可以通过干法蚀刻制程将所述掺杂多晶硅锗层33全部去除,从而后续步骤中所形成的源极、漏极可直接与所述未掺杂多晶硅锗层34的两侧区域相接触。
步骤5、如图7所示,采用一道光刻制程对所述未掺杂多晶硅锗层34进行图案化处理,使其左、右两侧分别与源极接触区41的左侧、及漏极接触区42的右侧相对应,所述未掺杂多晶硅锗层34上对应所述源极接触区41与漏极接触区42之间的部分形成沟道区43。
步骤6、如图8所示,在所述有源层40上沉积栅极绝缘层50,在所述栅极绝缘层50上沉积第一金属层,采用一道光刻制程对所述第一金属层进行图案化处理,得到对应沟道区43上方的栅极60。
具体的,所述第一金属层的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
步骤7、如图9所示,在所述栅极60、及栅极绝缘层50上沉积层间绝缘层70,采用一道光刻制程对所述层间绝缘层70与栅极绝缘层50进行图案化处理,在所述层间绝缘层70与栅极绝缘层50上形成分别对应于源极接触区41、及漏极接触区42的第一、第二过孔71、72。
具体的,所述层间绝缘层70可为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
步骤8、如图10所示,在所述层间绝缘层70上沉积第二金属层,采用一道光刻制程对所述第二金属层进行图案化处理,得到源极81与漏极82,所述源极81、及漏极82分别经由第一、第二过孔71、72与源极接触区41、及漏极接触区42相接触。
具体的,所述第二金属层的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
本发明提供的一种TFT基板的制作方法,通过在基板上沉积缓冲层与非晶硅锗(a-SiGe)层,在所述非晶硅锗层的上部植入掺杂离子,形成掺杂非晶硅锗层,然后采用快速热退火(RTA)工艺对所述掺杂非晶硅锗层和未掺杂非晶硅锗层进行晶化处理,由于该晶化过程是从掺杂非晶硅锗层开始,且掺杂非晶硅锗层的晶化温度较低,因此该晶化过程可以在较低的温度下进行,而与掺杂非晶硅锗层接触的未掺杂非晶硅锗层在该低温下可以继续结晶,从而得到掺杂多晶硅锗(poly-SiGe)层和未掺杂多晶硅锗(poly-SiGe)层,相较于现有的固相晶化(SPC)等结晶工艺来说,本发明的结晶制程可以在更低的温度下进行,并且能够缩短结晶时间,改善结晶效果,可制得更大更均匀的晶粒。
请参阅图10,基于上述制作方法,本发明还提供一种TFT基板,包括基板10、设于所述基板10上的缓冲层20、设于所述缓冲层20上的有源层40、设于所述有源层40上的栅极绝缘层50、设于所述栅极绝缘层50上的栅极60、设于所述栅极60及栅极绝缘层50上的层间绝缘层70、及设于所述层间绝缘层70上的源极81与漏极82;
其中,所述有源层40包括未掺杂多晶硅锗层34、及位于所述未掺杂多晶硅锗层34上方的掺杂多晶硅锗层33,所述掺杂多晶硅锗层33包括分别对应所述未掺杂多晶硅锗层34两侧的源极接触区41与漏极接触区42,所述层间绝缘层70与栅极绝缘层50上设有分别对应于源极接触区41、及漏极接触区42的第一、第二过孔71、72,所述源极81、及漏极82分别经由第一、第二过孔71、72与源极接触区41、及漏极接触区42相接触。
具体的,所述未掺杂多晶硅锗层34上对应所述源极接触区41与漏极接触区42之间的部分形成沟道区43,所述栅极60对应沟道区43上方设置。
优选的,所述基板10为玻璃基板。
优选的,所述缓冲层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的,所述掺杂多晶硅锗层33为N型掺杂多晶硅锗层或P型掺杂多晶硅锗层。具体的,所述N型掺杂多晶硅锗层中掺杂的离子可以为磷(P)离子或砷(As)离子;所述P型掺杂多晶硅锗层中掺杂的离子可以为硼(B)离子或镓(Ga)离子。
具体的,所述层间绝缘层70可为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的,所述栅极60、源极81、及漏极82的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
综上所述,本发明提供的一种TFT基板的制作方法,通过在基板上沉积缓冲层与非晶硅锗(a-SiGe)层,在所述非晶硅锗层的上部植入掺杂离子,形成掺杂非晶硅锗层,然后采用快速热退火(RTA)工艺对所述掺杂非晶硅锗层和未掺杂非晶硅锗层进行晶化处理,由于该晶化过程是从掺杂非晶硅锗层开始,且掺杂非晶硅锗层的晶化温度较低,因此该晶化过程可以在较低的温度下进行,而与掺杂非晶硅锗层接触的未掺杂非晶硅锗层在该低温下可以继续结晶,从而得到掺杂多晶硅锗(poly-SiGe)层和未掺杂多晶硅锗(poly-SiGe)层,相较于现有的固相晶化(SPC)等结晶工艺来说,本发明的结晶制程可以在更低的温度下进行,并且能够缩短结晶时间,改善结晶效果,可制得更大更均匀的晶粒。本发明提供的一种TFT基板,采用掺杂多晶硅锗(poly-SiGe)层作为有源层的源、漏极接触区,导电性能好,可以与源、漏极之间形成良好的欧姆接触,提高了TFT基板的电学性能。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。
Claims (5)
1.一种TFT基板的制作方法,其特征在于,包括如下步骤:
步骤1、提供一基板(10),在所述基板(10)上依次沉积缓冲层(20)、及非晶硅锗层(30);
步骤2、从所述非晶硅锗层(30)的上表面对所述非晶硅锗层(30)进行离子掺杂,从而在所述非晶硅锗层(30)中形成位于上方的掺杂非晶硅锗层(31)及位于下方的未掺杂非晶硅锗层(32);
步骤3、采用快速热退火工艺对所述掺杂非晶硅锗层(31)与未掺杂非晶硅锗层(32)进行晶化处理,使得所述掺杂非晶硅锗层(31)与未掺杂非晶硅锗层(32)分别转化为掺杂多晶硅锗层(33)与未掺杂多晶硅锗层(34),所述掺杂多晶硅锗层(33)与未掺杂多晶硅锗层(34)共同构成有源层(40);
步骤4、采用一道光刻制程对所述掺杂多晶硅锗层(33)进行图案化处理,形成间隔设置的源极接触区(41)与漏极接触区(42);
步骤5、采用一道光刻制程对所述未掺杂多晶硅锗层(34)进行图案化处理,使其左、右两侧分别与源极接触区(41)的左侧、及漏极接触区(42)的右侧相对应,所述未掺杂多晶硅锗层(34)上对应所述源极接触区(41)与漏极接触区(42)之间的部分形成沟道区(43);
步骤6、在所述有源层(40)上沉积栅极绝缘层(50),在所述栅极绝缘层(50)上沉积第一金属层,采用一道光刻制程对所述第一金属层进行图案化处理,得到对应沟道区(43)上方的栅极(60);
步骤7、在所述栅极(60)、及栅极绝缘层(50)上沉积层间绝缘层(70),采用一道光刻制程对所述层间绝缘层(70)与栅极绝缘层(50)进行图案化处理,在所述层间绝缘层(70)与栅极绝缘层(50)上形成分别对应于源极接触区(41)、及漏极接触区(42)的第一、第二过孔(71、72);
步骤8、在所述层间绝缘层(70)上沉积第二金属层,采用一道光刻制程对所述第二金属层进行图案化处理,得到源极(81)与漏极(82),所述源极(81)、及漏极(82)分别经由第一、第二过孔(71、72)与源极接触区(41)、及漏极接触区(42)相接触。
2.如权利要求1所述的TFT基板的制作方法,其特征在于,所述基板(10)为玻璃基板;所述缓冲层(20)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层。
3.如权利要求1所述的TFT基板的制作方法,其特征在于,在所述非晶硅锗层(30)中掺杂的离子为N型离子或P型离子,所述离子掺杂的方式为离子植入机植入掺杂或者气相沉积掺杂。
4.如权利要求3所述的TFT基板的制作方法,其特征在于,所述N型离子为磷离子或砷离子;所述P型离子为硼离子或镓离子。
5.如权利要求1所述的TFT基板的制作方法,其特征在于,所述层间绝缘层(70)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层;所述第一金属层、第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510894341.2A CN105355593B (zh) | 2015-12-07 | 2015-12-07 | Tft基板的制作方法及tft基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510894341.2A CN105355593B (zh) | 2015-12-07 | 2015-12-07 | Tft基板的制作方法及tft基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105355593A CN105355593A (zh) | 2016-02-24 |
CN105355593B true CN105355593B (zh) | 2018-07-10 |
Family
ID=55331533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510894341.2A Active CN105355593B (zh) | 2015-12-07 | 2015-12-07 | Tft基板的制作方法及tft基板 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105355593B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106783542A (zh) * | 2016-12-23 | 2017-05-31 | 苏州工业园区纳米产业技术研究院有限公司 | Lpcvd法沉积硅锗膜的方法 |
CN107359203A (zh) * | 2017-05-12 | 2017-11-17 | 惠科股份有限公司 | 显示面板和显示装置 |
CN107342297A (zh) * | 2017-06-28 | 2017-11-10 | 深圳市华星光电半导体显示技术有限公司 | 薄膜晶体管阵列基板及其制备方法、显示装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101086968A (zh) * | 2006-06-09 | 2007-12-12 | 三星电子株式会社 | 底栅薄膜晶体管及其制造方法 |
CN101404295A (zh) * | 2007-10-05 | 2009-04-08 | 株式会社半导体能源研究所 | 薄膜晶体管、及具有其的显示装置、和其制造方法 |
CN101527320A (zh) * | 2007-12-03 | 2009-09-09 | 株式会社半导体能源研究所 | 半导体装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5466933B2 (ja) * | 2009-12-03 | 2014-04-09 | 株式会社ジャパンディスプレイ | 薄膜トランジスタおよびその製造方法 |
-
2015
- 2015-12-07 CN CN201510894341.2A patent/CN105355593B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101086968A (zh) * | 2006-06-09 | 2007-12-12 | 三星电子株式会社 | 底栅薄膜晶体管及其制造方法 |
CN101404295A (zh) * | 2007-10-05 | 2009-04-08 | 株式会社半导体能源研究所 | 薄膜晶体管、及具有其的显示装置、和其制造方法 |
CN101527320A (zh) * | 2007-12-03 | 2009-09-09 | 株式会社半导体能源研究所 | 半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN105355593A (zh) | 2016-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105552027B (zh) | 阵列基板的制作方法及阵列基板 | |
CN105470197B (zh) | 低温多晶硅阵列基板的制作方法 | |
JP4026182B2 (ja) | 半導体装置の製造方法、および電子機器の製造方法 | |
JP4700160B2 (ja) | 半導体装置 | |
CN105489552B (zh) | Ltps阵列基板的制作方法 | |
JP2000101088A (ja) | 電気光学装置、電気光学装置用の駆動基板、及びこれらの製造方法 | |
CN110148600A (zh) | 阵列基板及制备方法 | |
WO2017128564A1 (zh) | 氧化硅薄膜的沉积方法及低温多晶硅tft基板的制备方法 | |
CN102832169A (zh) | 阵列基板及其制备方法、显示器件 | |
CN105355593B (zh) | Tft基板的制作方法及tft基板 | |
CN105679705B (zh) | 阵列基板的制作方法 | |
US10693011B2 (en) | Thin film transistor array substrate, method of manufacturing the same, and display device including thin film transistor substrate | |
CN105679772B (zh) | 低温多晶硅tft基板的制作方法及低温多晶硅tft基板 | |
CN105702622B (zh) | 低温多晶硅tft基板的制作方法及低温多晶硅tft基板 | |
US9837542B2 (en) | Polycrystalline silicon thin-film transistor | |
JP2000208422A (ja) | 積層膜形成方法及び薄膜製造装置 | |
US9136354B2 (en) | Methods for manufacturing passivation layer and thin film transistor array substrate | |
CN105514123B (zh) | Ltps阵列基板的制作方法 | |
TW200421618A (en) | Low temperature poly silicon thin film transistor and method of forming poly silicon layer of the same | |
US7678623B2 (en) | Staggered source/drain and thin-channel TFT structure and fabrication method thereof | |
KR100525436B1 (ko) | 다결정화 방법과 이를 이용한 액정표시장치 제조방법 | |
CN106711157B (zh) | Ltps阵列基板的制作方法 | |
JP4547857B2 (ja) | トランジスタの製造方法 | |
CN100536117C (zh) | 薄膜晶体管面板的制造方法 | |
CN105679764B (zh) | Tft基板的制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |