CN105280696A - AlGaN/GaN high electron mobility transistor with multi-channel fin-type structure - Google Patents
AlGaN/GaN high electron mobility transistor with multi-channel fin-type structure Download PDFInfo
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- 229910002704 AlGaN Inorganic materials 0.000 title claims abstract description 113
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- 238000001312 dry etching Methods 0.000 claims description 9
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- 230000008569 process Effects 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 description 13
- 238000001704 evaporation Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 230000008021 deposition Effects 0.000 description 8
- 238000005566 electron beam evaporation Methods 0.000 description 8
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- 239000002090 nanochannel Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses a AlGaN/GaN high electron mobility transistor structure with a multi-channel fin-type structure and a manufacturing method, wherein the AlGaN/GaN high electron mobility transistor is designed mainly to solve the problems of the poor gate control ability of a multi-channel apparatus and low electric current of a FinFET apparatus; the AlGaN/GaN high electron mobility transistor comprises a substrate (1), a first layer AlGaN/GaN heterojunction (2), a SiN passivation layer (4) and a source electrode, a drain electroce, and a gate electrode successively from bottom to top; the source electrode and the drain electrode are located on AlGaN potential barrier layers on top layers at two sides of the SiN passivation layer respectively; the AlGaN/GaN high electron mobility transistor is characterized in that a GaN layer and the AlGaN potential barrier layer are set between the first layer AlGaN/GaN heterojunction and the SiN passivation layer so as to form a second layer AlGaN/GaN heterojuntion (3); and the gate electrode covers the top portion of a second layer heterojuntion and the two side walls of the first and the second heterojunctions. According to the invention, the gate control ability is strong; the saturation current is large; the subthreshold property is good; and the AlGaN/GaN high electron mobility transistor can be used for microwave power apparatus with a shrot gate length, low power consumption and low noise.
Description
Technical field
The invention belongs to microelectronics technology, relate to semiconductor device structure and making, particularly a kind of AlGaN/GaN high electron mobility transistor (HEMT) of many raceway grooves fin structure, can be used for making large scale integrated circuit.
Background technology
In recent years with SiC and the GaN third generation wide bandgap semiconductor that is representative with characteristics such as its large energy gap, high breakdown electric field, high heat conductance, high saturated electrons speed and heterojunction boundary two-dimensional electron gas 2DEG concentration are high, make it be subject to extensive concern.In theory, the device such as high electron mobility transistor (HEMT), LED, laser diode LD utilizing these materials to make has obvious advantageous characteristic than existing device, therefore researcher has carried out extensive and deep research to it both at home and abroad in the last few years, and achieves the achievement in research attracted people's attention.
AlGaN/GaN heterojunction high electron mobility transistor (HEMT) has shown advantageous advantage in high-temperature device and HIGH-POWERED MICROWAVES device, and pursuit device high-frequency, high pressure, high power have attracted numerous research.In order to promote the application of GaN heterojunction device in the more field such as big current, more high power, more low-power consumption, higher frequency, switching mode, multivalued gate further, the research for many raceway grooves Multiple heterostructures materials and devices just seems necessary.
2005, RongmingChu reported AlGaN/GaN/AlGaN/GaN material structure, and completed the HEMT device of double channel simultaneously.See RongmingChu, etal, AlGaN/GaNDouble-ChannelHEMTs, IEEETranscationsonelectrondevices, 2005.52 (4): 438.Because this structure has two GaN layer as channel layer, therefore be called as double channel AlGaN/GaN heterojunction.Prove by experiment, in double channel, the raceway groove of the most contiguous grid can have the few affected effect of shielding bottom raceway groove in high temperature, high pressure, high frequency etc.Compared with single raceway groove AlGaN/GaN heterojunction, double channel AlGaN/GaN heterojunction can have higher two-dimensional electron gas gross density, and this makes device saturation current increase considerably, and for the device of power application, the raising of saturation current is most important.But the total barrier layer thickness of double channel AlGaN/GaN heterojunction material increases, device gate is increased with channel distance below, and reduce grid-control ability, device transconductance peak value declines to some extent.
2013, the people such as Lu Ming to prepare etc. the structure simulation of triple channel AlGaN/GaN heterojunction material, Material growth, device and have carried out further research.See Lu Ming master's thesis, triple channel AlGaN/GaN heterojunction material and device are studied.Along with the increase of raceway groove quantity, the number of plies of the heterojunction be made up of AlGaN/GaN also increases, and makes device have the Two-dimensional electron gas-bearing formation of three layers to be connected in parallel between source and drain, further reduces channel resistance like this, improve device source leakage current.But, along with the increase of raceway groove quantity, from grid more away from the control that is subject to of raceway groove more weak, the control ability of grid voltage declines and causes mutual conductance peak value to decline, device gain decline.And due to the decline of grid-control ability, the negative sense of threshold voltage moves very large.The raising of grid to the control ability of multiple raceway groove is a challenge.
Adopt the AlGaN/GaNHEMT device of FinFET structure making relative to common GaN base HEMT device, there is more advantage.The maximum advantage of FinFET structure have employed 3-D solid structure exactly, by grid, raceway groove is wrapped up from three directions, raceway groove can be subject to grid in three directions and control preferably, make device in channel length very in short-term, improve grid-control ability, improve short-channel effect, reduce off-state leakage current.In high-speed high frequency application aspect, FinFET structure device has low leakage current and good Sub-Threshold Characteristic.
The people such as Cai Yong report nano-channel array AlGaN/GaNHEMT.See ShenghouLiu, YongCai, GuodongGu, etal.Enhancement-ModeOperationofNanochannelArray (NCA) AlGaN/GaNHEMTs, IEEEELECTRONDEVICELETTERS, 2012, VOL.33, NO.3.The FinFET structure of three ring grid greatly strengthen the control ability of grid.But the stress relaxation occurred in raceway groove reduces the piezoelectric polarization at heterojunction place, the electron gas concentration be present near heterojunction is declined, make threshold voltage meeting forward migration.Along with the reduction of nano-channel width, the peak transconductance of device increases gradually, and the mutual conductance with nano-channel array device is all larger than conventional device, and peak transconductance increases 55%.But because FinFET structure device has the grid width of nanometer scale, and reducing of grid width makes source-drain current obviously decline, the current driving ability of device declines, and is unfavorable for the application of device in high-power.
The people such as Ki-Sik adopt FinFET structure on conventional potential barrier thickness AlGaN/GaN heterojunction, have studied the making of enhancement device, see Ki-SikIm, Dong-HyeokSon, Ho-KyunAhn, etal.PerformanceimprovementofnormallyoffAlGaN/GaNFinFETs withfullygate-coverednanochannel, Solid-StateElectronics2013,89:124 – 127.The device of this result of study report makes current on/off ratio larger, and subthreshold behavior is more excellent, and power consumption is lower, lays a good foundation for realizing high stability GaN base digital circuit.In order to further improve GaN base digital circuit characteristic, nanoscale grid length and grid width must be adopted, but the nanoscale grid width of FinFET can make the current driving ability of circuit devcie unit weaken, saturation current reduces, and can not meet the application requirement of GaN base electronic device in high-voltage switch gear, digital circuit field.
Summary of the invention
The object of the invention is to for above many raceway grooves heterojunction device grid-control ability and the lower deficiency of FinFET structure device current driving force, there is provided a kind of AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure, to meet the application requirement of GaN base electronic device in high-voltage switch gear, digital circuit field.
Technical thought of the present invention is: to AlGaN/GaN double heterojunction or AlGaN/GaN tri-heterojunction material, and the single grid width in design 100nm, forms three-dimensional FinFET structure.The employing of AlGaN/GaN double heterojunction or AlGaN/GaN tri-heterojunction material structure makes the two-dimensional electron gas path forming multiple parallel connection between source and drain, reduces the conducting resistance between source and drain, increased device electric current.The key that three-dimensional FinFET structure is formed is, when being formed with region meas etching, design device unit grid is wide is less than 100nm.The grid width being less than 100nm makes device side grid play control ability, improves grid-control ability and increased device mutual conductance.
In the growth of AlGaN/GaN double heterojunction or AlGaN/GaN tri-heterojunction material structure, realize every layer of conduction two-dimensional electron gas and all there is higher mobility and electron concentration, ensure that the structure of many channels connected in parallel makes the conducting resistance between device source and drain obviously reduce.In FinFET structure is formed, adopt dry etch process to ensure the precipitous of grid fin side, and ensure that the height of grid fin is obviously greater than the thickness of potential barrier of heterogenous junction layer, realize the isolation of device.
According to above-mentioned technical thought, the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure of the present invention, comprise substrate, ground floor AlGaN/GaN heterojunction, SiN passivation layer and source and drain gate electrode from bottom to top, source electrode and drain electrode lay respectively in the top layer AlGaN potential barrier of SiN passivation layer both sides, it is characterized in that:
Be provided with GaN layer and AlGaN potential barrier between AlGaN/GaN heterojunction and SiN passivation layer, form second layer AlGaN/GaN heterojunction;
Gate electrode covers the top of second layer heterojunction and two sidewalls of ground floor heterojunction and second layer heterojunction.
According to above-mentioned technical thought, the present invention makes the manufacture method of the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure, comprises the steps:
(1) on sapphire or SiC substrate, utilize MOCVD technique, growing GaN layer and AlGaN potential barrier form ground floor AlGaN/GaN heterojunction successively, and wherein GaN thickness is 1 ~ 2 μm, AlGaN potential barrier thickness is 15 ~ 25nm, and its Al component is 25 ~ 35%;
(2) GaN and AlGaN of repeated growth same structure once or twice on ground floor AlGaN/GaN heterojunction, obtain double heterojunction or three heterojunction, form many channel structures, wherein GaN thickness is 20 ~ 30nm, AlGaN potential barrier thickness is 15 ~ 25nm, and its Al component is 25 ~ 35%;
(3) on all heterojunction, carry out active area dry etching and mesa-isolated, form the grid fin that width is 30 ~ 100nm;
(4) at making source, AlGaN potential barrier both sides, the leakage Ohm contact electrode of upper space;
(5) adopt pecvd process, between source-drain electrode, carry out the thick SiN layer deposit of 50 ~ 100nm cover its surface formation passivation layer;
(6) in the middle of SiN passivation layer, ICP dry etching equipment is adopted, at CF
4under the etch rate of plasma 0.5nm/s, dry etching goes out grid groove, and depositing metal forms gate electrode, makes two sidewalls of two sidewalls of its top covering second layer heterojunction and ground floor heterojunction and second layer heterojunction or the top of third layer heterojunction and ground floor heterojunction, second layer heterojunction and third layer heterojunction;
(7) interconnecting line is made.
As preferably, the AlGaN/GaN High Electron Mobility Transistor of above-mentioned many raceway grooves fin structure, is characterized in that: AlGaN potential barrier thickness is 15 ~ 25nm, and its Al component is 25 ~ 35%.
As preferably, the AlGaN/GaN High Electron Mobility Transistor of above-mentioned many raceway grooves fin structure, is characterized in that: device gate fin width is less than 100nm.
Device of the present invention is owing to adopting the three-dimensional grid structure of the AlGaN/GaN heterojunction structure of many raceway grooves and FinFET, and thus tool has the following advantages compared with existing similar device:
1) make the two-dimensional electron gas path that can form multiple parallel connection between source and drain, the formation of the plurality of channels connected in parallel path reduces the resistance between source and drain greatly, makes device have less ON resistance, has larger current driving ability simultaneously.
2) grid are not only controlled raceway groove from upper end, and the grid width within 100nm makes gate electrode to control channel electrons from the side, obviously strengthen grid-control ability, improve device transconductance and device gain ability.
3) enhance grid-control ability, effectively can reduce the off-state leakage current of device, reduce the quiescent dissipation of device.
4) reduce the subthreshold swing of device, and make device have good switching characteristic.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram;
Fig. 2 is the end view of Fig. 1;
Fig. 3 is the fabrication processing schematic diagram of device of the present invention.
Embodiment
With reference to Fig. 1, device of the present invention comprises sapphire or SiC substrate 1, ground floor AlGaN/GaN heterojunction 2, second layer AlGaN/GaN heterojunction 3, SiN passivation layer 4 and source electrode, drain electrode, gate electrode.Wherein orlop is sapphire or SiC substrate 1, it substrate is intrinsic GaN layer that thickness is 1 ~ 2 μm, intrinsic GaN layer is 15 ~ 25nm is thick, Al component is the AlGaN potential barrier of 25 ~ 35%, form ground floor AlGaN/GaN heterojunction 2, it is 20 ~ 30nm that this ground floor AlGaN/GaN heterojunction 2 is provided with GaN layer thickness, AlGaN potential barrier thickness is 15 ~ 25nm, Al component is the second layer AlGaN/GaN heterojunction 3 of 25 ~ 35%, above second layer AlGaN/GaN heterojunction 3, namely top layer is AlGaN potential barrier, source electrode and drain electrode lay respectively at top layer AlGaN potential barrier both sides, thickness is that the SiN passivation layer 4 of 50 ~ 100nm is deposited between source electrode and drain electrode, gate electrode covers the top of second layer heterojunction 3 and two sidewalls of ground floor heterojunction 2 and second layer heterojunction 3, form the rectangle frame of a half opening, as shown in Figure 2.
With reference to Fig. 3, the making of device of the present invention provides following three kinds of embodiments.
Embodiment 1: make the double channel fin AlGaN/GaN High Electron Mobility Transistor that grid fin width is 100nm.
Step 1. utilizes MOCVD technique, epitaxial growth double heterojunction.
1.1) on SiC substrate substrate, growth thickness is the intrinsic GaN layer of 1 μm;
1.2) in intrinsic GaN layer, grow the thick AlGaN potential barrier of 15nm, wherein Al component is 35%, forms two-dimensional electron gas at the contact position of intrinsic GaN layer and AlGaN potential barrier, obtains ground floor AlGaN/GaN heterojunction;
1.3) in the thick AlGaN potential barrier of 15nm, regrowth second layer thickness is the intrinsic GaN layer of 20nm;
1.4) in second layer intrinsic GaN layer, grow the thick AlGaN potential barrier of second layer 15nm, wherein Al component is 35%, obtains second layer AlGaN/GaN heterojunction.
The process conditions of this step are: with NH
3for N source, MO source is Ga source, and growth temperature is 1000 DEG C.
Step 2. makes grid fin and active area.
2.1) first adopt photoresist spinner whirl coating under the rotating speed of 3500 turns/min, obtain photoresist mask; Adopt electron beam E-beam mask aligner to expose again, form the mask graph of table top active area and the wide grid fin of 100nm;
2.2) adopted by the substrate carrying out mask ICP98c type sense coupling machine at Cl
2carry out mesa-isolated and grid fin etching with the etch rate of 1nm/s in plasma, etching depth is 150nm.
Step 3. electrode fabrication and device passivation.
3.1) source-drain electrode makes:
First, adopt photoresist spinner whirl coating under the rotating speed of 5000 turns/min, obtain photoresist mask thickness 0.8 μm;
Then, be dry 10min in the high temperature oven of 80 DEG C in temperature, adopt NSR1755I7A mask aligner to expose, form source, drain region mask graph;
Then, adopt Ohmiker-50 electron beam evaporation platform to carry out source-drain electrode making with the evaporation rate of 0.1nm/s, source and drain metal selects Ti/Al/Ni/Au successively, and wherein Ti thickness is 20nm, Al thickness be 120nm, Ni thickness be 45nm, Au thickness is 55nm; Source and drain metal ohmic contact has evaporated laggard row metal to be peeled off;
Finally, then use RTP500 rapid thermal anneler, at the N of 870 DEG C
2carry out the rapid thermal annealing of 30s in atmosphere, alloy is carried out to metal ohmic contact, complete the making of source, drain electrode;
3.2) adopt PECVD790 deposition apparatus with NH
3for N source, SiH
4source is Si source, and in the superiors' AlGaN potential barrier, deposition thickness is the SiN passivation layer of 100nm, and deposition temperature is 250 DEG C;
3.3) grid groove is made:
First, with the rotating speed of 5000 turns/min at extension material surface positive-glue removing, obtain the photoresist mask that thickness is 0.8 μm, then be dry 10min in the high temperature oven of 80 DEG C in temperature, then adopt the photoetching of NSR1755I7A mask aligner to obtain gate electrode figure;
Then, adopt ICP98c type sense coupling machine at CF
4remove the thick SiN layer of gate region 100nm with the etch rate of 0.5nm/s etching in plasma, form slot grid structure;
3.4) gate electrode is made:
First, adopt photoresist spinner whirl coating under the rotating speed of 5000 turns/min, obtaining photoresist mask thickness is 0.8 μm;
Then, be dry 10min in the high temperature oven of 80 DEG C in temperature, adopt NSR1755I7A mask aligner to expose, lithography alignment forms the gate region mask graph covering whole grid groove;
Finally, Ohmiker-50 electron beam evaporation platform is adopted to carry out the evaporation of grid metal with the evaporation rate of 0.1nm/s, make two sidewalls of its top covering second layer heterojunction and ground floor heterojunction and second layer heterojunction, grid metal selects Ni/Au successively, wherein Ni thickness is 20nm, Au thickness is 200nm; Evaporate laggard row metal to peel off, obtain complete gate electrode.
Step 4. makes interconnecting pins.
First adopt photoresist spinner positive-glue removing under the rotating speed of 5000 turns/min;
Adopt NSR1755I7A mask aligner to expose again, form contact conductor mask graph;
Then adopt Ohmiker-50 electron beam evaporation platform to carry out the evaporation of lead-in wire electrode metal with the evaporation rate of 0.3nm/s to the substrate making mask, it is 200nm that metal selects Ti thickness to be 20nm, Au thickness; Finally evaporate laggard row at lead-in wire electrode metal to peel off, obtain complete lead-in wire electrode.
Embodiment 2: make the triple channel fin AlGaN/GaN High Electron Mobility Transistor that grid fin width is 50nm.
Step one. utilize MOCVD technique, epitaxial growth three heterojunction.
1a) on sapphire substrate, with NH
3for N source, MO source is Ga source, and growth temperature is 1000 DEG C, and growth thickness is the intrinsic GaN layer of 1.5 μm;
1b) in intrinsic GaN layer, the AlGaN potential barrier that growth 20nm is thick, wherein Al component is 30%, forms two-dimensional electron gas at the contact position of intrinsic GaN layer and AlGaN potential barrier, obtains ground floor AlGaN/GaN heterojunction;
1c) in the thick AlGaN potential barrier of ground floor 20nm, grow the intrinsic GaN layer that the second layer thickness is 25nm;
1d) in second layer intrinsic GaN layer, grow the thick AlGaN potential barrier of second layer 20nm, wherein Al component is 30%, obtains second layer AlGaN/GaN heterojunction;
1e) in the thick AlGaN potential barrier of second layer 20nm, growth regulation threeply degree is the intrinsic GaN layer of 25nm;
1f) in third layer intrinsic GaN layer, grow the thick AlGaN potential barrier of third layer 20nm, wherein Al component is 30%, obtains third layer AlGaN/GaN heterojunction.
Above-mentioned steps 1b) ~ 1f) process conditions and 1a) identical.
Step 2. make grid fin and active area.
2a) first adopt photoresist spinner whirl coating under the rotating speed of 3500 turns/min, obtain photoresist mask; Adopt electron beam E-beam mask aligner to expose again, form the mask graph of table top active area and the wide grid fin of 50nm;
2b) adopted by the substrate carrying out mask ICP98c type sense coupling machine at Cl
2carry out mesa-isolated and grid fin etching with the etch rate of 1nm/s in plasma, etching depth is 175nm.
Step 3. electrode fabrication and device passivation.
3a) source-drain electrode makes:
3a1) adopt photoresist spinner whirl coating under the rotating speed of 5000 turns/min, obtain photoresist mask thickness 0.8 μm;
Be 3a2) dry 10min in the high temperature oven of 80 DEG C in temperature, adopt NSR1755I7A mask aligner to expose, form source, drain region mask graph;
3a3) adopt Ohmiker-50 electron beam evaporation platform to carry out source-drain electrode making with the evaporation rate of 0.1nm/s, source and drain metal selects Ti/Al/Ni/Au successively, and wherein Ti thickness is 20nm, Al thickness be 120nm, Ni thickness be 45nm, Au thickness is 55nm; Source and drain metal ohmic contact has evaporated laggard row metal to be peeled off;
3a4) use RTP500 rapid thermal anneler, at the N of 870 DEG C
2carry out the rapid thermal annealing of 30s in atmosphere, alloy is carried out to metal ohmic contact, complete the making of source, drain electrode;
3b) adopt PECVD790 deposition apparatus with NH
3for N source, SiH
4source is Si source, and in the superiors' AlGaN potential barrier, deposition thickness is the SiN passivation layer of 75nm, and deposition temperature is 250 DEG C;
3c) make grid groove:
3c1) with the rotating speed of 5000 turns/min at extension material surface positive-glue removing, obtain the photoresist mask that thickness is 0.8 μm, then be dry 10min in the high temperature oven of 80 DEG C in temperature, then adopt the photoetching of NSR1755I7A mask aligner to obtain gate electrode figure;
3c2) adopt ICP98c type sense coupling machine at CF
4remove the thick SiN layer of gate region 75nm with the etch rate of 0.5nm/s etching in plasma, form slot grid structure;
3d) make gate electrode:
3d1) adopt photoresist spinner whirl coating under the rotating speed of 5000 turns/min, obtaining photoresist mask thickness is 0.8 μm;
Be 3d2) dry 10min in the high temperature oven of 80 DEG C in temperature, adopt NSR1755I7A mask aligner to expose, lithography alignment forms the gate region mask graph covering whole grid groove;
Ohmiker-50 electron beam evaporation platform 3d3) is adopted to carry out the evaporation of grid metal with the evaporation rate of 0.1nm/s, make two sidewalls of its top covering third layer heterojunction and ground floor, the second layer and third layer heterojunction, grid metal selects Ni/Au successively, wherein Ni thickness is 20nm, Au thickness is 200nm; Evaporate laggard row metal to peel off, obtain complete gate electrode.
Step 4. make interconnecting pins.
First adopt photoresist spinner positive-glue removing under the rotating speed of 5000 turns/min; Adopt NSR1755I7A mask aligner to expose again, form contact conductor mask graph; Then adopt Ohmiker-50 electron beam evaporation platform to carry out the evaporation of lead-in wire electrode metal with the evaporation rate of 0.3nm/s to the substrate making mask, it is 200nm that metal selects Ti thickness to be 20nm, Au thickness; Finally evaporate laggard row at lead-in wire electrode metal to peel off, obtain complete lead-in wire electrode.
Embodiment 3: make the double channel fin AlGaN/GaN High Electron Mobility Transistor that grid fin width is 30nm.
Steps A. utilize MOCVD technique, epitaxial growth double heterojunction.
With NH
3for N source, MO source is Ga source, and growth temperature is under the process conditions of 1000 DEG C, and first on SiC substrate substrate, growth thickness is the intrinsic GaN layer of 2 μm; Again in intrinsic GaN layer, the AlGaN potential barrier that growth 25nm is thick, wherein Al component is 25%, forms two-dimensional electron gas at the contact position of intrinsic GaN layer and AlGaN potential barrier, obtains ground floor AlGaN/GaN heterojunction; Then in the thick AlGaN potential barrier of 25nm, the intrinsic GaN layer that the second layer thickness is 30nm is grown; Finally in second layer intrinsic GaN layer, grow the thick AlGaN potential barrier of second layer 25nm, wherein Al component is 25%, obtains second layer AlGaN/GaN heterojunction.
Step B. makes grid fin and active area.
First adopt photoresist spinner whirl coating under the rotating speed of 3500 turns/min, obtain photoresist mask; Adopt electron beam E-beam mask aligner to expose again, form the mask graph of table top active area and the wide grid fin of 30nm; Then adopted by the substrate carrying out mask ICP98c type sense coupling machine at Cl
2carry out mesa-isolated and grid fin etching with the etch rate of 1nm/s in plasma, etching depth is 200nm.
Step C. electrode fabrication and device passivation.
C1) source-drain electrode makes:
First adopt photoresist spinner whirl coating under the rotating speed of 5000 turns/min, obtain photoresist mask thickness 0.8 μm; Be dry 10min in the high temperature oven of 80 DEG C again in temperature, adopt NSR1755I7A mask aligner to expose, form source, drain region mask graph; Then source and drain metal selects Ti/Al/Ni/Au successively, adopts Ohmiker-50 electron beam evaporation platform to carry out source-drain electrode making with the evaporation rate of 0.1nm/s, and wherein Ti thickness is 20nm, Al thickness be 120nm, Ni thickness be 45nm, Au thickness is 55nm; Finally, evaporated laggard row metal at source and drain metal ohmic contact and peeled off, and used RTP500 rapid thermal anneler, at the N of 870 DEG C
2carry out the rapid thermal annealing of 30s in atmosphere, alloy is carried out to metal ohmic contact, complete the making of source, drain electrode;
C2) adopt PECVD790 deposition apparatus with NH
3for N source, SiH
4source is Si source, and at 250 DEG C, in the superiors' AlGaN potential barrier, deposition thickness is the SiN passivation layer of 50nm;
C3) grid groove is made:
With the rotating speed of 5000 turns/min at extension material surface positive-glue removing, obtain the photoresist mask that thickness is 0.8 μm, then be dry 10min in the high temperature oven of 80 DEG C in temperature, then adopt the photoetching of NSR1755I7A mask aligner to obtain gate electrode figure; Adopt ICP98c type sense coupling machine at CF again
4remove the thick SiN layer of gate region 50nm with the etch rate of 0.5nm/s etching in plasma, form slot grid structure;
C4) gate electrode makes:
First adopt photoresist spinner whirl coating under the rotating speed of 5000 turns/min, obtaining photoresist mask thickness is 0.8 μm; Be dry 10min in the high temperature oven of 80 DEG C again in temperature, and expose with NSR1755I7A mask aligner, lithography alignment forms the gate region mask graph covering whole grid groove; Then, Ohmiker-50 electron beam evaporation platform is adopted to carry out the evaporation of grid metal with the evaporation rate of 0.1nm/s, make two sidewalls of its top covering second layer heterojunction and ground floor heterojunction and second layer heterojunction, grid metal selects Ni/Au successively, wherein Ni thickness is 20nm, Au thickness is 200nm; Evaporate laggard row metal to peel off, obtain complete gate electrode.
Step D. makes interconnecting pins.
First adopt photoresist spinner positive-glue removing under the rotating speed of 5000 turns/min; Adopt NSR1755I7A mask aligner to expose again, form contact conductor mask graph; Then adopt Ohmiker-50 electron beam evaporation platform to carry out the evaporation of lead-in wire electrode metal with the evaporation rate of 0.3nm/s to the substrate making mask, it is 200nm that metal selects Ti thickness to be 20nm, Au thickness; Finally evaporate laggard row at lead-in wire electrode metal to peel off, obtain complete lead-in wire electrode.
Claims (10)
1. the AlGaN/GaN High Electron Mobility Transistor of raceway groove fin structure more than a kind, comprise substrate (1), ground floor AlGaN/GaN heterojunction (2), SiN passivation layer (4) and source and drain gate electrode from bottom to top successively, source electrode and drain electrode lay respectively in the top layer AlGaN potential barrier of SiN passivation layer both sides, it is characterized in that:
Be provided with GaN layer and AlGaN potential barrier between ground floor AlGaN/GaN heterojunction (2) and SiN passivation layer (4), form second layer AlGaN/GaN heterojunction (3);
Gate electrode covers the top of second layer heterojunction (3) and two sidewalls of ground floor heterojunction (2) and second layer heterojunction (3).
2. the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure according to claim 1, is characterized in that: substrate (1) is sapphire or SiC substrate.
3. the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure according to claim 1, it is characterized in that: the GaN layer thickness in ground floor AlGaN/GaN heterojunction (2) is 1 ~ 2 μm, the GaN layer thickness in second layer AlGaN/GaN heterojunction (3) is 20 ~ 30nm.
4. the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure according to claim 1, it is characterized in that: the AlGaN potential barrier thickness in ground floor AlGaN/GaN heterojunction (2) in AlGaN potential barrier thickness and second layer AlGaN/GaN heterojunction is 15 ~ 25nm, and its Al component is 25 ~ 35%.
5. the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure according to claim 1, is characterized in that: the thickness of SiN passivation layer (4) is 50 ~ 100nm.
6. the AlGaN/GaN High Electron Mobility Transistor of many raceway grooves fin structure according to claim 1, is characterized in that: grid fin width is 30 ~ 100nm.
7. a manufacture method for the AlGaN/GaN High Electron Mobility Transistor of the fin structure of raceway groove more than, comprises the steps:
1) on sapphire or SiC substrate, utilize MOCVD technique, growing GaN layer and AlGaN potential barrier form ground floor AlGaN/GaN heterojunction successively, and wherein GaN thickness is 1 ~ 2 μm, and AlGaN potential barrier thickness is 15 ~ 25nm, and its Al component is 25 ~ 35%;
2) GaN and AlGaN of repeated growth same structure once or twice on ground floor AlGaN/GaN heterojunction, obtain double heterojunction or three heterojunction, form many channel structures, wherein GaN thickness is 20 ~ 30nm, AlGaN potential barrier thickness is 15 ~ 25nm, and its Al component is 25 ~ 35%;
3) on all heterojunction, carry out active area dry etching and mesa-isolated, form the grid fin that width is 30 ~ 100nm;
4) at making source, AlGaN potential barrier both sides, the leakage Ohm contact electrode of upper space;
5) adopt pecvd process, between source-drain electrode, carry out the thick SiN layer deposit of 50 ~ 100nm cover its surface formation passivation layer;
6) in the middle of SiN passivation layer, ICP dry etching equipment is adopted, at CF
4under the etch rate of plasma 0.5nm/s, dry etching goes out grid groove, and depositing metal forms gate electrode, makes two sidewalls of two sidewalls of its top covering second layer heterojunction and ground floor heterojunction and second layer heterojunction or the top of third layer heterojunction and ground floor heterojunction, second layer heterojunction and third layer heterojunction;
7) interconnecting line is made.
8. the AlGaN/GaN High Electron Mobility Transistor manufacture method of many raceway grooves fin structure according to claim 7, wherein said step 1) in MOCVD technique, be with NH
3for N source, MO source is Ga source, carries out the growth of AlGaN/GaN heterojunction at 1000 DEG C.
9. the AlGaN/GaN High Electron Mobility Transistor manufacture method of many raceway grooves fin structure according to claim 7, wherein said step 3) in carry out mesa-isolated with active area dry etching, formation grid fin, carry out as follows:
9a) first adopt photoresist spinner whirl coating under the rotating speed of 3500 turns/min, obtain photoresist mask; Adopt E-beam mask aligner to expose again, form the mask graph of table top active area and grid fin;
9b) adopt ICP dry etching equipment, at Cl
2under the etch rate of plasma 1nm/s, dry etching is formed with source region and grid fin, and etching depth is much larger than channel thickness.
10. the AlGaN/GaN High Electron Mobility Transistor manufacture method of many raceway grooves fin structure according to claim 7, wherein said step 5) in pecvd process, be with NH
3for N source, SiH
4source is Si source, at 250 DEG C, carry out SiN layer deposit.
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