CN105141347B - Microminiature base station baseband processor chip set - Google Patents
Microminiature base station baseband processor chip set Download PDFInfo
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- CN105141347B CN105141347B CN201510324092.3A CN201510324092A CN105141347B CN 105141347 B CN105141347 B CN 105141347B CN 201510324092 A CN201510324092 A CN 201510324092A CN 105141347 B CN105141347 B CN 105141347B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0617—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal for beam forming
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
- H04B7/086—Weighted combining using weights depending on external parameters, e.g. direction of arrival [DOA], predetermined weights or beamforming
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
- H04L25/03248—Arrangements for operating in conjunction with other apparatus
- H04L25/03286—Arrangements for operating in conjunction with other apparatus with channel-decoding circuitry
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2626—Arrangements specific to the transmitter only
- H04L27/2627—Modulators
- H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
- H04L27/2636—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2689—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation
- H04L27/2695—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation with channel estimation, e.g. determination of delay spread, derivative or peak tracking
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
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- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Mobile Radio Communication Systems (AREA)
- Radio Transmission System (AREA)
Abstract
The present invention provides a kind of microminiature base station baseband processor chip set, including：It receives beam forming chipset, aerial signal merging chipset, user wave beam receiving and transmitting signal processing chip group and sends beam forming chipset；Beam forming chipset is received to connect with the receiving terminal of L antenna of microminiature base station by analog-digital converter, receive beam forming chipset and aerial signal merging chipset and connect, user wave beam receiving and transmitting signal processing chip group merges chipset with aerial signal, transmission beam forming chipset is separately connected, it sends beam forming chipset to connect with the transmitting terminal of L antenna of microminiature base station by digital analog converter, L is the integer more than 1.Above-mentioned microminiature base station baseband processor chip set can solve the problems, such as the pin that very large antenna array and super large calculation amount generate, power consumption, area-constrained, and pass through the hardware spending that fragment optimization minimizes digital beam shaping structures.
Description
Technical field
The present invention relates to wireless communication baseband processor technical field more particularly to a kind of microminiature base station baseband processors
Chipset.
Background technology
5th third-generation mobile communication technology (5-Generation, abbreviation 5G) will be that current widely applied wireless communication is brought
The technological innovation of various aspects is embodied in superelevation transmission bandwidth, ultralow communication delay, higher spectrum utilization efficiency etc..Based on 5G
Requirement, ultra-large aerial array and beam forming technique are likely to become the key technology of 5G communications.
Microminiature hot spot base station is the base station system suitable for 5G super-intensive networking application scenes.Its application scenarios is covered all
Such as office, campus, intensive block, slow-moving vehicle indoor and outdoor situation, usual covering radius are less than hundred meters of ranges.Each 5G
Microminiature base station will provide the broadband data transmission clothes that total rate is up to 10 giga bits per seconds for the user in its overlay area
Business.Prediction result shows that the global annual output of 5G microminiatures base station will occupy an leading position in all kinds of 5G communication base stations.
Microminiature base station needs to support the requirement of its high band wide data transmission by ultra-large aerial array.In general,
To meet the wireless transmission of above-mentioned covered scene, the two-dimensional antenna array of antennas up to a hundred is needed.Simultaneously as day
The limitation of line physical size, carrier wavelength need short enough.Millimeter wave band is current many wireless communication class application studies
One of hot spot.Using the wireless transmission of the wave band, for example, the interval of aerial array can be narrowed down to about using 60GHz radio frequencies
The overall dimensions of 2.5mm, aerial array also substantially reduce.
Since millimeter wave has larger transmission loss, therefore, it is necessary to be provided for micro-base station using beam forming technique
Has directive high energy flow gain.The hardware of existing base station beam forming implements organization plan, and main includes three kinds.The
One, radio frequency analog beam forming.Second, digital beam forming.Third, the forming of analog to digital mixed-beam.In these structures
In scheme, there is radio frequency analog beam forming minimum expense, digital beam forming to have best performance.Analog to digital
Mixed-beam forming is then the compromise of the two.
Implement organization plan for above-mentioned hardware, there has been no ripe system on chip Research of Hardware Implementation.On piece
The hardware realization of system needs to consider each item constraint, including algorithm level constraint, pin constraint, power constraints and area-constrained
Deng.For the base station of the Beamforming technology based on ultra-large aerial array, input and output signal handling capacity is very big.
Processing chip can easily exceed the pin constraint of technique defined.In addition, for the Base-Band Processing of broadband super large operand, if not
Select suitable algorithm and structure, and carry out the processing of rational fragment multinuclear, the power consumption of microminiature base station and it is area-constrained also very
Difficulty is satisfied.
In consideration of it, how to provide it is a kind of can solve pin, power consumption that very large antenna array and super large calculation amount generate,
The microminiature base station baseband processor chip set of area-constrained problem becomes the current technical issues that need to address.
Invention content
The present invention provides a kind of microminiature base station baseband processor chip set, is applied to 5G and wirelessly communicates microminiature hot spot base
In standing, flexibly configurable can solve pin, power consumption that very large antenna array and super large calculation amount generate, area-constrained ask
Topic, and pass through the hardware spending of the digital beam shaping structures of fragment optimization minimum.
In a first aspect, the present invention provides a kind of microminiature base station baseband processor chip set, including：Receive beam forming core
Piece group, aerial signal merge chipset, user wave beam receiving and transmitting signal processing chip group and send beam forming chipset；
The beam forming chipset that receives is connected by the receiving terminal of analog-digital converter and L antenna of microminiature base station
Connect, the reception beam forming chipset and the aerial signal merge chipset and connect, at the user wave beam receiving and transmitting signal
Chipset merges chipset with the aerial signal to reason, the transmission beam forming chipset is separately connected, the transmission wave beam
Forming chipset is connect by digital analog converter with the transmitting terminal of L antenna of microminiature base station, and L is the integer more than 1.
Optionally, the reception beam forming chipset includes：M reception beam forming chip, M are the integer more than 1；
The reception beam forming chip includes：First multiplies module, antenna merging module and output buffer module again；
Described first multiplies module again includes：K groups, every group of U high speed and fixed-point complex multiplication unit, K and U are more than 1
Integer；
The complex multiplication unit, for carrying out beam forming ranking operation from K root antenna received signals；
The antenna merging module includes：U the first addition units；
The accumulator that first addition unit is U inputs, singly exports, for being passed through from K root antenna received signals
The signal for belonging to same receiving area in the signal crossed after the complex multiplication unit carries out beam forming ranking operation carries out
Merge；
The output buffer module is high-speed parallel random access memory ram, for the U the first addition units
Signal after merging carries out temporary processing, and exports to the aerial signal and merge chipset.
Optionally, the aerial signal merging chipset includes：The mutiple antennas of dual input list output form arrangement connection
Signal merges chip, for merging the output signal for receiving beam forming chipset, the signal after merging is defeated
Go out to the user wave beam receiving and transmitting signal processing chip group.
Optionally, the user wave beam receiving and transmitting signal processing chip group includes：N number of user wave beam transmitting-receiving letter being mutually juxtaposed
Number processing chip is used for reception signal of the parallel processing from most U beam shaping zones, and is communicated with macro base station,
The downlink data from macro base station is handled simultaneously, and the downlink signal in most multipair U beamforming transmission region is modulated, will adjust
Signal after system is exported to the transmission beam forming chipset, and N and U are the integer more than 1.
Optionally, the user wave beam receiving and transmitting signal processing chip includes：At uplink signal process part and downlink signal
Manage part；
The uplink signal process part includes：Filtering is equal with fast Fourier transform module, channel estimation module, channel
Weigh module, De-mapping module, de-interleaving block, forward error correction coding module and first circulation redundancy check module；
The filtering and fast Fourier transform module, including：Delay chain type register group, multidiameter delay are filtered
Device and fast fourier transform processor；
The filter processor includes the two-dimensional parallel multiply-add arithmetic element based on single-instruction multiple-data, coordinates institute
Delay chain type register group is stated, for completing multistage filtering operation within a clock cycle；
The fast fourier transform processor includes：Plural butterfly unit, the sequence for the integral number power to 2 are realized
The low latency Fourier transformation of different lengths；
The channel estimation module, for carrying out channel estimation to the signal after Fourier transformation；
The channel equalization module, for the carry out channel equalization after channel estimation；
The De-mapping module, for carrying out bit-detection operation to the signal after channel equalization；
The de-interleaving block, for being deinterleaved to the signal after bit detection calculations；
The forward error correction coding module, for carrying out forward error correction coding to the signal after deinterleaving；
The first circulation redundancy check module, for carrying out Cyclical Redundancy Check to the signal after forward error correction coding；
The downlink signal process part includes：Second circulation redundancy check module, channel coding module, modulation module and
Inverse fast fourier transform module；
The second circulation redundancy check module carries out Cyclical Redundancy Check for the signal to input；
The channel coding module, for being encoded to the signal after Cyclical Redundancy Check；
The modulation module, for being modulated to the signal after coding；
The inverse fast fourier transform module, for carrying out inverse fast fourier transform to modulated signal.
Optionally, the channel estimation module and the channel equalization module are fixed point matrix-function processor；
Fixed point matrix-the function processor includes：Multilayer multiplication addition and data rearrangement units and functional operation accelerate
Unit；
The multilayer multiplication addition and data rearrangement units include real number, the vectorial addition and subtraction of plural number, vector for carrying out
The basis vector operation of product, dot product, transposition；
The functional operation accelerator module, it is real within the at most default clock cycle for passing through Polynomial Estimation algorithm
Now preset the special function operation of precision；
And/or
The De-mapping module, for carrying out bit-detection fortune to the signal after channel equalization using bit-detection algorithm
It calculates；
And/or
The de-interleaving block uses forward error correction encoding and decoding application specific processor；
And/or
The forward error correction coding module uses forward error correction encoding and decoding application specific processor；
And/or
The first circulation redundancy check module, for using bit processor coordinate register, it is based on look-up table and
The low latency operation of row Cyclical Redundancy Check CRC algorithm to signal after forward error correction coding to carrying out Cyclical Redundancy Check；
And/or
The channel coding module is low overhead simple code and modulation circuit；
And/or
The modulation module is low overhead simple code and modulation circuit.
Optionally, the transmission beam forming chipset includes：M pieces send beam forming chip；
The transmission beam forming chip, for by user wave beam receiving and transmitting signal processing chip group modulation output
Signal carry out beam forming, digital pre-distortion and molding filtration processing successively, and will treated that signal is exported to microminiature
K antenna transmitting terminal of base station.
Optionally, the transmission beam forming chip includes：Input buffer module, second multiply module again, subscriber signal closes
And module, digital pre-distortion block and molding filtration module；
The input buffer module, for the letter by user wave beam receiving and transmitting signal processing chip group modulation output
Number carry out it is temporary handle and export to described second multiply module again；
Described second multiplies module again, and beam forming weighting is sent for being carried out to signal to input buffer module output
Operation；
The subscriber signal merging module, including K the second addition units；
The accumulator that second addition unit is U inputs, singly exports, for being carried out to multiplying module again by described second
The roads U signal after transmission beam forming ranking operation merges；
The digital pre-distortion block, for passing through digital circuit to being merged by the subscriber signal merging module
The transmission power of signal later is pre-compensated for；
The shaping filter module for carrying out pulse shape filter to the signal after precompensation, and pulse shaping is filtered
Signal after wave is exported to the antenna transmitting terminal of microminiature base station, so that the antenna transmitting terminal will be after the pulse shape filter
Signal carry out digital-to-analogue conversion after sent.
Optionally, the shaping filter module is high-speed digital filter.
Optionally, the reception beam forming chipset passes through analog-digital converter and microminiature base using the first difference port
The receiving terminal for the L antenna stood connects, and the transmission beam forming chipset passes through digital analog converter using the first difference port
It is connect with the transmitting terminal of L antenna of microminiature base station；The reception beam forming chipset uses the second difference port and institute
It states aerial signal and merges chipset connection, the transmission beam forming chipset is using the second difference port and the user wave beam
Receiving and transmitting signal processing chip group connects, and the aerial signal is merged chipset and received using the second difference port and the user wave beam
Signalling processing chip group connects；
First difference port and the sampling rate of the analog-digital converter and digital analog converter match, the modulus
Converter uses identical rate, second difference port and intermediate digital signal transmission rate phase with the digital analog converter
Matching, first difference port are different from the rate of second difference port.
As shown from the above technical solution, microminiature base station baseband processor chip set of the invention is applied to 5G channel radios
Believe in microminiature hot spot base station, flexibly configurable, pin, the work(of very large antenna array and the generation of super large calculation amount can be solved
Consumption, area-constrained problem, and pass through the hardware spending of the digital beam shaping structures of fragment optimization minimum.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram for microminiature base station baseband processor chip set that one embodiment of the invention provides；
Fig. 2 is that the structure of the reception beam forming chip in microminiature base station baseband processor chip set shown in FIG. 1 is shown
It is intended to；
Fig. 3 is the user wave beam receiving and transmitting signal processing chip in microminiature base station baseband processor chip set shown in FIG. 1
Ascender structural schematic diagram；
Fig. 4 is the user wave beam receiving and transmitting signal processing chip in microminiature base station baseband processor chip set shown in FIG. 1
Descender structural schematic diagram；
Fig. 5 is that the structure of the transmission beam forming chip in microminiature base station baseband processor chip set shown in FIG. 1 is shown
It is intended to；
Fig. 6 is that a kind of aerial signal in microminiature base station baseband processor chip set shown in FIG. 1 merges chipset
A kind of schematic diagram of connection type.
Specific implementation mode
With reference to the accompanying drawings and examples, the specific implementation mode of the present invention is described in further detail.Implement below
Example is not limited to the scope of the present invention for illustrating the present invention.
Fig. 1 shows the structural schematic diagram for the microminiature base station baseband processor chip set that one embodiment of the invention provides,
As shown in Figure 1, the microminiature base station baseband processor chip set of the present embodiment, including：Receive beam forming chipset 11, antenna
Signal merges chipset 12, user wave beam receiving and transmitting signal processing chip group 13 and sends beam forming chipset 14；
It is described to receive receiving terminal of the beam forming chipset 11 by analog-digital converter 15 and L antenna of microminiature base station
Connection, the reception beam forming chipset 11 merge chipset 12 with the aerial signal and connect, the user wave beam transmitting-receiving
Signal processing chip group 13 merges chipset 12 with the aerial signal, the transmission beam forming chipset 14 is separately connected,
The transmission beam forming chipset 14 is connect by digital analog converter 16 with the transmitting terminal of L antenna of microminiature base station, and L is
Integer more than 1.
In a particular application, beam forming chipset 11 is received described in the present embodiment may include：M reception beam forming
Chip, M are the integer more than 1；
The reception beam forming chip, as shown in Fig. 2, may include：First multiplies module 11a, antenna merging module again
11b and output buffer module 11c；
Described first multiplies module 11a again may include：K groups, every group of U high speed and fixed-point complex multiplication unit, K and U are big
In 1 integer；
The complex multiplication unit, for carrying out beam forming ranking operation from K root antenna received signals；
The antenna merging module 11b may include：U the first addition units；
The accumulator that first addition unit is U inputs, singly exports, for being passed through from K root antenna received signals
The signal for belonging to same receiving area in the signal crossed after the complex multiplication unit carries out beam forming ranking operation carries out
Merge；
The output buffer module 11c is high-speed parallel random access memory ram, for the U the first additions
Signal after unit merges carries out temporary processing, and exports to the aerial signal and merge chipset.
It will be appreciated that it is K that each, which receives the antenna number that beam forming chip is connected, and receive beam forming chip
There is a M, therefore main aerial number L=K × M of base station.
In a particular application, aerial signal merging chipset 12 described in the present embodiment may include：Dual input list exports shape
The mutiple antennas signal of formula arrangement connection merges chip, for closing the output signal for receiving beam forming chipset
And the signal after merging is exported to the user wave beam receiving and transmitting signal processing chip group 13.
Fig. 6 shows that a kind of aerial signal in microminiature base station baseband processor chip set shown in FIG. 1 merges chip
Group a kind of connection type schematic diagram, as shown in fig. 6, Fig. 6 with receive beam forming chip-count be 12 be exemplary in the case of,
Merge chips by amounting to 10 aerial signals to be constituted with the mono- basic connection type interconnection exported of dual input-, including 6 the
One stage signal merges chip, 3 second stage signals merge chip and 1 phase III signal merges chip；These chips
It arranges and connects in the form of inverted triangle, each first stage signal, which merges chip, to receive beam forming chip from two
Signal is further merged；Each second and phase III signal merge chip, respectively to merging the defeated of chip on last stage
Go out signal further to be merged.The signal merged by two or three stages is input into the processing of user wave beam receiving and transmitting signal
In chip, the merging of terminal stage is carried out.By the signal union operation in each stage, pending signal additionally increases by 1 bit
Word length.
In a particular application, user wave beam receiving and transmitting signal processing chip group 13 described in the present embodiment may include：It is N number of mutual
User wave beam receiving and transmitting signal processing chip arranged side by side is used for reception signal of the parallel processing from most U beam shaping zones,
And communicated with macro base station, while the downlink data from macro base station is handled, under most multipair U beamforming transmission region
Row signal is modulated, and modulated signal is exported to the transmission beam forming chipset, N and U are whole more than 1
Number.For example, U can be preferably 10.
Wherein, the user wave beam receiving and transmitting signal processing chip may include：Uplink signal process part and downlink signal
Process part；
The uplink signal process part, as shown in figure 3, may include：Filtering and fast Fourier transform module, channel
Estimation module, channel equalization module, De-mapping module, de-interleaving block, forward error correction coding module and the inspection of first circulation redundancy
Look into module；
The filtering and fast Fourier transform module, it may include：Postpone chain type register group, multidiameter delay filtering at
Manage device and fast fourier transform processor；
The filter processor includes that the two-dimensional parallel multiply-add arithmetic element based on single-instruction multiple-data (is equipped with length
Degree and the optionally multiply-add instruction set of precision), coordinate the delay chain type register group, for (passing through within a clock cycle
Programming) multistage filtering operation is completed, the filter processor, can under configurable delay chain type register group structural support
With by instructing the finite impulse response filtering for realizing various exponent numbers, infinite-duration impulse response filtering, signal autocorrelation and cross-correlation
Scheduling algorithm function；
The fast fourier transform processor includes：Plural butterfly unit, for (instruction set support under) to 2 it is whole
The sequence of power realizes that the low latency Fourier transformation of different lengths, i.e. its data channel use the plural butterfly of high degree of parallelism for several times
Multiply-add structure can complete the parallel base 8 in parallel 4,2 tunnel of base in parallel 2,4 tunnel of base in 8 tunnels and single channel base parallel within a clock cycle
A variety of plural butterfly computations such as 16, can realize the low latency Fast Fourier Transform (FFT) of different lengths by programming；
The channel estimation module, for carrying out channel estimation to the signal after Fourier transformation；
The channel equalization module, for the carry out channel equalization after channel estimation；
The De-mapping module, for carrying out bit-detection operation to the signal after channel equalization, i.e., by theoretic
Simplification of a formula converts based on maximum, minimum value approximate operation the arithmetic operators such as complicated index, logarithm to, and is mapped to
On simple lookup table circuit and numerical value comparison circuit, hardware complexity is largely reduced；
The de-interleaving block, for being deinterleaved to the signal after bit detection calculations；
The forward error correction coding module, for carrying out forward error correction coding to the signal after deinterleaving；
The first circulation redundancy check module, for carrying out Cyclical Redundancy Check to the signal after forward error correction coding.
Further, the channel estimation module and the channel equalization module all can be pinpoint matrix-function processing
Device；
Fixed point matrix-the function processor may include：Multilayer multiplication addition and data rearrangement units and functional operation add
Fast unit；
The multilayer multiplication addition and data rearrangement units include real number, the vectorial addition and subtraction of plural number, vector for carrying out
The basis vector operation of product, dot product, transposition etc.；
The functional operation accelerator module, it is real within the at most default clock cycle for passing through Polynomial Estimation algorithm
Now preset the special function operation of precision.
For example, the default clock cycle is preferably 10 clock cycle, and the default precision is preferably
16 bit accuracies.
Matrix-the function processor divides LU Decomposition used in channel estimation and Channel Equalization Algorithm, QR
It the main operationals such as solves, invert, being pre-allocated and programmed by data, the operation of high efficiency, Lothrus apterus, low latency may be implemented.
In a particular application, the De-mapping module can be used for using bit-detection algorithm to the signal after channel equalization
Carry out bit-detection operation (bit data demapping is carried out to the signal after channel equalization).
For example, it is preferable that the De-mapping module can be used for mapping (Maximum using max log
Logarithm MAP, abbreviation Max-Log-Map) algorithm to after channel equalization signal carry out bit-detection operation.
Preferably, it is special that forward error correction encoding and decoding can be used in the de-interleaving block and the forward error correction coding module
Processor, the forward error correction encoding and decoding application specific processor be preferably high-throughput, low overhead the special place of forward error correction encoding and decoding
Manage device.
Preferably, the first circulation redundancy check module can be based on looking into for coordinating register using bit processor
The low latency operation of cardiopulmonary bypass in beating heart redundancy check (Cyclic Redundancy Check, abbreviation CRC) algorithm of table method to it is preceding to
Cyclical Redundancy Check is carried out to signal after Error Correction of Coding.The first circulation redundancy check module uses parallel logic operational data
Channel, cooperation register file carry out the parallel CRC algorithm based on look-up table, may be implemented to include CRC8, CRC16, CRC24,
The low latency operation of a variety of cyclic redundancy check algorithms such as CRC32.
Wherein, the downlink signal process part, as shown in figure 3, may include：Second circulation redundancy check module, letter
Road coding module, modulation module and inverse fast fourier transform module；
The second circulation redundancy check module carries out Cyclical Redundancy Check for the signal to input；
The channel coding module, for being encoded to the signal after Cyclical Redundancy Check；
The modulation module, for being modulated to the signal after coding；
The inverse fast fourier transform module, for carrying out inverse fast fourier transform to modulated signal.
Preferably, the channel coding module and the modulation module all can be low overhead simple code and modulation electricity
Road.
It will be appreciated that the second circulation redundancy check module of the present embodiment and the first circulation redundancy check mould
Identical processor hardware can be used in block, and the software code run is different；The inverse fast fourier transform module can be used
Above-mentioned fast fourier transform processor runs inverse fast fourier transform in the fast fourier transform processor.
In a particular application, beam forming chipset 14 is sent described in the present embodiment may include：M pieces send beam forming
Chip；
The transmission beam forming chip, for by user wave beam receiving and transmitting signal processing chip group modulation output
Signal carry out beam forming, digital pre-distortion and molding filtration processing successively, and will treated that signal is exported to microminiature
K antenna transmitting terminal of base station.
Further, the transmission beam forming chip, as shown in figure 5, may include：Input buffer module 14a, second
Multiply module 14b, subscriber signal merging module 14c, digital pre-distortion block 14d and molding filtration module 14e again；
The input buffer module 14a, for by user wave beam receiving and transmitting signal processing chip group modulation output
Signal carry out it is temporary handle and export to described second multiply module again；
Described second multiplies module 14b again, for carrying out transmission beam forming to signal to input buffer module output
Ranking operation；
The subscriber signal merging module 14c, including K the second addition units；
The accumulator that second addition unit is U inputs, singly exports, for being carried out to multiplying module again by described second
The roads U signal after transmission beam forming ranking operation merges；
The digital pre-distortion block 14d, for being carried out by digital circuit to passing through the subscriber signal merging module
The transmission power of signal after merging is pre-compensated for；
The shaping filter module 14e, for carrying out pulse shape filter to the signal after precompensation, and by pulse shaping
Filtered signal is exported to the antenna transmitting terminal of microminiature base station, so that the antenna transmitting terminal is by the pulse shape filter
Signal afterwards is sent after carrying out digital-to-analogue conversion.
Preferably, the shaping filter module 14e can be high-speed digital filter.
In a particular application, the high-speed-differential port of two kinds of different rates can be used in the embodiment of the present invention：
The reception beam forming chipset 11 passes through analog-digital converter 15 and microminiature base station using the first difference port
L antenna receiving terminal connection, the first difference port of the transmissions beam forming chipset 14 use passes through digital analog converter
16 connect with the transmitting terminal of L antenna of microminiature base station；The reception beam forming chipset 11 uses the second difference port
Merge chipset 12 with the aerial signal connect, the transmission beam forming chipset 14 the second difference port of use with it is described
User wave beam receiving and transmitting signal processing chip group 13 connects, and the aerial signal merges chipset 12 and uses the second difference port and institute
State the connection of user wave beam receiving and transmitting signal processing chip group 13；First difference port and the analog-digital converter and the digital-to-analogue
The sampling rate of converter 16 matches, and the digital analog converter 16 uses identical rate, institute with the analog-digital converter 15
It states the second difference port with intermediate digital signal transmission rate to match, first difference port and second difference port
Rate it is different.
It should be noted that the first difference port includes the whole input of system, output port, i.e., with 15 phase of analog-digital converter
11 input port of reception beam forming chipset even, and the transmission beam forming chipset 14 that is connected with digital analog converter 16
Output port (digital analog converter 16 uses identical rate with analog-digital converter 15)；Second difference port includes all of system
The transmission port of intermediate digital signal receives the output port of beam forming chipset 11, sends beam forming chipset 14
Input port and the aerial signal merge chipset 12 and the user wave beam receiving and transmitting signal processing chip group 13 institute
Have input, output port (that is, the output end for receiving beam forming chipset 11 merge with aerial signal chipset 12 connection,
Aerial signal merges connection and the user wave beam receiving and transmitting signal of chipset 12 and user wave beam receiving and transmitting signal processing chip group 13
The connection of processing chip group 13 and the input terminal for sending beam forming chipset 14, is all made of the second difference port).Wherein,
The rate of two difference ports is preferably twice of the first difference port speed.
For example, with the microminiature hot spot base station example under a kind of application scenarios of 5G, the configuration of chipset feature is joined
Number and configuration method illustrate.Under the application scenarios, hot spot base station passes through 128 antenna multiple-input and multiple-output (Multi-
Input Multi-output, abbreviation MIMO), provide wideband data for the user in 50 meters of radius in 10 beam areas
Access.For the application scenarios, in order to meet minimum hardware expense, and meet the design constraints such as pin, power consumption and area, to core
Number of chips in piece group structure does following configuration：It receives beam forming chipset and sends chip contained by beam forming chipset
Number M=12, each sends and receivees the reception data on most 11 antennas of beam forming chip processing；Aerial signal merges core
Piece group was divided into for three stages, and each stage has 6,3 and 1 signals to merge chip respectively；User wave beam receiving and transmitting signal handles core
Chip-count N=2 contained by piece group, each user wave beam receiving and transmitting signal processing chip handle separate 5 beam shaping zones
Signal.Under the configuration of such number of chips, according to Software simulation calculation, the digit chip in baseband system can expire simultaneously
Sufficient chip pin number requires (most 1000 pins), area-constrained (45 square millimeters of maximum area chip) and low-power consumption constraint
(3.4 watts of maximum power dissipation chip).The configuration co-used chip quantity is 36, realizes the design of baseband processor hardware spending minimum
Target.
The microminiature base station baseband processor chip set of the present embodiment is applied to 5G wireless communication microminiature hot spots base station
In, main modular in chipset is based on Software Radio Design, can flexible programming, chipset feature flexibly configurable itself,
It is adapted to different antenna numbers, user rate, different frequency range (6 to 40GHz or more) and bandwidth, for each applicable cases, is led to
It crosses configuration and can get minimum hardware cost, very large antenna array can be solved and pin that super large calculation amount generates, power consumption, face
Product restricted problem, and pass through the hardware spending of the digital beam shaping structures of fragment optimization minimum.
One of ordinary skill in the art will appreciate that：Realize that all or part of step of above method embodiment can pass through
Program instruction relevant hardware is completed.Program above-mentioned can be stored in a computer read/write memory medium.The program
When being executed, it includes the steps that above-mentioned each method embodiment to execute；And storage medium above-mentioned includes：ROM, RAM, magnetic disc or
The various media that can store program code such as CD.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, the claim for the present invention that it does not separate the essence of the corresponding technical solution are protected
The range of shield.
Claims (8)
1. a kind of microminiature base station baseband processor chip set, which is characterized in that including：Receive beam forming chipset, antenna
Signal merges chipset, user wave beam receiving and transmitting signal processing chip group and sends beam forming chipset；
The reception beam forming chipset connect by analog-digital converter with the receiving terminal of L antenna of microminiature base station, institute
It states reception beam forming chipset to connect with aerial signal merging chipset, the user wave beam receiving and transmitting signal processing chip
Group merges chipset with the aerial signal, the transmission beam forming chipset is separately connected, the transmission beam forming core
Piece group is connect by digital analog converter with the transmitting terminal of L antenna of microminiature base station, and L is the integer more than 1；
The reception beam forming chipset uses L antenna of the first difference port by analog-digital converter and microminiature base station
Receiving terminal connection, the transmission beam forming chipset passes through digital analog converter and microminiature base station using the first difference port
L antenna transmitting terminal connection；The reception beam forming chipset is closed using the second difference port and the aerial signal
And chipset connects, the transmission beam forming chipset is handled using the second difference port and the user wave beam receiving and transmitting signal
Chipset connects, and the aerial signal merges chipset and handles core using the second difference port and the user wave beam receiving and transmitting signal
Piece group connects；
First difference port and the sampling rate of the analog-digital converter and digital analog converter match, the analog-to-digital conversion
Device uses identical rate, second difference port and intermediate digital signal transmission rate phase with the digital analog converter
Match, first difference port is different from the rate of second difference port.
2. baseband processor chipset according to claim 1, which is characterized in that the reception beam forming chipset packet
It includes：M reception beam forming chip, M are the integer more than 1；
The reception beam forming chip includes：First multiplies module, antenna merging module and output buffer module again；
Described first multiplies module again includes：K groups, every group of U high speed and fixed-point complex multiplication unit, K and U are the integer more than 1；
The complex multiplication unit, for carrying out beam forming ranking operation from K root antenna received signals；
The antenna merging module includes：U the first addition units；
First addition unit is U inputs, the accumulator that singly exports, for from K root antenna received signals by institute
It states and belongs to the signal of same receiving area in the signal after complex multiplication unit carries out beam forming ranking operation and merge；
The output buffer module is high-speed parallel random access memory ram, for merging to the U the first addition units
Signal afterwards carries out temporary processing, and exports to the aerial signal and merge chipset.
3. baseband processor chipset according to claim 1, which is characterized in that the aerial signal merges chipset packet
It includes：The mutiple antennas signal of dual input list output form arrangement connection merges chip, is used for the reception beam forming chip
The output signal of group merges, and the signal after merging is exported to the user wave beam receiving and transmitting signal processing chip group.
4. baseband processor chipset according to claim 1, which is characterized in that the user wave beam receiving and transmitting signal processing
Chipset includes：N number of user wave beam receiving and transmitting signal processing chip being mutually juxtaposed comes from most U wave beams for parallel processing
The reception signal of shaped region, and communicated with macro base station, while the downlink data from macro base station is handled, most multipair U
The downlink signal in beamforming transmission region is modulated, and modulated signal is exported to the transmission beam forming chip
Group, N and U are the integer more than 1.
5. baseband processor chipset according to claim 4, which is characterized in that the user wave beam receiving and transmitting signal processing
Chip includes：Uplink signal process part and downlink signal process part；
The uplink signal process part includes：Filtering and fast Fourier transform module, channel estimation module, channel equalization mould
Block, De-mapping module, de-interleaving block, forward error correction coding module and first circulation redundancy check module；
The filtering and fast Fourier transform module, including：Postpone chain type register group, multidiameter delay filter processor and
Fast fourier transform processor；
The filter processor includes the two-dimensional parallel multiply-add arithmetic element based on single-instruction multiple-data, is prolonged described in cooperation
Slow chain type register group, for completing multistage filtering operation within a clock cycle；
The fast fourier transform processor includes：Plural butterfly unit, the sequence for the integral number power to 2 are realized a variety of
The low latency Fourier transformation of length；
The channel estimation module, for carrying out channel estimation to the signal after Fourier transformation；
The channel equalization module, for the carry out channel equalization after channel estimation；
The De-mapping module, for carrying out bit-detection operation to the signal after channel equalization；
The de-interleaving block, for being deinterleaved to the signal after bit detection calculations；
The forward error correction coding module, for carrying out forward error correction coding to the signal after deinterleaving；
The first circulation redundancy check module, for carrying out Cyclical Redundancy Check to the signal after forward error correction coding；
The downlink signal process part includes：Second circulation redundancy check module, channel coding module, modulation module and inverse fast
Fast fourier transformation module；
The second circulation redundancy check module carries out Cyclical Redundancy Check for the signal to input；
The channel coding module, for being encoded to the signal after Cyclical Redundancy Check；
The modulation module, for being modulated to the signal after coding；
The inverse fast fourier transform module, for carrying out inverse fast fourier transform to modulated signal.
6. baseband processor chipset according to claim 1, which is characterized in that the transmission beam forming chipset packet
It includes：M pieces send beam forming chip；
The transmission beam forming chip, for the letter by user wave beam receiving and transmitting signal processing chip group modulation output
Carry out beam forming, digital pre-distortion and shaping filter processing number successively, and will treated that signal is exported to microminiature base station
K antenna transmitting terminal.
7. baseband processor chipset according to claim 6, which is characterized in that the transmission beam forming chip packet
It includes：Input buffer module, second multiply module, subscriber signal merging module, digital pre-distortion block and shaping filter module again；
The input buffer module, for by the user wave beam receiving and transmitting signal processing chip group modulation output signal into
Row keeps in handle and export to described second multiplies module again；
Described second multiplies module again, and beam forming weighting fortune is sent for being carried out to signal to input buffer module output
It calculates；
The subscriber signal merging module, including K the second addition units；
The accumulator that second addition unit is U inputs, singly exports, for being sent to multiplying module again by described second
The roads U signal after beam forming ranking operation merges；
The digital pre-distortion block, after passing through digital circuit to being merged by the subscriber signal merging module
The transmission power of signal pre-compensated for；
The shaping filter module, for carrying out pulse shape filter to the signal after precompensation, and will be after pulse shape filter
Signal export to the antenna transmitting terminal of microminiature base station so that the antenna transmitting terminal is by the letter after the pulse shape filter
Number carry out digital-to-analogue conversion after sent.
8. baseband processor chipset according to claim 7, which is characterized in that the shaping filter module is high speed number
Word filter.
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| CN1157066A (en) * | 1995-05-24 | 1997-08-13 | 诺基亚电信公司 | Method for transmitting pilot channels, and cellular radio system |
| CN1379558A (en) * | 2001-04-11 | 2002-11-13 | 白桦 | Base station equipment with adaptive array and its transmitting and receiving method |
| WO2004042959A1 (en) * | 2002-11-04 | 2004-05-21 | Vivato Inc | Directed wireless communication |
| CN101065912A (en) * | 2004-07-30 | 2007-10-31 | 香港应用科技研究院有限公司 | Wlan access point with extended coverage area |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1157066A (en) * | 1995-05-24 | 1997-08-13 | 诺基亚电信公司 | Method for transmitting pilot channels, and cellular radio system |
| CN1379558A (en) * | 2001-04-11 | 2002-11-13 | 白桦 | Base station equipment with adaptive array and its transmitting and receiving method |
| WO2004042959A1 (en) * | 2002-11-04 | 2004-05-21 | Vivato Inc | Directed wireless communication |
| CN101065912A (en) * | 2004-07-30 | 2007-10-31 | 香港应用科技研究院有限公司 | Wlan access point with extended coverage area |
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