CN104952707B - The compound hard masks of TiN are used to form the hard of interconnection layer structure and cover and the production method of interconnection layer - Google Patents
The compound hard masks of TiN are used to form the hard of interconnection layer structure and cover and the production method of interconnection layer Download PDFInfo
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Abstract
This application discloses the production methods of a kind of compound hard masks of TiN, the mask and interconnection layer that are used to form interconnection layer structure.The compound hard masks of the TiN include at least one set of mask assembly, and wherein mask assembly includes：First mask layer is arranged close to device surface to be etched；Second mask layer is arranged in side of first mask layer far from device to be etched；Second mask layer is titanium nitride layer, and the hardness of the first mask layer is less than the hardness of the second hard mask layer.By the way that titanium nitride layer to be disposed over, to improve the hardness of the compound hard masks of TiN, and then be conducive to provide protection, while the thickness by reducing TiN in etching process for semiconductor devices, the quantity of TiN fragments when reducing polishing, and then reduce TiN residues.
Description
Technical field
This application involves semiconductor integrated circuit manufacture technology field, in particular to a kind of compound hard masks of TiN,
The production method for being used to form the mask and interconnection layer of interconnection layer structure.
Background technology
In the manufacturing process of semiconductor devices, it will usually form patterned hard mask on a semiconductor substrate, then
Required semiconductor functional areas, such as groove or through-hole etc. are formed along the pattern etching semiconductor substrate of hard mask, are finally removed
Hard mask.Currently, most common hard mask material is TiN.TiN is high because having many advantages, such as compact structure, hardness so that is etching
Etching ion does not pass through TiN in the process, and then can effectively be protected to semiconductor devices, avoid semiconductor devices by
To damage.
Currently, the technique of the removal hard masks of TiN is mainly using chemically mechanical polishing.So-called chemically mechanical polishing is in machinery
On the basis of polishing, chemical addition agent is added on the surface to be polished to achieve the effect that enhancing polishing.To the hard masks of TiN
When carrying out CMP process processing, since TiN hardness is higher, keeps its processing performance poor, be easy to produce on burnishing surface
Raw gap.At the same time, when carrying out CMP process processing to the hard masks of TiN, generated TiN clasts can fill
It can not be polished solution on burnishing surface gap and wash away so that TiN residues are generated on the semiconductor devices of formation,
And then influence the stability of semiconductor devices.
In the manufacturing process of interconnection layer, TiN residues can be equally generated on interconnection layer.The making step packet of interconnection layer
It includes：Oxide mask and the hard masks of TiN are formed on connected medium layer as mask, then etching is through dielectric layer and mask shape
At through-hole, then metal preparation layers are formed in through-holes, finally using the mask and gold on chemically mechanical polishing removal dielectric layer
Belong to preparation layers and forms metal layer.During being chemically-mechanicapolish polished to mask and metal preparation layers, part TiN can be remained
On being formed by interconnection layer, as shown in Figure 1, being shown in FIG. 1 a kind of existing mutual using the hard masks of TiN as mask fabrication
The even SEM photograph of layer, the generated TiN residues in figure this it appears that on the burnishing surface of interconnection layer（In Fig. 1
Shown in a）, the presence of these TiN residues can influence the stability of interconnection layer.
Invention content
The application is intended to provide a kind of compound hard mask of TiN, is used to form the mask of interconnection layer structure and the system of interconnection layer
Make method, to solve the problems, such as easily there are TiN residues in semiconductor devices.
To achieve the goals above, this application provides a kind of compound hard masks of TiN, the compound hard masks of the TiN include extremely
Few one group of mask assembly, wherein mask assembly include：First mask layer is arranged close to device surface to be etched；Second mask layer,
It is arranged in side of first mask layer far from device to be etched；Second mask layer is titanium nitride layer, and the hardness of the first mask layer is low
In the hardness of the second hard mask layer.
Further, in the above-mentioned compound hard masks of TiN, the compound hard masks of the TiN include 2~4 groups of mask assemblies.
Further, in the above-mentioned compound hard masks of TiN, the first mask layer and the second mask layer in each mask assembly
Height is than being 1：0.5~2.
Further, in the above-mentioned compound hard masks of TiN, in difference group mask assembly, the material phase of the first mask layer
Together or differ.
Further, in the above-mentioned compound hard masks of TiN, each first mask layer is containing silicon dielectric layer.
Further, in the above-mentioned compound hard masks of TiN, each first mask layer is selected from SiO2, SiOC, SiON or
SiCN。
Present invention also provides a kind of mask being used to form interconnection layer structure, which includes being set in turn in interconnection to be situated between
The compound hard mask of oxide mask and TiN provided by the present application on matter layer.
Further, in above-mentioned mask, oxide mask is selected from black diamond, SiOC and SiO2Any one of or it is more
Kind.
Further, in above-mentioned mask, oxide mask includes being directed away from connected medium layer direction to set successively
The black diamond and SiO set2。
Further, in above-mentioned mask, mask further includes being arranged in the compound hard masks of TiN far from connected medium layer one
The protective layer of side, preferably protective layer are SiO2。
Present invention also provides a kind of production methods of interconnection layer, including connected medium is sequentially formed on semiconductor substrate
Layer and mask, etching form through-hole through mask and connected medium layer, are filled in through-hole and form metal preparation layers, and removal
Mask and metal preparation layers on connected medium layer form metal layer, wherein forming the application in the step of forming mask
The mask of offer.
Using technical solution provided by the present application, while titanium nitride layer and hardness being used to be less than the another kind of titanium nitride layer
Material layer.By the way that titanium nitride layer to be disposed over, to improve the hardness of the compound hard masks of TiN, and then be conducive to etched
Journey provides protection, while the thickness by reducing TiN for semiconductor devices, the quantity of TiN fragments when reducing polishing, and then reduces
TiN residues.Meanwhile by using the lower material layer of hardness on the surface of device to be etched, improving the compound hard masks of TiN
Processing performance, and then in polishing, reduce on left burnishing surface after the polishing compound hard masks of TiN the quantity in gap and
Area, and then reduce generation TiN residues on semiconductor devices, improve the stability of semiconductor devices.
Description of the drawings
The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 shows the SEM photograph of existing interconnection layer；
Fig. 2 shows the cross-sectional views for the hard mask that the application embodiment is provided；
Fig. 3 shows a kind of cross-section structure for mask being used to form interconnection layer structure that the application embodiment is provided
Schematic diagram；And
Fig. 4 shows that the another kind that the application embodiment is provided is used to form the section knot of the mask of interconnection layer structure
Structure schematic diagram.
Specific implementation mode
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below in conjunction with embodiment.
It should be noted that term used herein above is merely to describe specific implementation mode, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Be also intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or combination thereof.
For ease of description, herein can with use space relative terms, as " ... on ", " in ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, if the device in attached drawing is squeezed, it is described as " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also the positioning of other different modes（It is rotated by 90 ° or is in other orientation）, and
And respective explanations are made to the opposite description in space used herein above.
As described in background technology, there are problems that hard mask residue in the semiconductor device.The application's
Inventor studies regarding to the issue above, provides a kind of compound hard masks of TiN.As shown in Fig. 2, the compound hard masks of the TiN
100 include at least one set of mask assembly 110, and mask assembly 110 includes：First mask layer 111 and the second mask layer 112.First
Mask layer 111 is arranged close to device surface to be etched；Second mask layer 112 is arranged in the first mask layer 111 far to be etched
The side of device, the second mask layer 112 are titanium nitride layer, and the hardness of the first mask layer 111 is hard less than the second hard mask layer 112
Degree.
In the compound hard masks of this TiN provided herein, while using titanium nitride layer and hardness less than nitridation
Another material layer of titanium layer.By the way that titanium nitride layer to be disposed over, to improve the hardness of the compound hard masks of TiN, Jin Eryou
When providing protection, while the thickness by reducing TiN for semiconductor devices conducive in etching process, and then reducing polishing, TiN is broken
The quantity of piece, and then reduce TiN residues.Meanwhile it by using the lower material layer of hardness on the surface of device to be etched, carrying
The high processing performance of the compound hard masks of TiN, and then in polishing reduces left throwing after the polishing compound hard masks of TiN
The quantity and area in gap in smooth surface, and then reduce generation TiN residues on semiconductor devices, improve semiconductor devices
Stability.
The quantity of mask assembly 110 can be one or more groups of, the technology of this field in the above-mentioned compound hard masks 100 of TiN
Personnel can set the quantity of mask assembly 110 according to actual process demand.In a preferred embodiment, the TiN is compound
Hard mask 100 includes 2~4 groups of mask assemblies 110.When the compound hard masks 100 of TiN include 2~4 groups of mask assemblies 110, pass through
It is layered the TiN layer of setting, ensure that the hardness of the compound hard masks of TiN 100, and then is conducive to provide protection for semiconductor devices.
Meanwhile it is identical in the height of the compound hard masks of TiN 100, the group number of mask assembly 110 is more, the height of every layer of TiN
Thinner, in this case, TiN layer is easier to be removed, and when removal TiN layer, generated TiN fragments are more dispersed, are easy to
Removal, and then the TiN residues generated on the semiconductor device are advantageously reduced, improve the stability of semiconductor devices.So
And the increase of the group number with mask assembly 110, preparation process also can be relative complex, in order to simplify preparation process, in the application
In preferably 2~4 groups of mask assemblies 110.
In each mask assembly 110, those skilled in the art equally can set first according to actual process demand and cover
The height ratio of mold layer 111 and the second mask layer 112.In a preferred embodiment, the first mask layer 111 and the second mask layer
112 height ratio is 1：0.5~2.The compound hard masks of TiN 100 are advantageously allowed using the mask assembly 110 of above-mentioned height ratio
Hardness reaches a balance with processing performance, and then while being conducive to provide protection to semiconductor devices, after reducing polishing
The TiN residues generated on semiconductor devices, improve the stability of semiconductor devices.Above-mentioned first mask layer 111 can be
Common siliceous dielectric material in this field.Preferably, the first mask layer 111 is SiO2, SiOC, SiON or SiCN.It needs to note
Meaning, in different groups of mask assemblies 110, the material of the first mask layer 111 can be identical, can not also be identical.
Present invention also provides a kind of the hard of interconnection layer structure that be used to form to cover.As shown in figure 3, the mask includes setting successively
The compound hard mask 100 of oxide mask 200 and TiN being placed on connected medium layer, the compound hard masks 100 of wherein TiN are this
The compound hard masks of the provided TiN of application 100.TiN residues, Jin Erti are not will produce on the interconnection layer formed using the mask
The high stability of interconnection layer.
Above-mentioned oxide mask 200 can be the common oxide mask material in this field.Preferably, oxide mask
200 are selected from black diamond, SiOC and SiO2Any one or more of.Oxide mask 200 can be one or more layers, work as oxidation
When object mask 200 is multilayer, in a kind of preferred embodiment, oxide mask 200 includes far from connected medium layer direction
The black diamond and SiO set gradually2.It should be noted that as shown in figure 4, the mask can also include that setting is compound hard in TiN
The protective layer 300 of the separate connected medium layer side of mask 100, the protective layer 300 are preferably SiO2。
Meanwhile present invention also provides a kind of production methods of interconnection layer, including sequentially formed mutually on semiconductor substrate
Even dielectric layer and mask, etching form through-hole through mask and connected medium layer, are filled in through-hole and form metal preparation layers, with
And metal layer is formed positioned at the mask and metal preparation layers removed on connected medium layer, wherein mask is provided herein
Mask.TiN residues are not will produce on the interconnection layer formed using the production method, and then improve the stability of interconnection layer.
The material of above-mentioned semiconductor substrate can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carbonization SiC),
Can also be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other materials, such as 6 GaAs etc.
III-V compound.A kind of structure, such as transistor, diode, capacitor, shallow ridges are at least formed on above-mentioned semiconductor substrate
Slot structure or interconnection layer etc..Above-mentioned connected medium layer can be Low-K materials, such as SiO2Or SiCOH, form connected medium layer
Technique can be chemical vapor deposition, sputtering etc..
Above-mentioned mask includes oxide mask 200 and the compound hard masks of TiN 100.Wherein oxide mask 200 can be this
The common oxide mask material in field, preferably black diamond, SiOC and SiO2Any one or more of forms oxide and covers
The technique of film 200 can be chemical vapor deposition, sputtering or thermal oxide etc..The compound hard masks 100 of TiN are provided herein
The compound hard masks 100 of TiN, including the first mask layer 111 and the second mask layer 112 that are stacked, wherein the second mask layer is
Titanium nitride layer, the first mask layer 111 can be the common siliceous dielectric material in this field, preferably SiO2, SiOC, SiON or
SiCN。
It can be chemical vapor deposition, sputtering etc. to form above-mentioned first mask layer 111 and titanium nitride technique.When using chemistry
Vapor deposition is when forming TiN, in a kind of optional scheme, with TiCl4And NH3For reaction gas, TiCl4Flow be 300~
500sccm, NH3Flow be 150~250sccm, react indoor pressure be 5~10torr, depositing temperature be 500~650
DEG C, sedimentation time is 20~90 seconds.
The technique for etching above-mentioned mask and connected medium layer is dry etching.In a kind of optional scheme, dry etching
Process conditions are：Etching gas is CF4And CHF3, sputtering power is 400~1000 watts, and etching temperature is 25~60 DEG C, when etching
Between be 30~360 seconds.
Above-mentioned metal preparation layers can be metal material commonly used in the prior art, such as Cu, Au or Sn, preferably Cu,
The technique for forming above-mentioned metal preparation layers includes but not limited to using plating or chemical vapor deposition.It is formed when using electroplating technology
When Cu, a kind of optional embodiment is：With Cu2P2O7For the sources Cu in electroplate liquid, the current density in electroplating process is 1~5A/
dm2, the temperature of electroplate liquid is 5~80 DEG C.
The technique for removing mask and metal preparation layers on connected medium layer is chemically mechanical polishing.Chemically mechanical polishing
The Si0 that used polishing fluid can be well known to those skilled in the art2Polishing fluid, such as can be the various of market sale
The polishing fluid of model.In a kind of optional scheme, the process conditions of chemically mechanical polishing are：The pressure applied on grinding head is
200~300g/cm2, the rotating speed of grinding head is 50~100r/min, 100~300ml/min of flow velocity of polishing fluid, polish temperature
It it is 20~45 DEG C, polishing time is 20~120 seconds.
The production method that the application provides interconnection layer is further illustrated with reference to embodiment.However, these exemplary realities
The mode of applying can be implemented there are many different forms, and should not be construed to be limited solely to embodiment party set forth herein
Formula.It should be understood that thesing embodiments are provided so that disclosure herein is thoroughly and complete, and these are shown
The design of example property embodiment is fully conveyed to those of ordinary skill in the art.
Embodiment 1
A kind of production method of interconnection layer is present embodiments provided, is included the following steps：
SiO is sequentially formed on a si substrate2Dielectric layer, SiOC mask layers and by one group of SiO2The TiN of/TiN compositions is compound
Hard mask, wherein SiO in the compound hard masks of TiN2Height be 150The height of TiN is 150Form the reaction condition of TiN
For：With TiCl4And NH3For reaction gas, TiCl4Flow be 400sccm, NH3Flow be 300sccm, react indoor pressure
It is 5torr by force, depositing temperature is 500 DEG C, and sedimentation time is 60 seconds；
Etch the compound hard masks of TiN, SiOC mask layers and SiO2Dielectric layer forms through-hole, wherein the process conditions etched
For：Etching gas is CF4And CHF3, sputtering power is 1000 watts, and etching temperature is 60 DEG C, and etch period is 70 seconds；
Form Cu preparation layers in through-holes by electroplating technology, wherein electroplating technique condition is：With Cu2P2O7For plating
The sources Cu in liquid, the current density in electroplating process are 3A/dm2, the temperature of electroplate liquid is 65 DEG C；
SiO is removed using chemically mechanical polishing2The compound hard masks of TiN, SiOC mask layers and Cu preparation layers on dielectric layer,
With in SiO2Cu layers are formed in dielectric layer, wherein the process conditions chemically-mechanicapolish polished are：The pressure applied on grinding head is
220g/cm2, the rotating speed of grinding head is 85r/min, and the flow velocity 260ml/min of polishing fluid, polish temperature is 35 DEG C, polishing time
It is 35 seconds.
Embodiment 2
A kind of production method of interconnection layer is present embodiments provided, is included the following steps：
SiO is sequentially formed on a si substrate2Dielectric layer, SiOC mask layers and the TiN that is made of 2 groups of SiON/TiN are compound
Hard mask, wherein the height 40 of SiON in every group of SiON/TiNThe height 80 of TiNThe reaction condition for forming every group of TiN is：
With TiCl4And NH3For reaction gas, TiCl4Flow be 400sccm, NH3Flow be 300sccm, react indoor pressure
For 5torr, depositing temperature is 500 DEG C, and sedimentation time is 30 seconds；
Etch the compound hard masks of TiN, SiOC mask layers and SiO2Dielectric layer forms through-hole, in through-holes by electroplating technology
Cu preparation layers are formed, and using chemically mechanical polishing removal SiO2The compound hard masks of TiN, SiOC mask layers on dielectric layer and
The step of Cu preparation layers, is same as Example 1.
Embodiment 3
A kind of production method of interconnection layer is present embodiments provided, is included the following steps：
SiO is sequentially formed on a si substrate2Dielectric layer, SiOC mask layers and the TiN that is made of 2 groups of SiOC/TiN are compound
Hard mask, wherein the height 40 of SiOC in every group of SiOC/TiNThe height 80 of TiNThe reaction condition for forming every group of TiN is：
With TiCl4And NH3For reaction gas, TiCl4Flow be 400sccm, NH3Flow be 300sccm, react indoor pressure
For 5torr, depositing temperature is 500 DEG C, and sedimentation time is 30 seconds；
Etch the compound hard masks of TiN, SiOC mask layers and SiO2Dielectric layer forms through-hole, in through-holes by electroplating technology
Cu preparation layers are formed, and using chemically mechanical polishing removal SiO2The compound hard masks of TiN, SiOC mask layers on dielectric layer and
The step of Cu preparation layers, is same as Example 1.
Embodiment 4
A kind of production method of interconnection layer is present embodiments provided, is included the following steps：It sequentially forms on a si substrate
SiO2Dielectric layer, SiOC mask layers and the compound hard masks of TiN being made of 4 groups of SiCN/TiN, wherein in every group of SiCN/TiN
The height 60 of SiCNThe height 30 of TiNThe reaction condition for forming every group of TiN is：With TiCl4And NH3For reaction gas, TiCl4
Flow be 400sccm, NH3Flow be 300sccm, react indoor pressure be 5torr, depositing temperature be 500 DEG C, deposition
Time is 15 seconds；
Etch the compound hard masks of TiN, SiOC mask layers and SiO2Dielectric layer forms through-hole, in through-holes by electroplating technology
Cu preparation layers are formed, and using chemically mechanical polishing removal SiO2The compound hard masks of TiN, SiOC mask layers on dielectric layer and
The step of Cu preparation layers, is same as Example 1.
Comparative example 1
This comparative example provides a kind of production method of interconnection layer, includes the following steps：
SiO is sequentially formed on a si substrate2Dielectric layer, SiOC mask layers and 300The hard masks of TiN, wherein forming TiN
Reaction condition be：With TiCl4And NH3For reaction gas, TiCl4Flow be 400sccm, NH3Flow be 300sccm, instead
It is 5torr to answer indoor pressure, and depositing temperature is 500 DEG C, and sedimentation time is 100 seconds；
Etch hard mask, SiOC mask layers and SiO2Dielectric layer forms through-hole, and Cu is formed in through-holes by electroplating technology
Preparation layers, and using chemically mechanical polishing removal SiO2On dielectric layer the step of hard mask, SiOC mask layers and Cu preparation layers
It is same as Example 1.
Test：By the leakage current in 1 obtained interconnection layer of testing example 1 to 4 and comparative example, to characterize interconnection layer
Isolation effect and reliability.Test method is：Apply test voltage on interconnection layer, test voltage increases every time from 0V to 30V
Add 1V；The leakage current between interconnection layer is measured simultaneously, and is averaged.Test result is see table 1.
Table 1.
| Leakage current（Average value/A） | |
| Embodiment 1 | 3.5×10-9 |
| Embodiment 2 | 3.2×10-9 |
| Embodiment 3 | 3.3×10-9 |
| Embodiment 4 | 2.7×10-9 |
| Comparative example 1 | 7.8×10-8 |
As it can be seen from table 1 the leakage current for the interconnection layer that embodiment 1 to 4 obtains is 2.7 × 10-9~3.5 × 10-9It
Between, and the leakage current for the interconnection layer that comparative example 1 obtains is 7.8 × 10-8A.As it can be seen that the stabilization for the interconnection layer that embodiment 1 to 4 obtains
Property is apparently higher than the stability for the interconnection layer that comparative example 1 obtains.
It can be seen from the above description that the application the above embodiments realize following technique effect：The application is same
When used titanium nitride layer and hardness less than another material layer of titanium nitride layer as compound hard mask.By by titanium nitride layer
It is disposed over, to improve the hardness of the compound hard masks of TiN, and then is conducive to provide guarantor in etching process for semiconductor devices
Shield, while the thickness by reducing TiN, the quantity of TiN fragments when reducing polishing, and then reduce TiN residues.Meanwhile passing through
The lower material layer of hardness is used on the surface of device to be etched, improves the processing performance of the compound hard masks of TiN, and then throwing
Light time, reduce the quantity and area in gap on burnishing surface left after polishing the compound hard masks of TiN, and then reduces and partly lead
The TiN residues generated on body device, improve the stability of semiconductor devices.
The foregoing is merely the preferred embodiments of the application, are not intended to limit this application, for the skill of this field
For art personnel, the application can have various modifications and variations.Within the spirit and principles of this application, any made by repair
Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (1)
1. a kind of production method of interconnection layer, which is characterized in that the production method includes the following steps：
SiO is sequentially formed on a si substrate2Dielectric layer, SiOC mask layers and the TiN that is made of 4 groups of SiCN/TiN is compound covers firmly
Film, wherein in each group SiCN/TiN, the height of the SiCNThe height of the TiNForm the reaction item of the TiN
Part is：With TiCl4And NH3For reaction gas, TiCl4Flow be 400sccm, NH3Flow be 300sccm, reaction it is indoor
Pressure is 5torr, and depositing temperature is 500 DEG C, and sedimentation time is 15 seconds；
Etch the compound hard masks of the TiN, the SiOC mask layers and the SiO2Dielectric layer forms through-hole, passes through electroplating technology
Cu preparation layers are formed in through-holes, and using chemically mechanical polishing removal SiO2Compound hard masks of the TiN on dielectric layer,
The step of SiOC mask layers and the Cu preparation layers；The process conditions of chemically mechanical polishing are：The pressure applied on grinding head
Power is 220g/cm2, the rotating speed of grinding head is 85r/min, and the flow velocity 260mL/min of polishing fluid, polish temperature is 35 DEG C, polishing
Time is 35 seconds.
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| CN201410127662.5A CN104952707B (en) | 2014-03-31 | 2014-03-31 | The compound hard masks of TiN are used to form the hard of interconnection layer structure and cover and the production method of interconnection layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779780A (en) * | 2012-07-25 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming non-load-effect large size groove |
| CN103377886A (en) * | 2012-04-13 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Hard mask layer structure, manufacturing method thereof and manufacturing method of semiconductor device |
| CN103489822A (en) * | 2012-06-11 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103515228A (en) * | 2012-06-18 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377886A (en) * | 2012-04-13 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Hard mask layer structure, manufacturing method thereof and manufacturing method of semiconductor device |
| CN103489822A (en) * | 2012-06-11 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103515228A (en) * | 2012-06-18 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN102779780A (en) * | 2012-07-25 | 2012-11-14 | 上海华力微电子有限公司 | Method for forming non-load-effect large size groove |
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