CN104733535A - Power MOSFET - Google Patents
Power MOSFET Download PDFInfo
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- CN104733535A CN104733535A CN201510115551.7A CN201510115551A CN104733535A CN 104733535 A CN104733535 A CN 104733535A CN 201510115551 A CN201510115551 A CN 201510115551A CN 104733535 A CN104733535 A CN 104733535A
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- epitaxial loayer
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- floating electrode
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- 238000007667 floating Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 16
- 230000005684 electric field Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a power MOSFET. The power MOSFET comprises a substrate, an epitaxial layer, source doping zones, well zones, polycrystal source electrodes, multiple floating electrodes, a capacitance dielectric layer and a side wall dielectric layer, wherein the epitaxial layer covers the substrate; the source doping zones are located in the epitaxial layer; the well zones are located in the epitaxial layer and below the source doping zones; the polycrystal source electrodes are surrounded by the epitaxial layer and located below the surface of a chip; the floating electrodes are surrounded by the epitaxial layer and located below the polycrystal source electrodes; the capacitance dielectric layer is located among the floating electrodes, between the floating electrodes and the polycrystal source electrodes and between the floating electrodes which are located the lowermost positions and the epitaxial layer; the side wall dielectric layer is located between the epitaxial layer and the polycrystal source electrodes and between the epitaxial layer and the floating electrodes. The power MOSFET has both the advantages of a CC-MOSFET and the advantages of an SJ-MOSFET.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of power MOSFET.
Background technology
In power semiconductor field, the longitudinal metal-MOSFET (being called for short MOSFET) formed with vertical double diffusion technique is called VDMOSFET, is called for short VDMOS.Because it has the features such as switching speed is fast, input impedance is high, frequency characteristic is good, be widely used.For traditional VDMOS, the mode generally by increasing epitaxy layer thickness and reduction outer layer doping concentration improves puncture voltage.But along with the increase of puncture voltage, this mode can make epilayer resistance improve significantly, research shows to there is a limit between conducting resistance and puncture voltage---be referred to as " silicon limit ", conducting resistance cannot be reduced again.A lot of device layout method breaches this limit, if insulated gate bipolar transistor (being called for short IGBT) device reduces on state resistance by injecting few sub method in epitaxial loayer.And the principle of the charge balance that another kind of technology utilizes, by introducing transverse electric field in epitaxial loayer, make the distribution of longitudinal electric field be converted into trapezoidal profile by triangle, the dependence that weakens puncture voltage and doping content reduces conducting resistance.Conventional at present the two kinds technology introducing transverse electric field comprise charge balance isolated-gate field effect transistor (IGFET) (being called for short CC-MOSFET) and superjunction field-effect transistor (being called for short SJ-MOSFET).
CC-MOSFET is proposed in nineteen ninety-five by B.Jayant Baliga, by adding the source electrode field plate or grid field plate that run through whole drift region in epitaxial loayer, when making device be in blocking state, in space charge region, electric charge is all balanced by this field plate, thus realizes object longitudinal electric field being converted into trapezoidal profile.Because this structure well can merge with groove grid technique, therefore, this device architecture is widely used in the middle of the design of mesolow power groove isolated-gate field effect transistor (IGFET) (being called for short Trench MOSFET).
But because the field plate running through drift region is generally source electrode or gate electrode, this structure is used for there are 2 obvious defects in high voltage structures design.This is because the change of drift region built-in potential along with lengthwise position changes.This causes the electrical potential difference in different longitudinal position between drift region and field plate to be all change on the one hand, very difficult realization charge balance completely, increasing this imbalance and will make longitudinal electric field substantial deviation trapezoidal profile along with puncture voltage, makes this structure to the improvement of conducting resistance and not obvious.On the other hand, field plate bears whole source-drain voltage near drain electrode place dielectric layer, and for ensureing that this dielectric layer can not puncture in advance, the raising along with device electric breakdown strength is become more and more thicker by its thickness.It is very large that this can cause its cellular density cannot do as low-voltage device, can affect the reduction of conducting resistance equally.
SJ-MOSFET is that the PN by replacing in drift region realizes charge balance, when device is in blocking state, and P district and N district electric charge complete equipilibrium, thus realize the object that longitudinal electric field is converted into trapezoidal profile.Along with the change of lengthwise position, the electrical potential difference in P district and N interval is basicly stable, and therefore SJ-MOSFET does not exist the phenomenon along with puncture voltage raising cellular width increases in theory.
But SJ-MOSFET is made by the mode of repeatedly extension or cutting backfill, and more high technology difficulty is larger for its depth-to-width ratio, this restrict the reduction of cellular density, affects the further improvement of conducting resistance.
Therefore, need one to reduce conducting resistance, the power MOSFET of the shortcoming of above-mentioned CC-MOSFET and SJ-MOSFET can be overcome again.
Summary of the invention
The present invention is intended to solve above-described problem.The object of this invention is to provide a kind of power MOSFET, it has had the advantage of CC-MOSFET and SJ-MOSFET concurrently.
According to an aspect of the present invention, provide a kind of power MOSFET, described power MOSFET comprises:
Substrate;
Epitaxial loayer, described epitaxial loayer covers described substrate;
Source dopant region, described source dopant region is positioned at described epitaxial loayer;
Well region, described well region is positioned at described epitaxial loayer and is positioned at below described source dopant region;
Polycrystalline source electrode, described polycrystalline source electrode is surrounded by described epitaxial loayer and is positioned at below chip surface;
Multiple floating electrode, described floating electrode is surrounded by described epitaxial loayer and is positioned at below described polycrystalline source electrode;
Capacitor dielectric layer, described capacitor dielectric layer between described floating electrode, between described floating electrode and described polycrystalline source electrode, and between the described floating electrode and described epitaxial loayer of bottom; And
Side wall medium layer, described side wall medium layer between described epitaxial loayer and described polycrystalline source electrode, and between described epitaxial loayer and described floating electrode.
Wherein, the length of described floating electrode is 0.5um ~ 8um, and width is 0.5um ~ 2um.
Wherein, the number of described floating electrode is 1-20.
Wherein, the length of multiple described floating electrode is identical.
Wherein, the thickness of described capacitor dielectric layer is 10nm ~ 500nm, and the material of described capacitor dielectric layer is SiO
2or Si
3n
4.
Wherein, the thickness of described side wall medium layer is 100nm ~ 800nm, and the material of described side wall medium layer is SiO
2or Si
3n
4.
Wherein, described power MOSFET also comprises:
Through described source dopant region, and go deep into the source contact hole of described well region inside;
Surrounded by described epitaxial loayer, be positioned at the polycrystalline grid below described chip surface, above described polycrystalline source electrode;
Gate oxide between described epitaxial loayer and described polycrystalline grid;
Spacer medium layer between described polycrystalline grid and described polycrystalline source electrode;
Be positioned at the surface oxide layer above described polycrystalline grid and described source dopant region;
Be positioned at the metal source of described chip surface; And
Be positioned at the metal leakage pole below described substrate.
The power MOSFET with multilayer floating structure of the present invention passes through in epitaxial loayer drift region, multiple floating electrode, capacitor dielectric layer and side wall medium layer is added below polycrystalline source electrode, thus form a series of electric capacity be connected between source electrode and drain electrode, to realize the charge balance under blocking state.In addition, power MOSFET of the present invention only need increase the thickness of epitaxial loayer and the number of floating electrode, overcomes the shortcoming that CC-MOSFET designs high voltage structures.Meanwhile, power MOSFET of the present invention is changed few to the manufacturing process of existing CC-MOSFET, can with traditional Trench MOSFET process compatible.Therefore, power MOSFET provided by the invention has had the advantage of CC-MOSFET and SJ-MOSFET concurrently.
Read the following description for exemplary embodiment with reference to accompanying drawing, other features and advantages of the present invention will become clear.
Accompanying drawing explanation
To be incorporated in specification and the accompanying drawing forming a part for specification shows embodiments of the invention, and together with the description for explaining principle of the present invention.In the drawings, similar Reference numeral is used for key element like representation class.Accompanying drawing in the following describes is some embodiments of the present invention, instead of whole embodiment.For those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can be obtained according to these accompanying drawings.
Fig. 1 schematically illustrates the structural representation according to power MOSFET of the present invention;
Fig. 2 schematically illustrates the equivalent model according to power MOSFET of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combination in any mutually.
Rotating fields schematic diagram according to the embodiment of the present invention shown in the drawings.These figure not draw in proportion, wherein for purposes of clarity, are exaggerated some details, and may eliminate some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, in reality may due to manufacturing tolerance or technical limitations deviation to some extent, and those skilled in the art can design the regions/layers with difformity, size, relative position in addition needed for actual.
The power MOSFET that the present invention proposes is by epitaxial loayer drift region, multiple floating electrode, capacitor dielectric layer and side wall medium layer is added below polycrystalline source electrode, thus form a series of electric capacity be connected between source electrode and drain electrode, to realize the charge balance under blocking state.This power MOSFET comprises: substrate; Cover the epitaxial loayer of substrate; Be positioned at the source dopant region of epitaxial loayer; Be positioned at epitaxial loayer and be positioned at the well region below source dopant region; Surrounded by epitaxial loayer and be positioned at the polycrystalline source electrode below chip surface; Surrounded by epitaxial loayer and be positioned at the floating electrode below polycrystalline source electrode; Between floating electrode, between floating electrode and polycrystalline source electrode, and the capacitor dielectric layer between the floating electrode and epitaxial loayer of bottom; And the side wall medium layer between epitaxial loayer and polycrystalline source electrode, between epitaxial loayer and floating electrode.
Describe in detail with reference to the accompanying drawings according to power MOSFET of the present invention.
Fig. 1 shows the structural representation according to power MOSFET of the present invention.As shown in Figure 1, this power MOSFET comprises substrate 101; Cover the epitaxial loayer 102 of substrate 101; Be positioned at the source dopant region 104 of epitaxial loayer 102; Be positioned at epitaxial loayer 102 and be positioned at the well region 103 below source dopant region 104; Surrounded by epitaxial loayer 102 and be positioned at the polycrystalline source electrode 112 below chip surface; Surrounded by epitaxial loayer 102 and be positioned at the floating electrode 115 below polycrystalline source electrode 112; Between floating electrode 115, between floating electrode 115 and polycrystalline source electrode 112, and the capacitor dielectric layer 108 between the floating electrode 115 and epitaxial loayer 102 of bottom; And the side wall medium layer 106 between epitaxial loayer 102 and polycrystalline source electrode 112, between epitaxial loayer 102 and floating electrode 115.
Wherein substrate 101 is the first conduction type, and epitaxial loayer 102 is the first conduction type, and source dopant region 104 is the first conduction type, and well region 103 is the second conduction type, and polycrystalline source electrode 112 is the first conduction type.Floating electrode 115 is generally the first conduction type of polycrystalline, but exists for the possibility of the second conduction type, even exists for the possibility of metal electrode.
Multiple floating electrode 115 is formed in epitaxial loayer 102, below polycrystalline source electrode 112; Between the floating electrode 115 and the polycrystalline source electrode 112 above it of the top, between adjacent floating electrode 115 and between the floating electrode 115 of bottom and the epitaxial loayer 102 below it, all form capacitor dielectric layer 108; And between epitaxial loayer 102 and polycrystalline source electrode 112, between epitaxial loayer 102 and each floating electrode 115, all form side wall medium layer 106.These floating electrodes 115, capacitor dielectric layer 108 and side wall medium layer 106 constitute a series of series connection electric capacity between the source and drain.By the dividing potential drop effect of these electric capacity, define the field plate that electromotive force changes with lengthwise position.When device is in blocking state, in different longitudinal position, the electrical potential difference between drift region and field plate is uniform substantially, thus realizes charge balance completely.
The length of floating electrode 115 is generally 0.5um ~ 8um, and width is relevant with technological level, is generally 0.5um ~ 2um.The length of multiple floating electrode 115 can identical also can not be identical, the example that the length being each floating electrode 115 provided in Fig. 1 is identical.When the length of each floating electrode 115 is not identical, its length also can be gradual change.When the length of floating electrode 115 is not identical, in order to realize charge balance, power MOSFET just can be allowed to have certain process allowance during fabrication.The length of each floating electrode 115 can be designed according to design needs and process conditions.In addition, the number of the floating electrode 115 of formation is relevant with the puncture voltage of device, is generally 1 ~ 20.The number of the floating electrode 115 formed is more, and the puncture voltage of device is higher.
Capacitor dielectric layer 108 can be SiO
2or Si
3n
4form Deng multiple material, its thickness is 10nm ~ 500nm.Side wall medium layer 106 can be SiO
2or Si
3n
4form Deng multiple material, thickness is 100nm ~ 800nm.According to the thickness of capacitor dielectric layer 108 and the thickness of side wall medium layer 106, the electric capacity of the side wall medium layer 106 of formation is less than the electric capacity of capacitor dielectric layer 108.
Shown in Fig. 1, this power MOSFET can also comprise: go deep into the source contact hole 109 of well region 103 inside through source dopant region 104; Surrounded by epitaxial loayer 102, be positioned at below chip surface, polycrystalline grid 113 above polycrystalline source electrode 112; Gate oxide 105 between epitaxial loayer 102 and polycrystalline grid 113; Spacer medium layer 107 between polycrystalline grid 113 and polycrystalline source electrode 112; Be positioned at the surface oxide layer 110 above polycrystalline grid 113 and source dopant region 104; Be positioned at the metal source 111 of chip surface; And the metal leakage pole 114 be positioned at below substrate 101.
Fig. 2 is the equivalent model according to power MOSFET of the present invention.Illustrate that this power MOSFET realizes the principle of the charge balance under blocking state by Fig. 2.In fig. 2, be what to comprise the consistent floating electrode 115 of 5 length be example.Wherein, suppose that the electric capacity of capacitor dielectric layer 108 is C
1, the electric capacity of side wall medium layer 106 is C
2.As electric capacity C
1much larger than electric capacity C
2time, charge balance completely can be realized.When device bears higher reverse voltage, in Fig. 2, the electromotive force of 5 floating electrodes 115 is respectively: V
d/ 6, V
d/ 3, V
d/ 2,2V
d/ 3,5V
d/ 6.These floating electrodes 115 are by electric capacity C
2coupling, the epitaxial loayer of the different depth of their correspondences is exhausted completely, is longitudinally defining trapezoidal Electric Field Distribution, thus achieving the object reducing conducting resistance.
When design has the device of higher puncture voltage, structure and the SJ-MOSFET of power MOSFET of the present invention are similar, only need increase the thickness of epitaxial loayer and the number of floating electrode, overcome the shortcoming that CC-MOSFET designs high voltage structures.Meanwhile, power MOSFET of the present invention is changed few to the manufacturing process of existing CC-MOSFET, can with traditional Trench MOSFET process compatible.Therefore, power MOSFET provided by the invention has had the advantage of CC-MOSFET and SJ-MOSFET concurrently.
Above-described content can combine enforcement individually or in every way, and these variant are all within protection scope of the present invention.
It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, by statement " comprising one ... " the key element limited, and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
In the above description, the ins and outs such as composition, etching for each layer are not described in detail.But it will be appreciated by those skilled in the art that and by various means of the prior art, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.With reference to embodiments of the invention, explanation is given to the present invention above.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the invention.Scope of the present invention is by claims and equivalents thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (7)
1. a power MOSFET, is characterized in that, described power MOSFET comprises:
Substrate (101);
Epitaxial loayer (102), described epitaxial loayer (102) covers described substrate (101);
Source dopant region (104), described source dopant region (104) are positioned at described epitaxial loayer (102);
Well region (103), described well region (103) is positioned at described epitaxial loayer (102) and is positioned at below, described source dopant region (104);
Polycrystalline source electrode (112), described polycrystalline source electrode (112) is surrounded by described epitaxial loayer (102) and is positioned at below chip surface;
Multiple floating electrode (115), described floating electrode (115) is surrounded by described epitaxial loayer (102) and is positioned at described polycrystalline source electrode (112) below;
Capacitor dielectric layer (108), described capacitor dielectric layer (108) is positioned between described floating electrode (115), between described floating electrode (115) and described polycrystalline source electrode (112), and be positioned between the described floating electrode (115) of bottom and described epitaxial loayer (102); And
Side wall medium layer (106), described side wall medium layer (106) is positioned between described epitaxial loayer (102) and described polycrystalline source electrode (112), and between described epitaxial loayer (102) and described floating electrode (115).
2. power MOSFET as claimed in claim 1, it is characterized in that, the length of described floating electrode (115) is 0.5um ~ 8um, and width is 0.5um ~ 2um.
3. power MOSFET as claimed in claim 1, it is characterized in that, the number of described floating electrode (115) is 1-20.
4. power MOSFET as claimed in claim 1, it is characterized in that, the length of multiple described floating electrode (115) is identical.
5. power MOSFET as claimed in claim 1, it is characterized in that, the thickness of described capacitor dielectric layer (108) is 10nm ~ 500nm, and the material of described capacitor dielectric layer (108) is SiO
2or Si
3n
4.
6. power MOSFET as claimed in claim 1, it is characterized in that, the thickness of described side wall medium layer (106) is 100nm ~ 800nm, and the material of described side wall medium layer (106) is SiO
2or Si
3n
4.
7. power MOSFET as claimed in claim 1, it is characterized in that, described power MOSFET also comprises:
Through described source dopant region (104), and go deep into the inner source contact hole (109) of described well region (103);
By described epitaxial loayer (102) surround, be positioned at below described chip surface, described polycrystalline source electrode (112) top polycrystalline grid (113);
Be positioned at the gate oxide (105) between described epitaxial loayer (102) and described polycrystalline grid (113);
Be positioned at the spacer medium layer (107) between described polycrystalline grid (113) and described polycrystalline source electrode (112);
Be positioned at the surface oxide layer (110) of described polycrystalline grid (113) and described source dopant region (104) top;
Be positioned at the metal source (111) of described chip surface; And
Be positioned at the metal leakage pole (114) below described substrate (101).
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|---|---|---|---|
| CN201510115551.7A CN104733535A (en) | 2015-03-17 | 2015-03-17 | Power MOSFET |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510115551.7A CN104733535A (en) | 2015-03-17 | 2015-03-17 | Power MOSFET |
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|---|---|
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ID=53457241
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001018869A2 (en) * | 1999-09-09 | 2001-03-15 | Infineon Technologies Ag | Semiconductor element for high blocking voltages during a simultaneously low closing resistance and method for the production thereof |
| CN101180737A (en) * | 2003-12-30 | 2008-05-14 | 飞兆半导体公司 | Power semiconductor devices and methods of manufacture |
| CN101632151A (en) * | 2007-01-22 | 2010-01-20 | 万国半导体股份有限公司 | Configuration of high-voltage semiconductor power device to achieve three dimensionalcharge coupling |
| US20100314659A1 (en) * | 2009-06-12 | 2010-12-16 | Alpha & Omega Semiconductor, Inc. | Nanotube Semiconductor Devices |
| JP2010541289A (en) * | 2007-10-05 | 2010-12-24 | ビシェイ−シリコニクス | Charge balance in MOSFET active and termination regions |
| CN102479806A (en) * | 2010-11-22 | 2012-05-30 | 上海华虹Nec电子有限公司 | Super junction semiconductor device and manufacturing method thereof |
-
2015
- 2015-03-17 CN CN201510115551.7A patent/CN104733535A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001018869A2 (en) * | 1999-09-09 | 2001-03-15 | Infineon Technologies Ag | Semiconductor element for high blocking voltages during a simultaneously low closing resistance and method for the production thereof |
| CN101180737A (en) * | 2003-12-30 | 2008-05-14 | 飞兆半导体公司 | Power semiconductor devices and methods of manufacture |
| CN101632151A (en) * | 2007-01-22 | 2010-01-20 | 万国半导体股份有限公司 | Configuration of high-voltage semiconductor power device to achieve three dimensionalcharge coupling |
| JP2010541289A (en) * | 2007-10-05 | 2010-12-24 | ビシェイ−シリコニクス | Charge balance in MOSFET active and termination regions |
| US20100314659A1 (en) * | 2009-06-12 | 2010-12-16 | Alpha & Omega Semiconductor, Inc. | Nanotube Semiconductor Devices |
| CN102479806A (en) * | 2010-11-22 | 2012-05-30 | 上海华虹Nec电子有限公司 | Super junction semiconductor device and manufacturing method thereof |
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