CN104599630B - Driving circuit, lighting control circuit, display panel and display device - Google Patents
Driving circuit, lighting control circuit, display panel and display device Download PDFInfo
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Abstract
The optimal embodiment of the invention provides a driving circuit, a lighting control circuit of the driving circuit, a display panel and a display device. The lighting control circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor and a second capacitor; the sixth transistor is connected in an equivalent diode form and can be conducted in one way; the second capacitor maintains stable level of the output end, thus a signal at the output end is avoided the influence from a clock signal, namely, the signal output by the output end of the lighting control circuit cannot be shaken; in addition, the tenth transistor transmits a first level signal or the eleventh transistor transmits a second level signal at the output end of the lighting control circuit in the whole working process, so that the signal output by the output end cannot be left, the output stability is improved, and the display effect is increased.
Description
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit, a light-emitting control circuit, a display panel and a display device.
Background
Organic light Emitting Display (Organic light Emitting Display) has become one of the key directions for the development of Display industry because of its technical advantages of no need of backlight, high contrast, thin thickness, wide viewing angle, high response speed, etc. The organic light emitting material is used as the light emitting material of the pixel, the pixel driving circuit is used for driving light emission, and the circuit design for providing the driving signal for the pixel driving circuit is the central importance of developing the organic light emitting display technology.
Disclosure of Invention
The preferred embodiment of the present invention mainly provides a light emission control circuit with a simple structure and a more stable output signal.
In one aspect, a preferred embodiment of the present invention provides a driving circuit including a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein:
the gate of the first transistor is coupled to a start signal input terminal for receiving a start signal, the first terminal of the first transistor is coupled to a second clock signal input terminal for receiving a second clock signal, and the second terminal of the first transistor is coupled to a first node;
a gate of the second transistor is coupled to the second clock signal input terminal, a first terminal of the second transistor is coupled to a second level signal input terminal for receiving a second level signal, and a second terminal of the second transistor is coupled to the first node;
a gate of the third transistor is coupled to the first node, a first terminal of the third transistor is coupled to a first clock signal input terminal for receiving a first clock signal, and a second terminal of the third transistor is coupled to a second node;
the gate of the fourth transistor is coupled to the start signal input terminal, the first terminal of the fourth transistor is coupled to a first level signal input terminal for receiving a first level signal, and the second terminal of the fourth transistor is coupled to the second node.
On the other hand, another preferred embodiment of the present invention provides a light emission control circuit, comprising an input unit and an inversion unit, wherein the input unit comprises the above-mentioned driving circuit.
Further, the reversing unit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor, and a second capacitor, wherein a gate of the fifth transistor is coupled to the second node, a first terminal of the fifth transistor is coupled to the first level signal input terminal, and a second terminal of the fifth transistor is coupled to the fourth node;
a first terminal of the sixth transistor is coupled to the first clock signal input terminal through the first capacitor, a gate of the sixth transistor is coupled to the first terminal, and a second terminal of the sixth transistor is coupled to the fourth node;
a gate of the seventh transistor is coupled to the fourth node, a second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor, and a first terminal of the seventh transistor is coupled to the second level signal input terminal;
a gate of the eighth transistor is coupled to the fourth node, a first terminal of the eighth transistor is coupled to the first level signal input terminal, and a second terminal of the eighth transistor is coupled to the third node;
a gate of the ninth transistor is coupled to the second node, a first terminal of the ninth transistor is coupled to the second level signal input terminal, and a second terminal of the ninth transistor is coupled to the third node;
a gate of the tenth transistor is coupled to the third node, a first terminal of the tenth transistor is coupled to the first level signal input terminal, and a second terminal of the tenth transistor is coupled to the output terminal of the light emission control circuit;
a gate of the eleventh transistor is coupled to the fourth node, a first terminal of the eleventh transistor is coupled to the second level signal input terminal, and a second terminal of the eleventh transistor is coupled to the output terminal of the light emission control circuit;
the second capacitor is coupled between the fourth node and the output end of the light-emitting control circuit.
On the other hand, another preferred embodiment of the present invention further provides a display panel, which includes N stages of the above light emission control circuit.
Further, a start signal input end of the first-stage light-emitting control circuit inputs a start signal, and a start signal input end of the I-th-stage light-emitting control circuit inputs an output signal of a previous-stage light-emitting control circuit, where I is 2,3, and … N.
On the other hand, a display device is further provided in a preferred embodiment of the present invention, including the display panel described above.
The driving circuit, the light-emitting control circuit, the display panel and the display device provided by the preferred embodiment of the invention at least have the following beneficial effects: the multi-stage light-emitting control circuits are mutually cascaded and only need one high-level trigger signal; the light-emitting control circuit is simple in structure, output signals cannot shake, output suspension cannot occur during working, output is more stable, and the display effect is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art lighting control circuit;
fig. 2 is a timing diagram of respective signals of the light emission control circuit of fig. 1;
FIG. 3 is a schematic diagram of a driving circuit provided in accordance with a preferred embodiment of the present invention;
FIG. 4 is a timing diagram of various signals of the driving circuit of FIG. 3;
FIGS. 5a to 5e are circuit diagrams corresponding to the respective operation stages of the driving circuit in FIG. 4;
FIG. 6 is a schematic diagram of a lighting control circuit according to a second preferred embodiment of the present invention;
fig. 7 is an operation timing diagram of the light emission control circuit in fig. 6;
FIGS. 8a to 8h are circuit diagrams corresponding to respective operation stages of the light emission control circuit in FIG. 6;
FIG. 9 is a schematic cross-sectional view of a display panel according to a third preferred embodiment of the present invention;
FIG. 10 is a schematic view of the structure of the second substrate of FIG. 9;
FIG. 11 is a schematic diagram of the connections of the transmit driver circuit of FIG. 10;
fig. 12 is a schematic structural diagram of a display device according to a fourth preferred embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the elements associated with the present invention are shown in the drawings.
As described in the background, the circuit design for providing driving signals for the pixel driving circuit is an important issue for OLED display, the pixel driving circuit generally needs the gate driving signal SCAN and the emission control signal Emit, and a plurality of gate driving signals SCAN may be needed for one row of OLED pixels. Generally, the light emission control signal is generated by a light emission driving circuit. The OLED display panel has N rows of pixels, and generally corresponds to N stages of light-emitting driving circuits, where each stage of light-emitting driving circuit generally includes a shift register circuit VSR and an inverter, and an output terminal of the shift register circuit is connected to an input terminal of the inverter. And the shift register circuit VSR of each stage of the light-emitting driving circuit is connected in a cascade manner, so that the corresponding light-emitting control signal Emit is generated stage by stage. The conventional pixel driving circuit has a PMOS structure, and the emission control signal Emit should be at a high level when the gate driving signal SCAN operates, so that the emission driving circuit needs to input a low level and then transmit the low level to the inverter through the shift register circuit VSR, that is, the conventional emission driving circuit inputs a low level signal.
The structure of the above-mentioned light emission driving circuit is too complicated, and thus alternative technologies have been successively developed, as shown in fig. 1, which is a circuit diagram of a light emission control circuit designed by samsung corporation (patent publication No.: US20140055444a1) that adopts a 10T3C structure, and the entire light emission control circuit does not adopt a shift register circuit and an inverter structure, but generates the light emission control signal Emi T directly from the 10T3C structure. Fig. 2 is a timing diagram illustrating the operation of the light-emitting control circuit in fig. 1, as can be seen from fig. 2, the light-emitting control circuit inputs a high-level start signal, but in the operation period from t4 to t5, since the potential at the N1 point is high, the M10 transistor is turned off, and thus the output terminal is floating, that is, the output signal is in an unstable state. In addition, when the light emission control circuit outputs, the output jitter phenomenon occurs because the potentials at the point N1 and the point N3 do not have the holding function. Therefore, the output is suspended and jittered, which results in unstable output signal of the light-emitting control circuit during operation and affects the display effect of the panel.
Example one
A driving circuit according to a first preferred embodiment of the present invention is shown IN fig. 3, and includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, wherein a gate of the first transistor M1 is coupled to a start signal input terminal IN for receiving a start signal, a first terminal of the first transistor M1 is coupled to a second clock signal input terminal XCK for receiving a second clock signal, and a second terminal of the first transistor M1 is coupled to a first node N1; a gate of the second transistor M2 is coupled to the second clock signal input terminal XCK, a first terminal is coupled to the second level signal input terminal VGL for receiving the second level signal, and a second terminal is coupled to the first node N1; a gate of the third transistor M3 is coupled to the first node N1, a first terminal thereof is coupled to the first clock signal input terminal CK for receiving the first clock signal, and a second terminal thereof is coupled to the second node N2; the fourth transistor M4 has a gate coupled to the start signal input terminal IN, a first terminal coupled to the first level signal input terminal VGH for receiving the first level signal, and a second terminal coupled to the second node N2.
Further, in the driving circuit provided in the first embodiment, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be PMOS transistors or NMOS transistors. Preferably, the first clock signal input from the first clock signal input terminal CK and the second clock signal input from the second clock signal input terminal XCK are pulse signals, and the phase difference is 180 degrees; when the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all PMOS transistors, the first level signal input by the first level signal input terminal VGH is a constant high level, and the second level signal input by the second level signal input terminal VGL is a constant low level; when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all NMOS transistors, the first level signal input from the first level signal input terminal VGH is at a constant low level, and the second level signal input from the second level signal input terminal VGL is at a constant high level. In practical use, the high level value of the start signal, the output signal, the first clock signal and the second clock signal can be 10V, the low level value can be-5V, and the high level value can be set according to the design type and the actual requirement of the transistor. For PMOS, the first terminal of the transistor is referred to as the source, and the second terminal is referred to as the drain. And for an NMOS transistor, the first terminal of the transistor is referred to as the drain, and the second terminal is referred to as the source.
Fig. 4 is a timing diagram illustrating a preferred operation of the driving circuit in fig. 3, wherein the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all PMOS transistors, the first level signal input from the first level signal input terminal VGH is at a constant high level, and the second level signal input from the second level signal input terminal VGL is at a constant low level.
The driving circuit provided by the first embodiment at least includes five operation periods, and the time points T1-T5 in fig. 4 correspond to five operation stages of the driving circuit provided by the first embodiment, as shown in fig. 5 a-5 e, respectively. The operation of a driving circuit according to an embodiment is described in detail below with reference to fig. 4 and 5a to 5 e:
fig. 5a is a circuit diagram of the first stage of the operation of the driving circuit IN the first embodiment, that is, the period T1 IN fig. 4, the start signal IN is inputted with a high level to control the first transistor M1 and the fourth transistor M4 to be turned off, the first clock signal CK is inputted with a high level, the second clock signal XCK is inputted with a low level to control the second transistor M2 to be turned on, the second level signal VGL is transmitted to the first node N1 through the second transistor M2 to make the potential of the first node be a low level, then the third transistor M3 is controlled to be turned on, and the third transistor M3 transmits the first clock signal CK to the second node N2 to make the potential of the second node be a high level.
Fig. 5b is a circuit diagram of a second stage of operation of the driving circuit according to the first embodiment, that is, during a period T2 IN fig. 4, the start signal IN is inputted with a high level to control the first transistor M1 and the fourth transistor M4 to be turned off, the first clock signal CK is inputted with a high level, the second clock signal XCK makes a transition from a low level to a high level to control the second transistor M2 to be turned off, the first node N1 keeps the previous stage potential, that is, the potential of the first node N1 keeps a low level, the third transistor M3 is controlled to be turned on, and the third transistor M3 transmits the first clock signal CK to the second node N2 to make the potential of the second node be a high level; the potential of the first node N1 is mainly held by the parasitic capacitance of the third transistor M3 at this stage, and thus the width-to-length ratio of the third transistor M3 is designed to be sufficiently large.
Fig. 5c is a circuit diagram of a third stage of operation of the driving circuit according to the first embodiment, that is, during a period T3 IN fig. 4, the start signal IN is inputted with a high level to control the first transistor M1 and the fourth transistor M4 to be turned off, the second clock signal XCK is inputted with a high level to control the second transistor M2 to be turned off, the first node N1 keeps a low level IN the previous stage, the third transistor M3 is controlled to be turned on, the first clock signal CK makes a transition, changes from the high level to the low level, and is transmitted to the second node N2 through the third transistor M3, so that the potential of the second node N2 is at the low level.
Fig. 5d is a circuit diagram of a fourth stage of operation of the driving circuit according to the first embodiment, that is, during a period T4 IN fig. 4, the start signal IN is inputted with a high level to control the first transistor M1 and the fourth transistor M4 to be turned off, the second clock signal XCK is inputted with a high level to control the second transistor M2 to be turned off, the first node N1 keeps a low level IN the previous stage, the third transistor M3 is controlled to be turned on, the first clock signal CK makes a transition, changes from a low level to a high level, and is transmitted to the second node N2 through the third transistor M3, so that the potential of the second node N2 is at a high level.
Fig. 5e is a circuit diagram of a fifth stage of operation of the driving circuit according to the first embodiment, that is, during a time period T5 IN fig. 4, the first clock signal CK inputs a high level, the start signal IN transitions from a high level to a low level, the first transistor M1 and the fourth transistor M4 are controlled to be turned on, the second clock signal XCK transitions from a high level to a low level, the second transistor M2 is controlled to be turned on, the second level signal VGL is transmitted to the first node N1 through the second transistor M2, the first transistor M1 transmits the second clock signal XCK at a low level to the first node, so that the potential of the first node N1 is at a low level, the third transistor M3 is controlled to be turned on, the third transistor M3 transmits the first clock signal CK at a high level to the second node N2, and the fourth transistor M4 transmits the first level signal VGH to the second node N2, so that the potential of the second node N2 is at a high level.
Example two
A second preferred embodiment of the present invention provides a light emitting control circuit, as shown in fig. 6, including an input unit 10 and an inversion unit 20, wherein the input unit 10 includes the driving circuit as described in the first embodiment, that is, includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4, and the inversion unit 20 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh fourth transistor M11, a first capacitor C1 and a second capacitor C2, that is, the entire light emitting driving circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M9, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, an eleventh transistor M10, an eleventh transistor M11, a fourth transistor M1, a first capacitor C365824, A second capacitor C2.
Wherein:
a gate of the first transistor M1 is coupled to a start signal input terminal IN for receiving a start signal, a first terminal is coupled to a second clock signal input terminal XCK for receiving a second clock signal, and a second terminal is coupled to the first node N1;
a gate of the second transistor M2 is coupled to the second clock signal input terminal XCK, a first terminal is coupled to the second level signal input terminal VGL for receiving the second level signal, and a second terminal is coupled to the first node N1;
a gate of the third transistor M3 is coupled to the first node N1, a first terminal thereof is coupled to the first clock signal input terminal CK for receiving the first clock signal, and a second terminal thereof is coupled to the second node N2;
a gate of the fourth transistor M4 is coupled to the start signal input terminal IN, a first terminal of the fourth transistor M4 is coupled to the first level signal input terminal VGH for receiving the first level signal, and a second terminal of the fourth transistor M4 is coupled to the second node N2;
a gate of the fifth transistor M5 is coupled to the second node N2, a first terminal thereof is coupled to the first level signal input terminal VGH, and a second terminal thereof is coupled to the fourth node N4;
a first terminal of the sixth transistor M6 is coupled to the first clock signal input terminal CK through the first capacitor C1, a gate of the sixth transistor M6 is coupled to the first terminal thereof, such that the sixth transistor M6 is equivalent to a diode and can only conduct in a single direction, and a second terminal of the sixth transistor M6 is coupled to the fourth node N4;
the gate of the seventh transistor M7 is coupled to the fourth node N4, the second terminal is coupled to the first terminal of the sixth transistor M6, and the first terminal is coupled to the second level signal input terminal VGL for receiving the second level signal;
a gate of the eighth transistor M8 is coupled to a fourth node N4, a first terminal thereof is coupled to the first level signal input terminal VGH, and a second terminal thereof is coupled to the third node N3;
a gate of the ninth transistor M9 is coupled to the second node N2, a first terminal thereof is coupled to the second level signal input terminal VGL, and a second terminal thereof is coupled to the third node N3;
a gate of the tenth transistor M10 is coupled to the third node N3, a first terminal thereof is coupled to the first level signal input terminal VGH, and a second terminal thereof is coupled to the output terminal OUT of the light emitting control circuit;
a gate of the eleventh transistor M11 is coupled to the fourth node N4, a first terminal thereof is coupled to the second level signal input terminal VGL, and a second terminal thereof is coupled to the output terminal OUT of the emission control circuit;
the second capacitor C2 is coupled between the fourth node N4 and the output terminal OUT of the light-emitting control circuit, and is used for keeping the output signal of the output terminal OUT stable.
Further, in the light emitting control circuit provided in the first embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 may be PMOS transistors or NMOS transistors. Preferably, the first clock signal input from the first clock signal input terminal CK and the second clock signal input from the second clock signal input terminal XCK are pulse signals, and the phase difference is 180 degrees. When the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all PMOS transistors, the first level signal input from the first level signal input terminal VGH is a constant high level, and the second level signal input from the second level signal input terminal VGL is a constant low level; when the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all NMOS transistors, the first level signal input from the first level signal input terminal VGH is at a constant low level, and the second level signal input from the second level signal input terminal VGL is at a constant high level. In practical use, the high level value of the start signal, the first level signal, the second level signal, the first clock signal and the second clock signal can be selected from 10V, the low level value can be selected from-5V, and the high level value can also be set according to the design type and the actual requirement of the transistor. For PMOS, the first terminal of the transistor is referred to as the source, and the second terminal is referred to as the drain. And for an NMOS transistor, the first terminal of the transistor is referred to as the drain, and the second terminal is referred to as the source.
Fig. 7 is a timing diagram illustrating a preferred operation of the light emission control circuit in fig. 6, wherein the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all PMOS transistors, the first level signal input from the first level signal input terminal VGH is a constant high level, and the second level signal input from the second level signal input terminal VGL is a constant low level.
The second embodiment provides a lighting control circuit comprising at least eight operation periods, and the time points T1-T8 in fig. 7 correspond to the eight operation stages of the second embodiment lighting control circuit, as shown in fig. 8 a-8 h, respectively. The operation of the second embodiment of the light emission control circuit is described in detail below with reference to fig. 7 and fig. 8a to 8 h:
fig. 8a is a circuit diagram of a first stage of operation of the light emitting control circuit IN the second embodiment, that is, a period T1 IN fig. 7, IN which the start signal IN is inputted with a low level to control the first transistor M1 and the fourth transistor M4 to be turned on, the second clock signal XCK is inputted with a high level, the first transistor M1 transmits the second clock signal XCK to the first node N1, so that the potential of the first node N1 is at a high level to control the third transistor M3 to be turned off, the first level signal VGH is transmitted to the second node N2 through the fourth transistor M4, so that the potential of the second node N2 is at a high level to control the fifth transistor M5 and the ninth transistor M9 to be turned off; the first clock signal CK makes a transition from a high level to a low level, and the bootstrap effect of the first capacitor C1 causes the gate potential of the sixth transistor to become low, and since the sixth transistor M6 is connected in an equivalent diode manner, the sixth transistor M6 is turned on and transmits a low level value to the fourth node N4, so that the potential of the fourth node N4 becomes low, and then the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned on, the eighth transistor M8 transmits the first level signal VGH to the third node N3, so that the potential of the third node N3 becomes high, the tenth transistor M1O is controlled to be turned off, and the eleventh transistor M11 transmits the second level signal VGL to the output terminal OUT of the light emitting control circuit as the output signal in this stage.
Fig. 8b is a circuit diagram of a second stage of operation of the light emitting control circuit according to the second embodiment, that is, during a period T2 IN fig. 7, the start signal IN is inputted with a low level to control the first transistor M1 and the fourth transistor M4 to be turned on, the first clock signal CK makes a transition and changes from the low level to the high level, the second clock signal XCK is inputted with a high level, the first transistor M1 transmits the second clock signal XCK to the first node N1 to make the potential of the first node N1 be at the high level, the third transistor M3 is controlled to be turned off, the first level signal VGH is transmitted to the second node N2 through the fourth transistor M4 to make the potential of the second node N2 be at the high level, and the fifth transistor M5 and the ninth transistor M9 are controlled to be turned off; the fourth node N4 is kept at the previous stage by the second capacitor C2, i.e. kept at a low level, and the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned on, the seventh transistor M7 transmits the second level signal VGL at a constant low level to the gate of the sixth transistor M6, although the transition of the first clock signal CK and the coupling effect of the first capacitor C1 have a transient pull-up effect on the gate potential of the sixth transistor M6, but the gate of the sixth transistor M6 becomes a low level, so that the sixth transistor M6 is turned on, the eighth transistor M8 transmits the first level signal VGH to the third node N3, so that the potential of the third node N3 becomes a high level, and the tenth transistor M1O is controlled to be turned off, and the eleventh transistor M11 transmits the second level signal VGL to the output terminal OUT of the lighting control circuit as the output signal of the stage.
Fig. 8c is a circuit diagram of a third stage of operation of the light emission control circuit IN the second embodiment, that is, during a period T3 IN fig. 7, the start signal IN transitions from a low level to a high level to control the first transistor M1 and the fourth transistor M4 to turn off, the first clock signal CK inputs a high level, the second clock signal XCK transitions from a high level to a low level to control the second transistor M2 to turn on, the second level signal VGL is transmitted to the first node N1 through the second transistor M2 to make the potential of the first node N1 be a low level, the third transistor M3 is controlled to turn on, the first clock signal CK is transmitted to the second node N2 through the third transistor M3 to make the potential of the second node N2 be a high level, and the fifth transistor M5 and the ninth transistor M9 are controlled to turn off; the potential of the fourth node N4 is maintained at the potential of the previous stage by the second capacitor C2, that is, at a low level, and the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned on, the seventh transistor M7 transmits the second level signal VGL to the gate of the sixth transistor M6, so that the sixth transistor M6 is turned on, the eighth transistor M8 transmits the first level signal VGH to the third node N3, so that the potential of the third node N3 becomes a high level, and the tenth transistor M1O is controlled to be turned off, and the eleventh transistor M11 transmits the second level signal VGL to the light emitting control circuit output terminal OUT as the output signal of the stage.
Fig. 8d is a circuit diagram of a fourth stage of operation of the light emission control circuit according to the second embodiment, that is, during a period T4 IN fig. 7, the start signal IN is inputted with a high level to control the first transistor M1 and the fourth transistor M4 to be turned off, the first clock signal CK is inputted with a high level, the second clock signal XCK makes a transition from a low level to a high level to control the second transistor M2 to be turned off, the first node N1 keeps the previous stage potential, that is, keeps the low level, the third transistor M3 is controlled to be turned on, the first clock signal CK is transmitted to the second node N2 through the third transistor M3, so that the potential of the second node N2 is at the high level to control the fifth transistor M5 and the ninth transistor M9 to be turned off; the potential of the fourth node N4 is maintained at the potential of the previous stage by the second capacitor C2, that is, at a low level, and the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned on, the seventh transistor M7 transmits the second level signal VGL to the gate of the sixth transistor M6, so that the sixth transistor M6 is turned on, the eighth transistor M8 transmits the first level signal VGH to the third node N3, so that the potential of the third node N3 becomes a high level, and the tenth transistor M1O is controlled to be turned off, and the eleventh transistor M11 transmits the second level signal VGL to the light emitting control circuit output terminal OUT as the output signal of the stage.
FIG. 8e is a circuit diagram illustrating a fifth phase of operation of the light emission control circuit according to the second embodiment, i.e., during the period T5 IN FIG. 7, the start signal IN is asserted to high to control the first transistor M1 and the fourth transistor M4 to be turned off, the second clock signal XCK is asserted to high to control the second transistor M2 to be turned off, the first node N1 is asserted to low, the third transistor M3 is asserted to high, the first clock signal CK transitions from high to low, and the first clock signal CK is transmitted to the second node N2 via the third transistor M3, so that the potential of the second node N2 is at a low level, the fifth transistor M5 and the ninth transistor M9 are controlled to be turned on, the first level signal VGH is transmitted to the fourth node N4 through the fifth transistor M5, so that the potential of the fourth node N4 becomes a high level, controlling the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 to be turned off; the second level signal is transmitted to the third node N3 through the ninth transistor M9, so that the potential of the third node N3 becomes low level, the tenth transistor M10 is controlled to be turned on, and the first level signal VGH is transmitted to the output terminal of the light emitting control circuit through the tenth transistor M10 as the output signal of this stage.
Fig. 8f is a circuit diagram of a sixth phase of the operation of the light emission control circuit IN the second embodiment, that is, IN the period T6 IN fig. 7, the start signal IN is inputted with a high level to control the first transistor M1 and the fourth transistor M4 to turn off, the second clock signal XCK is inputted with a high level to control the second transistor M2 to turn off, the first node N1 keeps the previous phase potential, that is, keeps the low level, the third transistor M3 is controlled to turn on, the first clock signal CK makes a transition to change from the low level to the high level, the first clock signal CK is transmitted to the second node N2 through the third transistor M3, so that the potential of the second node N2 is at the high level to control the fifth transistor M5 and the ninth transistor M9 to turn off, the transition of the first clock signal CK is coupled through the first capacitor C1, the gate potential of the sixth transistor M6 is pulled high, and the sixth transistor M6 is turned off; the potential of the fourth node N4 is kept at the previous stage potential by the second capacitor C2, i.e., kept at a high level, and the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned off; the third node N3 keeps the potential of the previous stage, i.e. the potential of the third node N3 keeps low level, and controls the tenth transistor M10 to turn on, and the first level signal VGH is transmitted to the output end of the light-emitting control circuit through the tenth transistor M10 as the output signal of the stage; the potential of the third node N3 is mainly held by the parasitic capacitance of the tenth transistor M10 at this stage, and thus the width-to-length ratio of the tenth transistor M10 is designed to be sufficiently large.
Fig. 8g is a circuit diagram of a seventh phase of operation of the light emission control circuit IN the second embodiment, that is, during a period T7 IN fig. 7, when the start signal IN transitions from high level to low level to control the first transistor M1 and the fourth transistor M4 to be turned on, the first clock signal CK inputs high level, the second clock signal XCK transitions from high level to low level to control the second transistor M2 to be turned on, the second level signal VGL is transmitted to the first node N1 through the second transistor M2 to make the potential of the first node N1 low level, the third transistor M3 is controlled to be turned on, the first clock signal CK is transmitted to the second node N2 through the third transistor M3 to make the potential of the second node N2 high level to control the fifth transistor M5 and the ninth transistor M9 to be turned off; the potential of the fourth node N4 is kept at the previous stage potential by the second capacitor C2, i.e., kept at a high level, and the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned off; the third node N3 keeps the potential of the previous stage, i.e. the potential of the third node N3 keeps low level, and controls the tenth transistor M10 to turn on, and the first level signal VGH is transmitted to the output end of the light-emitting control circuit through the tenth transistor M10 as the output signal of the stage; the potential of the third node N3 is mainly held by the parasitic capacitance of the tenth transistor M10 at this stage, and thus the width-to-length ratio of the tenth transistor M10 is designed to be sufficiently large.
Fig. 8h is a circuit diagram of an eighth phase of operation of the light emitting control circuit IN the second embodiment, that is, IN the period T8 IN fig. 7, the start signal IN is inputted with a low level to control the first transistor M1 and the fourth transistor M4 to be turned on, the first clock signal CK is inputted with a high level, the second clock signal XCK makes a transition from the low level to the high level to control the second transistor M2 to be turned off, the first transistor M1 transmits the second clock signal XCK to the first node N1 to make the potential of the first node N1 be a high level, the third transistor M3 is controlled to be turned off, the fourth transistor M4 transmits the first level signal VGH to the second node N2 to make the potential of the second node N2 be a high level, and the fifth transistor M5 and the ninth transistor M9 are controlled to be turned off; the potential of the fourth node N4 is kept at the previous stage potential by the second capacitor C2, i.e., kept at a high level, and the seventh transistor M7, the eighth transistor M8 and the eleventh transistor M11 are controlled to be turned off; the third node N3 keeps the potential of the previous stage, i.e. the potential of the third node N3 keeps low level, and controls the tenth transistor M10 to turn on, and the first level signal VGH is transmitted to the output terminal of the light emitting control circuit through the tenth transistor M10 as the output signal of this stage.
As can be seen from the above working process, the second capacitor C2 exists between the fourth node N4 and the output end OUT of the light-emitting control circuit, so that the potentials of the fourth node and the output end can be kept stable, and the influence of the jump of the first clock signal or the second clock signal is avoided, so that the signal output by the output end OUT of the light-emitting control circuit does not jitter. In the whole working process, at each stage, the tenth transistor M10 of the output end OUT transmits the first level signal VGH or the eleventh transistor M11 transmits the second level signal VGL, so that the signal output by the output end of the light-emitting control circuit is not suspended, and the output is more stable.
It should be noted that, in the light-emitting control circuit provided in the second embodiment, the first to eleventh transistors may be NMOS transistors, and in the operation process, only the level values of the start signal, the first clock signal, the second clock signal, the first level signal, and the second level signal need to be opposite.
EXAMPLE III
A third preferred embodiment of the present invention provides a display panel, a cross-sectional view of which is shown in fig. 9, and the display panel includes a first substrate 11 and a second substrate 12, where the first substrate 11 and the second substrate 12 are disposed opposite to each other, where the first substrate 11 may be a color film substrate, a Cover Glass (Cover Glass), a Cover Glass (Cover Lens), or the like, and the second substrate 12 may be a pixel array substrate, such as a common OLED pixel array substrate.
Fig. 10 is a schematic structural diagram of the second substrate 12 in the display panel according to the third embodiment of the invention. Referring to fig. 10, when the second substrate is a pixel array substrate, the method may include: a scan driving circuit 121, a data driving circuit 122, an emission driving circuit 123, m scan lines (S1, S2 … …, Sm), k data lines (D1, D2 … …, Dk), m emission driving lines (E1, E2, … …, Em), and a plurality of pixels 124; the emission driving circuit 123 in this embodiment includes multiple stages of the light emission control circuit as described in embodiment two.
Specifically, the scan drive circuit 121 in the present embodiment is configured to supply a scan signal to each scan line (S1, S2 … …, Sn); a data driving circuit 122 for supplying data signals to the respective data lines (D1, D2 … …, Dm); an emission driving circuit 123 for supplying a light emission driving signal to each emission driving line (E1, E2, … …, Em) to make a pixel driving circuit in the pixel 124 complete node initialization, threshold compensation, data writing, and the like; the pixels 124 are respectively disposed in regions where the scan lines and the data lines cross.
Fig. 11 is a connection diagram of the emission driving circuit 123 according to the third embodiment of the present invention, as shown in fig. 11, the emission driving circuit includes a plurality of stages of emission control circuits (E1, E2, E3, …), and the circuit diagram of each stage of emission control circuit is shown in fig. 6, and the emission control circuit is respectively connected to the first clock signal CK and the second clock signal XCK. The input end of the first stage of the light-emitting control circuit inputs the starting trigger signal STV, and then the input end of each stage of the light-emitting control circuit inputs the output signal of the previous stage of the light-emitting control circuit, so that a mutual cascade connection mode is formed, and the light-emitting drive signals are generated step by step under the drive of the first clock signal and the second clock signal.
According to the display panel provided by the fourth embodiment of the invention, the second substrate of the display panel adopts the emission driving circuit with stable output signals, so that the pixels in the second substrate can stably work, and the corresponding display panel can achieve a better display effect.
Example four
Fig. 12 is a schematic structural diagram of a display device according to a fourth preferred embodiment of the present invention, in which the display device 1 includes a display panel 2, and the structure of the display panel is the same as that of the display panel described in the third embodiment.
It should be noted that, in the embodiments of the present invention, the term "coupled" refers to an electrical connection between two components, including a direct electrical connection and an indirect electrical connection.
It should be understood that the above-described embodiments are merely illustrative of the present invention and are not to be construed as limiting the scope of the present invention. Those skilled in the art will appreciate that various modifications and changes can be made without inventive faculty, and all such modifications and changes are within the scope of the invention as defined in the claims.
Claims (9)
1. A drive circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein:
the gate of the first transistor is coupled to a start signal input terminal for receiving a start signal, the first terminal of the first transistor is coupled to a second clock signal input terminal for receiving a second clock signal, and the second terminal of the first transistor is coupled to a first node;
a gate of the second transistor is coupled to the second clock signal input terminal, a first terminal of the second transistor is coupled to a second level signal input terminal for receiving a second level signal, and a second terminal of the second transistor is coupled to the first node;
a gate of the third transistor is coupled to the first node, a first terminal of the third transistor is coupled to a first clock signal input terminal for receiving a first clock signal, and a second terminal of the third transistor is coupled to a second node;
the gate of the fourth transistor is coupled to the start signal input terminal, the first terminal of the fourth transistor is coupled to a first level signal input terminal for receiving a first level signal, and the second terminal of the fourth transistor is coupled to the second node.
2. The driving circuit of claim 1, wherein the operating state of the driving circuit comprises a first phase, a second phase, a third phase, a fourth phase, and a fifth phase, wherein:
in the first stage, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal controls the second transistor to be turned on, a second level signal is transmitted to a first node through the second transistor and controls the third transistor to be turned on, and the third transistor transmits a first clock signal to the second node;
in the second stage, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal jumps to control the second transistor to be turned off, the first node keeps the potential of the previous stage and controls the third transistor to be turned on, and the third transistor transmits the first clock signal to the second node;
in the third phase, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal controls the second transistor to be turned off, the first node keeps the potential of the previous phase, the third transistor is controlled to be turned on, and the first clock signal jumps and is transmitted to the second node through the third transistor;
in the fourth stage, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal controls the second transistor to be turned off, the first node keeps the potential of the previous stage, the third transistor is controlled to be turned on, and the first clock signal jumps and is transmitted to the second node through the third transistor;
in the fifth stage, the start signal makes a transition to control the first transistor and the fourth transistor to be turned on, the second clock signal makes a transition to control the second transistor to be turned on, a second level signal is transmitted to the first node through the second transistor to control the third transistor to be turned on, and the fourth transistor transmits a first level signal to the second node.
3. A lighting control circuit comprising an input unit and an inversion unit, wherein the input unit comprises a drive circuit according to any one of claims 1 to 2;
the reversing unit includes: a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor, and a second capacitor, wherein,
a gate of the fifth transistor is coupled to the second node, a first terminal of the fifth transistor is coupled to the first level signal input terminal, and a second terminal of the fifth transistor is coupled to a fourth node;
a first terminal of the sixth transistor is coupled to the first clock signal input terminal through the first capacitor, a gate of the sixth transistor is coupled to the first terminal, and a second terminal of the sixth transistor is coupled to the fourth node;
a gate of the seventh transistor is coupled to the fourth node, a second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor, and a first terminal of the seventh transistor is coupled to the second level signal input terminal;
a gate of the eighth transistor is coupled to the fourth node, a first terminal of the eighth transistor is coupled to the first level signal input terminal, and a second terminal of the eighth transistor is coupled to the third node;
a gate of the ninth transistor is coupled to the second node, a first terminal of the ninth transistor is coupled to the second level signal input terminal, and a second terminal of the ninth transistor is coupled to the third node;
a gate of the tenth transistor is coupled to the third node, a first terminal of the tenth transistor is coupled to the first level signal input terminal, and a second terminal of the tenth transistor is coupled to the output terminal of the light emission control circuit;
a gate of the eleventh transistor is coupled to the fourth node, a first terminal of the eleventh transistor is coupled to the second level signal input terminal, and a second terminal of the eleventh transistor is coupled to the output terminal of the light emission control circuit;
the second capacitor is coupled between the fourth node and the output end of the light-emitting control circuit.
4. The lighting control circuit of claim 3, wherein the operating state of the lighting control circuit includes a first phase, a second phase, a third phase, a fourth phase, a fifth phase, a sixth phase, a seventh phase, and an eighth phase, wherein,
in the first phase, the start signal controls the first transistor and the fourth transistor to be turned on, the first transistor transmits the second clock signal to the first node and controls the third transistor to be turned off, and the first level signal is transmitted to the second node through the fourth transistor and controls the fifth transistor and the ninth transistor to be turned off; the first clock signal controls the electric potential of the grid electrode of the sixth transistor through the first capacitor so as to enable the sixth transistor to be turned on, the electric potential of the grid electrode of the sixth transistor is transmitted to the fourth node through the sixth transistor, then a seventh transistor, an eighth transistor and an eleventh transistor are controlled to be turned on, the eighth transistor transmits a first level signal to the third node and controls a tenth transistor to be turned off, and the eleventh transistor transmits a second level signal to the output end of the light-emitting control circuit to serve as an output signal of the stage;
in the second stage, the start signal controls the first transistor and the fourth transistor to be turned on, the first transistor transmits the second clock signal to the first node and controls the third transistor to be turned off, and the first level signal is transmitted to the second node through the fourth transistor and controls the fifth transistor and the ninth transistor to be turned off; the fourth node potential is kept at the potential of the previous stage by a second capacitor, and then a seventh transistor, an eighth transistor and an eleventh transistor are controlled to be turned on, the seventh transistor transmits a second level signal to the grid electrode of a sixth transistor so as to enable the sixth transistor to be turned on, the eighth transistor transmits a first level signal to the third node and controls a tenth transistor to be turned off, and the eleventh transistor transmits a second level signal to the output end of the light-emitting control circuit to serve as an output signal of the stage;
in the third phase, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal controls the second transistor to be turned on, a second level signal is transmitted to a first node through the second transistor and controls the third transistor to be turned on, a first clock signal is transmitted to the second node through the third transistor and controls the fifth transistor and the ninth transistor to be turned off; the fourth node potential is kept at the potential of the previous stage by a second capacitor, and then a seventh transistor, an eighth transistor and an eleventh transistor are controlled to be turned on, the seventh transistor transmits a second level signal to the grid electrode of a sixth transistor so as to enable the sixth transistor to be turned on, the eighth transistor transmits a first level signal to the third node and controls a tenth transistor to be turned off, and the eleventh transistor transmits a second level signal to the output end of the light-emitting control circuit to serve as an output signal of the stage;
in the fourth stage, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal makes a transition to control the second transistor to be turned off, the first node keeps a potential of a previous stage and controls the third transistor to be turned on, and the first clock signal is transmitted to the second node through the third transistor and controls the fifth transistor and the ninth transistor to be turned off; the fourth node potential is kept at the potential of the previous stage by a second capacitor, and then the seventh transistor, the eighth transistor and the eleventh transistor are controlled to be turned on, the seventh transistor transmits a second level signal to the grid electrode of the sixth transistor to enable the sixth transistor to be turned on, the eighth transistor transmits a first level signal to the third node to control the tenth transistor to be turned off, and the eleventh transistor transmits a second level signal to the output end of the light-emitting control circuit to serve as an output signal of the stage;
in the fifth stage, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal controls the second transistor to be turned off, the first node keeps the potential of the previous stage, the third transistor is controlled to be turned on, the first clock signal makes a transition and is transmitted to the second node through the third transistor, the fifth transistor and the ninth transistor are controlled to be turned on, the first level signal is transmitted to the fourth node through the fifth transistor, and the seventh transistor, the eighth transistor and the eleventh transistor are controlled to be turned off; the second level signal is transmitted to the third node through the ninth transistor to control the tenth transistor to be turned on, and the first level signal is transmitted to the output end of the light-emitting control circuit through the tenth transistor to serve as an output signal of the stage;
in the sixth stage, the start signal controls the first transistor and the fourth transistor to be turned off, the second clock signal controls the second transistor to be turned off, the first node keeps the potential of the previous stage, the third transistor is controlled to be turned on, the first clock signal jumps and is transmitted to the second node through the third transistor, the fifth transistor and the ninth transistor are controlled to be turned off, the potentials of the third node and the fourth node keep the previous stage, and the signal at the output end of the light-emitting control circuit keeps unchanged;
in the seventh stage, the start signal jumps to control the first transistor and the fourth transistor to be turned on, the second clock signal jumps to control the second transistor to be turned on, a second level signal is transmitted to the first node through the second transistor to control the third transistor to be turned on, the first level signal is transmitted to the second node through the fourth transistor to control the fifth transistor and the ninth transistor to be turned off, and the potentials of the third node and the fourth node keep the same in the previous stage, and the signal at the output end of the light-emitting control circuit keeps unchanged;
in the eighth stage, the start signal controls the first transistor and the fourth transistor to be turned on, the second clock signal makes a transition to control the second transistor to be turned off, the first transistor transmits a second clock signal to the first node to control the third transistor to be turned off, the first level signal is transmitted to the second node through the fourth transistor to control the fifth transistor and the ninth transistor to be turned off, and the potentials of the third node and the fourth node keep the same in the previous stage, so that the signal at the output end of the light-emitting control circuit keeps unchanged.
5. The light emission control circuit according to claim 3 or 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor are all PMOS transistors, the first level signal is a constant high level, and the second level signal is a constant low level; or,
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are all NMOS transistors, the first level signal is a constant low level, and the second level signal is a constant high level.
6. The lighting control circuit according to claim 3 or 4, wherein the first clock signal and the second clock signal are out of phase by pi.
7. A display panel comprising N stages of the light emission control circuit according to any one of claims 3 to 6.
8. The display panel according to claim 7, wherein a start signal input terminal of the first-stage emission control circuit inputs a start signal, and a start signal input terminal of the I-th-stage emission control circuit inputs an output signal of a previous-stage emission control circuit, I-2, 3, … N.
9. A display device characterized by comprising the display panel according to claim 7 or 8.
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| CN105679239B (en) * | 2016-03-10 | 2018-06-22 | 北京大学深圳研究生院 | A kind of integrated gate drive circuitry, AMOLED pixel circuit and panel |
| CN105761757B (en) * | 2016-05-13 | 2018-05-18 | 京东方科技集团股份有限公司 | Shift register cell, driving method, array substrate, display panel and device |
| CN105810142B (en) * | 2016-05-20 | 2019-09-27 | 上海天马有机发光显示技术有限公司 | Shifting deposit unit and its driving method, shift-register circuit, display device |
| CN108122534B (en) | 2016-11-29 | 2019-03-26 | 昆山国显光电有限公司 | A kind of drive control circuit and its driving method, display device |
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| JP2001100653A (en) * | 1999-09-29 | 2001-04-13 | Tdk Corp | Shift register and image display device |
| KR100910562B1 (en) * | 2002-12-17 | 2009-08-03 | 삼성전자주식회사 | Device of driving display device |
| JP4646187B2 (en) * | 2004-02-12 | 2011-03-09 | 東北パイオニア株式会社 | Light emitting display device and drive control method thereof |
| KR100646992B1 (en) * | 2005-09-13 | 2006-11-23 | 삼성에스디아이 주식회사 | Emission driver and organic light emitting display using the same |
| TW200949807A (en) * | 2008-04-18 | 2009-12-01 | Ignis Innovation Inc | System and driving method for light emitting device display |
| US8330702B2 (en) * | 2009-02-12 | 2012-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Pulse output circuit, display device, and electronic device |
| IN2012DN01823A (en) * | 2009-10-16 | 2015-06-05 | Semiconductor Energy Lab | |
| CN102760407B (en) * | 2012-07-13 | 2015-11-25 | 京东方科技集团股份有限公司 | Emission control circuit, light-emitting control method and shift register |
| TWI497474B (en) * | 2013-12-25 | 2015-08-21 | Au Optronics Corp | Light emitting control circuit |
| CN103985346B (en) * | 2014-05-21 | 2017-02-15 | 上海天马有机发光显示技术有限公司 | TFT array substrate, display panel and display substrate |
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