CN104332496A - Injection reinforced bipolar transistor of insulated gate - Google Patents
Injection reinforced bipolar transistor of insulated gate Download PDFInfo
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- CN104332496A CN104332496A CN201410614629.5A CN201410614629A CN104332496A CN 104332496 A CN104332496 A CN 104332496A CN 201410614629 A CN201410614629 A CN 201410614629A CN 104332496 A CN104332496 A CN 104332496A
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- 238000002347 injection Methods 0.000 title abstract description 9
- 239000007924 injection Substances 0.000 title abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 36
- 239000012535 impurity Substances 0.000 claims description 24
- 238000009413 insulation Methods 0.000 claims description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 18
- 229910052785 arsenic Inorganic materials 0.000 claims description 18
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims description 18
- 239000011574 phosphorus Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 6
- 239000005864 Sulphur Substances 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 6
- -1 proton Chemical compound 0.000 claims description 6
- 229910052711 selenium Inorganic materials 0.000 claims description 6
- 239000011669 selenium Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000000737 periodic effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 230000001413 cellular effect Effects 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
The invention relates to the field of power semiconductor devices, in particular to an injection reinforced bipolar transistor of an insulated gate. The injection reinforced bipolar transistor comprises a p-type collector electrode, wherein a carrier diffusion layer is arranged on the p-type collector electrode. A plurality of grooves are longitudinally arranged on the carrier diffusion layer, and a plurality of rows of p-type mixing zones are transversely arranged on the carrier diffusion layer. Each row of p-type mixing zones comprises a plurality of independent p-type active zones and a plurality of independent p-type non-active zones, and the zones are separated by the grooves. The injection reinforced bipolar transistor is provided with strip-shaped periodic separate cell structures, emitting electrodes are correspondingly in separate shapes, accordingly holes generate the accumulative effect in the zones not covered by the emitting electrodes, further the carrier concentration of the zones close to the grooves is improved, and the on-state voltage drop is reduced.
Description
Technical field
The present invention relates to power semiconductor field, mainly a kind of injection reinforced insulation grid bipolar transistor.
Background technology
Insulated gate bipolar transistor is widely used in the core control field of power electronics industry, trench gate is one of core technology of this series products, its main purpose can realize larger current density and less conduction voltage drop, thus reduces device size and reduce power consumption.Traditional insulated gate bipolar transistor is (trench gate one side) when manufacturing Facad structure, the mode of usual employing cellular region all standing, which will cause device operationally to overflow emitter rapidly in hole, the region carrier concentration reduced near groove is lower, and the reduction of conduction voltage drop is restricted.
In prior art, bipolar transistor structure is also improved, if the patent No. is CN200920192176.6, the applying date is 2009-08-31, name is called the utility model patent of " insulated gate bipolar transistor ", its technical scheme is: the utility model insulated gate bipolar transistor, it is included in the substrate that N-substrate surface carries out the N-ion implantation formation of low concentration, be formed in the grid oxic horizon of substrate surface, be deposited on the polysilicon gate on grid oxic horizon, be formed in the p+ well region between grid oxic horizon and N-substrate and the N+ well region between p+ well region and grid oxic horizon, be positioned at the injection region, the back side below N-substrate, the emitter being positioned at the collector electrode below injection region and being positioned at above grid oxic horizon, N-type substrate below grid oxic horizon adds a dense P type trap zone,
For another example number of patent application is CN201210333321.4, the applying date is 2012-09-11, name is called the patent of invention of " insulated gate bipolar transistor that a kind of collector electrode terminal has dielectric layer ", its technical scheme is: a kind of collector electrode terminal has the insulated gate bipolar transistor of dielectric layer, belongs to power semiconductor and power integrated circuit technical field.The present invention, on the basis of traditional insulated gate bipolar transistor structure, introduces the continuous or discrete dielectric layer of one deck in device terminal collector region.
In above-mentioned patent, the grid of CN200920192176.6 is plane, the innovation of CN201210333321.4 is the back side, namely one deck dielectric layer is introduced at the terminal correspondence position of collector electrode, and Facad structure (trench gate one side) is still traditional structure, so still there is the lower problem of carrier concentration in turn on process.
summary of the invention
For the reduction of the conduction voltage drop solving existing bipolar transistor is restricted, separation property structure cell of present proposition a kind of striated cycle, emitter correspondence is formed and is separated shape, there is build-up effect in the region making hole not form covering at emitter, thus improving the carrier concentration of groove near zone, the one reducing conduction voltage drop further injects reinforced insulation grid bipolar transistor.
A kind of injection reinforced insulation grid bipolar transistor, it is characterized in that: comprise p-type collector electrode, described p-type collector electrode is provided with carrier diffusion layer, described carrier diffusion layer is vertically arranged with many grooves, described carrier diffusion layer is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region and p-type inactive area, separated by described groove between each block; P-type active region on described often row p-type mixed zone and p-type inactive area interval are arranged, and the p-type active region on the upper same row of adjacent row and p-type inactive area interval are arranged, described each p-type active region is provided with N-shaped emitter, and described N-shaped emitter is H type.
Field is provided with by layer between described p-type collector electrode and carrier diffusion layer.
Described field cutoff layer is heavily doped n-layer.
Described carrier diffusion layer is for gently to mix n-layer; Described N-shaped emitter is heavily doped n-layer.
The described transverse width often arranging p-type mixed zone is 2um-20um, and longitudinal width is the 2um-40um degree of depth is 2um-8um.
Described trench length direction is vertical with the length direction of p-type mixed zone.
Described groove includes U-shaped blanket insulative layer, for N-shaped fills polysilicon in described blanket insulative layer.
Described blanket insulative layer comprises silica and silicon nitride.
Described N-shaped is filled in polysilicon doped with phosphorus or arsenic.
The width of described groove is 0.5um-2um, and the degree of depth is 2um-8um, and the spacing between adjacent trenches is 2um-8um.
The N-shaped emitter dual-side of described H type relies on described blanket insulative layer, and the width of described dual-side is respectively 0.5um-3um, and the width between described H type dual-side is 0.5um-8um, and the degree of depth of described H type is 0.1um-1um.
The impurity of described p-type active region is boron, and the degree of depth is 2um-8um.
The impurity of described p-type inactive area is boron, and the degree of depth is 2um-8um.
The impurity of described p-type collector electrode is boron, and the degree of depth is 0.1um-2um.
Described field comprises phosphorus, selenium, proton, sulphur, arsenic or defect doping by layer impurity, and the degree of depth is 2um-20um.
Described n-type area of gently mixing is doped to phosphorus or arsenic, adopts gas to mix or middle photograph silicon chip.
Described p-type inactive area is or/and be provided with p-type emitter in p-type active region.
Described p-type emitter is attached most importance to doping p-type layer.
The advantage of the application is:
Striated cycle separation property structure cell is provided with in the bipolar transistor of 1, the application, emitter correspondence is formed and is separated shape, there is build-up effect in the region making hole not form covering at emitter, thus improves the carrier concentration of groove near zone, reduces conduction voltage drop further.
2, the application is in trench gate one side, be set to as cellular region non-fully covered structure, and the grid of the application is groove-shaped, completely different from the structure of documents and prior art.
3, due to the existence of p-type inactive area, hole will produce build-up effect under p-type inactive area, thus improve the carrier concentration near emitter, strengthen the conductivity modulation effect in this region, reduce conducting resistance, thus reduce conduction voltage drop.
4, the p-type active region mixed and p-type inactive area make the carrier accumulation near emitter more even.
5, " H " type emitter structure of the application can avoid the position deviation that causes because of lithographic accuracy, and the N-shaped emitter of both sides is connected together.
Accompanying drawing explanation
Fig. 1 is the application's basic block diagram.
Fig. 2 is B-B ' place cross-sectional view in Fig. 1.
Fig. 3 adds p-type emitter for comparing Fig. 2.
Fig. 4 all increases p-type emitter in p-type active region and p-type inactive area.
Fig. 5 is A-A ' place cross-sectional view in Fig. 1.
Fig. 6 is A-A ' place cross-sectional view when cancelling p-type inactive area.
In accompanying drawing: p-type collector electrode 101, field by layer 102, carrier diffusion layer 103, p-type active region 1041, p-type inactive area 1042, N-shaped emitter 105, p-type emitter 106, blanket insulative layer 201, groove 202.
Embodiment
Embodiment 1
A kind of reinforced insulation grid bipolar transistor that injects comprises p-type collector electrode 101, described p-type collector electrode 101 is provided with carrier diffusion layer 103, described carrier diffusion layer 103 is vertically arranged with many grooves 202, described carrier diffusion layer 103 is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region 1041 and p-type inactive area 1042, separated by described groove 202 between each block; P-type active region 1041 on described often row p-type mixed zone and p-type inactive area 1042 interval are arranged, and the p-type active region 1041 on the upper same row of adjacent row and p-type inactive area 1042 interval are arranged, described each p-type active region 1041 is provided with N-shaped emitter 105, and described N-shaped emitter 105 is in H type.
Striated cycle separation property structure cell is provided with in the bipolar transistor of the application, emitter correspondence is formed and is separated shape, there is build-up effect in the region making hole not form covering at emitter, thus improves the carrier concentration of groove 202 near zone, reduces conduction voltage drop further.The application, in groove 202 grid one side, be set to as cellular region non-fully covered structure, and the grid of the application is groove 202 type, completely different from the structure of documents and prior art.Due to the existence of p-type inactive area 1042, hole will produce build-up effect 1042 times at p-type inactive area, thus improve the carrier concentration near emitter, strengthen the conductivity modulation effect in this region, will reduce conducting resistance, thus reduce conduction voltage drop.P-type active region 1041 and the p-type inactive area 1042 of mixing make the carrier accumulation near emitter more even." H " type emitter structure of the application can avoid the position deviation caused because of lithographic accuracy, and the N-shaped emitter 105 of both sides is connected together.
Embodiment 2
A kind of reinforced insulation grid bipolar transistor that injects comprises p-type collector electrode 101, described p-type collector electrode 101 is provided with carrier diffusion layer 103, described carrier diffusion layer 103 is vertically arranged with many grooves 202, described carrier diffusion layer 103 is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region 1041 and p-type inactive area 1042, separated by described groove 202 between each block; P-type active region 1041 on described often row p-type mixed zone and p-type inactive area 1042 interval are arranged, and the p-type active region 1041 on the upper same row of adjacent row and p-type inactive area 1042 interval are arranged, described each p-type active region 1041 is provided with N-shaped emitter 105, and described N-shaped emitter 105 is in H type.
Field is provided with by layer 102 between p-type collector electrode 101 and carrier diffusion layer 103.Field cutoff layer is heavily doped n-layer.Described carrier diffusion layer 103 is for gently to mix n-layer; Described N-shaped emitter 105 is heavily doped n-layer.The transverse width often arranging p-type mixed zone is 2um-20um, and longitudinal width is the 2um-40um degree of depth is 2um-8um.
Groove 202 length direction is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped blanket insulative layer 201, for N-shaped fills polysilicon in described blanket insulative layer 201.
Blanket insulative layer 201 comprises silica and silicon nitride.N-shaped is filled in polysilicon doped with phosphorus and arsenic.
The width of groove 202 is 0.5um-2um, and the degree of depth is 2um-8um, and the spacing between adjacent trenches 202 is 2um-8um.N-shaped emitter 105 dual-side of H type relies on described blanket insulative layer 201, and the width of described dual-side is respectively 0.5um-3um, and the width between described H type dual-side is 0.5um-8um, and the degree of depth of described H type is 0.1um-1um.The impurity of p-type active region 1041 is boron, and the degree of depth is 2um-8um.The impurity of p-type inactive area 1042 is boron, and the degree of depth is 2um-8um.The impurity of p-type collector electrode 101 is boron, and the degree of depth is 0.1um-2um.
Field comprises phosphorus, selenium, proton, sulphur, arsenic or defect doping by layer 102 impurity, and the degree of depth is 2um-20um.Gently mix n-type area and be doped to phosphorus or arsenic, adopt gas to mix or middle photograph silicon chip.P-type inactive area 1042 is or/and be provided with p-type emitter 106 in p-type active region 1041.P-type emitter 106 is attached most importance to doping p-type layer.
Striated cycle separation property structure cell is provided with in the bipolar transistor of the application, emitter correspondence is formed and is separated shape, there is build-up effect in the region making hole not form covering at emitter, thus improves the carrier concentration of groove 202 near zone, reduces conduction voltage drop further.The application, in groove 202 grid one side, be set to as cellular region non-fully covered structure, and the grid of the application is groove 202 type, completely different from the structure of documents and prior art.Due to the existence of p-type inactive area 1042, hole will produce build-up effect 1042 times at p-type inactive area, thus improve the carrier concentration near emitter, strengthen the conductivity modulation effect in this region, will reduce conducting resistance, thus reduce conduction voltage drop.P-type active region 1041 and the p-type inactive area 1042 of mixing make the carrier accumulation near emitter more even." H " type emitter structure of the application can avoid the position deviation caused because of lithographic accuracy, and the N-shaped emitter 105 of both sides is connected together.
Embodiment 3
A kind of reinforced insulation grid bipolar transistor that injects comprises p-type collector electrode 101, described p-type collector electrode 101 is provided with carrier diffusion layer 103, described carrier diffusion layer 103 is vertically arranged with many grooves 202, described carrier diffusion layer 103 is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region 1041 and p-type inactive area 1042, separated by described groove 202 between each block; P-type active region 1041 on described often row p-type mixed zone and p-type inactive area 1042 interval are arranged, and the p-type active region 1041 on the upper same row of adjacent row and p-type inactive area 1042 interval are arranged, described each p-type active region 1041 is provided with N-shaped emitter 105, and described N-shaped emitter 105 is in H type.
Field is provided with by layer 102 between p-type collector electrode 101 and carrier diffusion layer 103.Field cutoff layer is heavily doped n-layer.The transverse width often arranging p-type mixed zone is 20um, and longitudinal width is the 2um degree of depth is 8um.
Groove 202 length direction is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped blanket insulative layer 201, for N-shaped fills polysilicon in described blanket insulative layer 201.
Blanket insulative layer 201 comprises silica and silicon nitride.N-shaped is filled in polysilicon doped with phosphorus and arsenic.
The width of groove 202 is 0.5um, and the degree of depth is 8um, and the spacing between adjacent trenches 202 is 2um.N-shaped emitter 105 dual-side of H type relies on described blanket insulative layer 201, and the width of described dual-side is respectively 3um, and the width between described H type dual-side is 0.5um, and the degree of depth of described H type is 1um.The impurity of p-type active region 1041 is boron, and the degree of depth is 2um.The impurity of p-type inactive area 1042 is boron, and the degree of depth is 8um.The impurity of p-type collector electrode 101 is boron, and the degree of depth is 0.1um.
Field comprises phosphorus, selenium, proton, sulphur, arsenic or defect doping by layer 102 impurity, and the degree of depth is 20um.Gently mix n-type area and be doped to phosphorus or arsenic, adopt gas to mix or middle photograph silicon chip.P-type inactive area 1042 is or/and be provided with p-type emitter 106 in p-type active region 1041.P-type emitter 106 is attached most importance to doping p-type layer.
Embodiment 4
A kind of reinforced insulation grid bipolar transistor that injects comprises p-type collector electrode 101, described p-type collector electrode 101 is provided with carrier diffusion layer 103, described carrier diffusion layer 103 is vertically arranged with many grooves 202, described carrier diffusion layer 103 is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region 1041 and p-type inactive area 1042, separated by described groove 202 between each block; P-type active region 1041 on described often row p-type mixed zone and p-type inactive area 1042 interval are arranged, and the p-type active region 1041 on the upper same row of adjacent row and p-type inactive area 1042 interval are arranged, described each p-type active region 1041 is provided with N-shaped emitter 105, and described N-shaped emitter 105 is in H type.
Field is provided with by layer 102 between p-type collector electrode 101 and carrier diffusion layer 103.Field cutoff layer is heavily doped n-layer.Described carrier diffusion layer 103 is for gently to mix n-layer; Described N-shaped emitter 105 is heavily doped n-layer.The transverse width often arranging p-type mixed zone is 2um, and longitudinal width is the 40um degree of depth is 2um.
Groove 202 length direction is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped blanket insulative layer 201, for N-shaped fills polysilicon in described blanket insulative layer 201.
Blanket insulative layer 201 comprises silica and silicon nitride.N-shaped is filled in polysilicon doped with phosphorus and arsenic.
The width of groove 202 is 2um, and the degree of depth is 2um, and the spacing between adjacent trenches 202 is 8um.N-shaped emitter 105 dual-side of H type relies on described blanket insulative layer 201, and the width of described dual-side is respectively 0.5um, and the width between described H type dual-side is 8um, and the degree of depth of described H type is 0.1um.The impurity of p-type active region 1041 is boron, and the degree of depth is 8um.The impurity of p-type inactive area 1042 is boron, and the degree of depth is 2um.The impurity of p-type collector electrode 101 is boron, and the degree of depth is 2um.
Field comprises phosphorus, selenium, proton, sulphur, arsenic or defect doping by layer 102 impurity, and the degree of depth is 2um.Gently mix n-type area and be doped to phosphorus or arsenic, adopt gas to mix or middle photograph silicon chip.P-type inactive area 1042 is or/and be provided with p-type emitter 106 in p-type active region 1041.P-type emitter 106 is attached most importance to doping p-type layer.
Embodiment 5
A kind of reinforced insulation grid bipolar transistor that injects comprises p-type collector electrode 101, described p-type collector electrode 101 is provided with carrier diffusion layer 103, described carrier diffusion layer 103 is vertically arranged with many grooves 202, described carrier diffusion layer 103 is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region 1041 and p-type inactive area 1042, separated by described groove 202 between each block; P-type active region 1041 on described often row p-type mixed zone and p-type inactive area 1042 interval are arranged, and the p-type active region 1041 on the upper same row of adjacent row and p-type inactive area 1042 interval are arranged, described each p-type active region 1041 is provided with N-shaped emitter 105, and described N-shaped emitter 105 is in H type.
Field is provided with by layer 102 between p-type collector electrode 101 and carrier diffusion layer 103.Field cutoff layer is heavily doped n-layer.Described carrier diffusion layer 103 is for gently to mix n-layer; Described N-shaped emitter 105 is heavily doped n-layer.The transverse width often arranging p-type mixed zone is 10um, and longitudinal width is the 21um degree of depth is 4um.
Groove 202 length direction is vertical with the length direction of p-type mixed zone.Groove 202 includes U-shaped blanket insulative layer 201, for N-shaped fills polysilicon in described blanket insulative layer 201.
Blanket insulative layer 201 comprises silica and silicon nitride.N-shaped is filled in polysilicon doped with phosphorus and arsenic.
The width of groove 202 is 1um, and the degree of depth is 3um, and the spacing between adjacent trenches 202 is 5um.N-shaped emitter 105 dual-side of H type relies on described blanket insulative layer 201, and the width of described dual-side is respectively 1.2um, and the width between described H type dual-side is 3um, and the degree of depth of described H type is 0.5um.The impurity of p-type active region 1041 is boron, and the degree of depth is 4um.The impurity of p-type inactive area 1042 is boron, and the degree of depth is 5um.The impurity of p-type collector electrode 101 is boron, and the degree of depth is 1.1um.
Field comprises phosphorus, selenium, proton, sulphur, arsenic or defect doping by layer 102 impurity, and the degree of depth is 12um.Gently mix n-type area and be doped to phosphorus or arsenic, adopt gas to mix or middle photograph silicon chip.P-type inactive area 1042 is or/and be provided with p-type emitter 106 in p-type active region 1041.P-type emitter 106 is attached most importance to doping p-type layer.
It should be noted that the structure disclosed in this patent is not only applicable to insulated gate bipolar transistor, be equally applicable to other channel-type power semiconductors such as MOSFET.Parameter disclosed in patent and method only for reference, protection content is not limited only to parameter described in literary composition, and in this field, technical staff can apply after suitably adjusting.
Claims (10)
1. one kind is injected reinforced insulation grid bipolar transistor, it is characterized in that: comprise p-type collector electrode (101), described p-type collector electrode (101) is provided with carrier diffusion layer (103), described carrier diffusion layer (103) is vertically arranged with many grooves (202), described carrier diffusion layer (103) is horizontally arranged with many row p-type mixed zones, often arrange p-type mixed zone and comprise multiple independently p-type active region (1041) and p-type inactive area (1042), separated by described groove (202) between each block; P-type active region (1041) on described often row p-type mixed zone and p-type inactive area (1042) interval are arranged, and the p-type active region (1041) on the upper same row of adjacent row and p-type inactive area (1042) interval are arranged, described each p-type active region (1041) is provided with N-shaped emitter (105), and described N-shaped emitter (105) is in H type.
2. one according to claim 1 injects reinforced insulation grid bipolar transistor, it is characterized in that: be provided with field between described p-type collector electrode (101) and carrier diffusion layer (103) by layer (102), described field cutoff layer is heavily doped n-layer; Described carrier diffusion layer (103) is for gently to mix n-layer; Described N-shaped emitter (105) is heavily doped n-layer.
3. one according to claim 1 and 2 injects reinforced insulation grid bipolar transistor, it is characterized in that: the described transverse width often arranging p-type mixed zone is 2um-20um, and longitudinal width is the 2um-40um degree of depth is 2um-8um.
4. one according to claim 3 injects reinforced insulation grid bipolar transistor, it is characterized in that: described groove (202) includes U-shaped blanket insulative layer (201), for N-shaped fills polysilicon in described blanket insulative layer (201); Described groove (202) length direction is vertical with the length direction of p-type mixed zone.
5. one according to claim 4 injects reinforced insulation grid bipolar transistor, it is characterized in that: described blanket insulative layer (201) comprises silica and silicon nitride.
6. one according to claim 5 injects reinforced insulation grid bipolar transistor, it is characterized in that: described N-shaped is filled in polysilicon doped with phosphorus and arsenic.
7. one according to claim 6 injects reinforced insulation grid bipolar transistor, it is characterized in that: the width of described groove (202) is 0.5um-2um, and the degree of depth is 2um-8um, and the spacing between adjacent trenches (202) is 2um-8um; N-shaped emitter (105) dual-side of described H type relies on described blanket insulative layer (201), and the width of described dual-side is respectively 0.5um-3um, and the width between described H type dual-side is 0.5um-8um, and the degree of depth of described H type is 0.1um-1um.
8. one according to claim 7 injects reinforced insulation grid bipolar transistor, it is characterized in that: the impurity of described p-type active region (1041) is boron, and the degree of depth is 2um-8um; The impurity of described p-type inactive area (1042) is boron, and the degree of depth is 2um-8um; The impurity of described p-type collector electrode (101) is boron, and the degree of depth is 0.1um-2um; Described field comprises phosphorus, selenium, proton, sulphur, arsenic or defect doping by layer (102) impurity, and the degree of depth is 2um-20um.
9. one according to claim 2 injects reinforced insulation grid bipolar transistor, it is characterized in that: described n-type area of gently mixing is doped to phosphorus or arsenic, adopts gas to mix or middle photograph silicon chip.
10. one according to claim 9 injects reinforced insulation grid bipolar transistor, it is characterized in that: described p-type inactive area (1042) is or/and be provided with p-type emitter (106) in p-type active region (1041), and described p-type emitter (106) is attached most importance to doping p-type layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701362A (en) * | 2015-03-23 | 2015-06-10 | 东南大学 | Trench-isolated and lateral insulated-gate bipolar transistor |
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| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| CN103367413A (en) * | 2013-04-27 | 2013-10-23 | 中国东方电气集团有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN104078494A (en) * | 2013-03-29 | 2014-10-01 | 三星电机株式会社 | Power semiconductor device and method of fabricating the same |
| CN204144267U (en) * | 2014-11-05 | 2015-02-04 | 中国东方电气集团有限公司 | A kind of injection reinforced insulation grid bipolar transistor |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| CN104078494A (en) * | 2013-03-29 | 2014-10-01 | 三星电机株式会社 | Power semiconductor device and method of fabricating the same |
| CN103367413A (en) * | 2013-04-27 | 2013-10-23 | 中国东方电气集团有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
| CN204144267U (en) * | 2014-11-05 | 2015-02-04 | 中国东方电气集团有限公司 | A kind of injection reinforced insulation grid bipolar transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104701362A (en) * | 2015-03-23 | 2015-06-10 | 东南大学 | Trench-isolated and lateral insulated-gate bipolar transistor |
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| CN104332496B (en) | 2018-03-23 |
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