CN104299906A - Buried barrier voltage-dividing field effect transistor and production method thereof - Google Patents
Buried barrier voltage-dividing field effect transistor and production method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000004888 barrier function Effects 0.000 title abstract 6
- 238000002353 field-effect transistor method Methods 0.000 title description 4
- 230000005669 field effect Effects 0.000 claims abstract description 29
- 238000000407 epitaxy Methods 0.000 claims description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 29
- 238000003466 welding Methods 0.000 claims description 26
- 238000005036 potential barrier Methods 0.000 claims description 22
- 239000011521 glass Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000011159 matrix material Substances 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 239000006059 cover glass Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 75
- 239000004065 semiconductor Substances 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 210000002421 cell wall Anatomy 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The invention discloses a buried barrier voltage-dividing field effect transistor and a production method thereof. Depth to which trenches are dug downwards in an epitaxial layer is determined according to voltage withstand requirements, and voltage-dividing barriers are buried in advance; and the voltage-dividing barriers are connected with a source through network structures similar to gates. The high-voltage power field effect device is of a two-layer structure. When voltage (a non-conduction state) exists between the source and a drain, depletion layers (regions) are formed between the buried barriers, an effect of voltage withstand can be realized, and at the same time, depletion layers are formed between the above buried barriers and the gates of the trenches above; and therefore, capacitance between the gates and the drain can be greatly eliminated, charging time in gate switching can be significantly reduced (Qg can be greatly reduced), and the switching speed of the MOS transistor can be increased.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of buried type potential barrier dividing potential drop field effect transistor and production method thereof.
Background technology
Power field effect pipe (MOS) pipe, when back-pressure is higher, bears back-pressure by epitaxial loayer, and the resistivity of epitaxial loayer is comparatively large, and thickness is thicker, and cause epilayer resistance to account for the ratio of overall conducting resistance maximum, therefore, the effect improving epilayer resistance is the most obvious.At present, popular method is three-dimensional (3D) structure adopting similar super junction (Super Junction), as shown in Figure 1.The 3D structure of similar Super Junction can reduce epilayer resistance from two aspects: on the one hand, vertical and horizontal both direction is changed into from single vertical direction in the space charge region bearing back-pressure, to reduce the thickness of epitaxial loayer; On the other hand, when ensureing that metal-oxide-semiconductor cut-off time space charged region majority carrier can exhaust, improve epitaxial loayer carrier concentration, then during metal-oxide-semiconductor conducting, the resistivity of epitaxial loayer is just as far as possible little as far as possible.Just diminished at withstand voltage constant situation lower epi layer resistance or overall conducting resistance like this, during power MOS pipe work, heating is just few.But what current Super Junction and 3D structure all adopted mostly is single-layer type forming method, because production technology process difficulty is comparatively large, therefore only rest in foreign brand name producer and domestic minority supplier hand.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of buried type potential barrier dividing potential drop field effect transistor and production method thereof, and it while reaching the three-dimensional structure phase same-action of super junction, can reduce technology difficulty.
For solving the problem, the present invention is achieved by the following technical solutions:
A production method for buried type potential barrier dividing potential drop field effect transistor, comprises the steps:
(1) in N+ Grown N-type epitaxy layer;
(2) etch in the N-type epitaxy layer of growth and latticedly bury groove, and the N-type epitaxy layer of growth upper surface and bury in groove and grow silicon dioxide oxide layer;
(3) what have a silicon dioxide oxide layer in growth to bury in groove plated metal or polysilicon as good conductor, and from the edge of this power field effect pipe, this good conductor is connected to source electrode;
(4) with boron-phosphorosilicate glass BPSG fill and lead up deposit good conductor bury groove, corrode silicon dioxide oxide layer, in N+ types of flexure first N-type epitaxy layer, define buried layer thus;
(5) on buried layer, N-type epitaxy layer is regrowed;
(6) in the N-type epitaxy layer regrowed, etch latticed gate trench, and grow gate oxide in the upper surface and gate trench of the N-type epitaxy layer regrowed;
(7) deposit polycrystalline silicon gate in the gate trench of gate oxide is had in growth;
(8) by the N-type epitaxy layer upper surface that boron ion implantation regrows to grid surrounding, and boron ion diffuse knot is formed tagma P BODY;
(9) at the photomask surface source region figure in tagma, and by the tagma upper surface of boron ion implantation to grid surrounding, and knot formation source region is spread;
(10) at the upper surface deposition boron-phosphorosilicate glass BPSG in whole upper surface and grid, source region and tagma, on buried layer, working lining is formed thus;
(11) photoetching erode away contact hole on the boron-phosphorosilicate glass BPSG of working lining, and anti-carve out the grid of this power field effect pipe and the welding zone Pad of source electrode by the method for evaporation or splash-proofing sputtering metal aluminium;
(12) thinning N+ substrate, and the drain electrode forming power field effect pipe at thinning N+ substrate lower surface back of the body gold.
In such scheme, the source region figure of described step (9) is three-back-shaped.
In such scheme, the contact hole of described step (11) is matrix form distribution.
According to a kind of buried type potential barrier dividing potential drop field effect transistor prepared by said method, primarily of the back of the body layer gold, N+ substrate, buried layer, working lining and welding zone composition; Buried layer is arranged on the top of N+ substrate; Second N-type epitaxy layer is positioned at the top of buried layer, and welding zone is arranged on the top of the second N-type epitaxy layer; Back of the body layer gold is coated in the lower surface of N+ substrate;
Buried layer is made up of the first N-type epitaxy layer, good conductor, silicon dioxide oxide layer and buried layer cover glass; Latticed good conductor is all embedded in the first N-type epitaxy layer, and latticed good conductor distributes in trench shape matrix form in the first N-type epitaxy layer; The side of each good conductor and bottom surface are covered with silicon dioxide oxide layer, end face is covered with buried layer cover glass;
Working lining is made up of the second N-type epitaxy layer, polysilicon gate, gate oxide, tagma, source region and gate protection glass; The bottom of latticed polysilicon gate embeds in the second N-type epitaxy layer, and side and the bottom surface of polysilicon gate are covered with gate oxide, and the top of polysilicon gate is covered with gate protection glass; Tagma is arranged on the surrounding of upper, the polysilicon gate of the second N-type epitaxy layer; The top in each tagma is provided with source region;
Welding zone comprises the welding zone of grid and source electrode; Grid welding zone and Source bonding area are located at gate protection glass top, and are connected to polysilicon gate and source region by the contact hole of the grid and source electrode that are opened in welding zone bottom.
In such scheme, the bottom of described polysilicon gate embeds the top of the second N-type epitaxy layer.
In such scheme, a corresponding good conductor immediately below each polysilicon gate.
In such scheme, described source region is three-back-shaped.
In such scheme, described source contact openings is the distribution in matrix form on gate protection glass, and is drawn by Source bonding area.
In such scheme, described polysilicon gate connects together in the form of a grid, and is drawn from grid welding zone by gate contact hole after crossing terminator.
Compared with prior art, the present invention determines the degree of depth of downward grooving on epitaxial loayer according to withstand voltage needs, bury dividing potential drop potential barrier in advance, and be connected to source electrode with the network similar to grid, divide two-layer making high-voltage power fieldtron, when source electrode (Source) and drain electrode (Drain) have voltage (not conducting), form depletion layer (forming exhaustion region between) between the potential barrier of burying, play withstand voltage effect.Simultaneously, the grid (Gate) of burying dividing potential drop potential barrier and groove above in said structure forms depletion layer (forming exhaustion region between), significantly can eliminate the electric capacity between Gate and Drain, significantly can reduce the charging interval (Qg can significantly reduce) during Gate switch, thus improve the switching speed of metal-oxide-semiconductor.
Accompanying drawing explanation
Fig. 1 be exemplary power field effect transistor analyse and observe structure cell figure;
Fig. 2 be buried type potential barrier dividing potential drop power field effect pipe of the present invention analyse and observe structure cell figure;
Fig. 3-22 be each step of production method of buried type potential barrier dividing potential drop power field effect pipe of the present invention corresponding analyse and observe structure cell figure and lithography layout.
Number in the figure: 1, carry on the back layer gold; 2, N+ substrate; 3, buried layer; 3-1, the first N-type epitaxy layer; 3-2, good conductor; 3-3, silicon dioxide oxide layer; 3-4, bury cover glass; 4, working lining; 4-1, the second N-type epitaxy layer; 4-2, gate oxide; 4-3, polysilicon gate; 4-4, tagma; 4-5 source region; 4-6, gate protection glass; 5, welding zone; 5-1, contact hole.
Embodiment
A production method for buried type potential barrier dividing potential drop field effect transistor, comprises the steps:
1, on N+ substrate 2, N-type epitaxy layer is grown; See Fig. 3;
2, below metal-oxide-semiconductor grid, latticed groove is dug, and at cell wall growth silicon dioxide oxide layer 3-3; Namely
2.1, etch in the N-type epitaxy layer of growth and latticedly bury groove, wherein photoetching buries the layout patterns of groove as shown in Figure 4, and the structure after photoetching corrosion as shown in Figure 5;
2.2, the N-type epitaxy layer of growth upper surface and bury on the bottom surface of groove and sidewall and grow silicon dioxide oxide layer 3-3; See Fig. 6;
3, have in growth that silicon dioxide oxide layer 3-3's to bury in groove plated metal or polysilicon as good conductor 3-2, and from the edge of power field effect pipe, this good conductor 3-2 is connected to source electrode; See Fig. 7;
4, with boron-phosphorosilicate glass fill and lead up deposit good conductor 3-2 bury groove, corrode silicon dioxide oxide layer 3-3, above N+ substrate 2, define buried layer 3 in the first N-type epitaxy layer thus; See Fig. 8;
5, on buried layer 3, N-type epitaxy layer is regrowed; See Fig. 9;
6, dig gate trench, and in groove, grow gate oxide 4-2, deposit polycrystalline silicon gate 4-3Gate; Namely
6.1, in the N-type epitaxy layer regrowed, etch latticed gate trench, wherein the layout patterns of photoetched grid groove as shown in Figure 10, and the structure after photoetching corrosion as shown in figure 11;
6.2, at the upper surface of the N-type epitaxy layer regrowed and the sidewall of gate trench and bottom grown gate oxide 4-2; See Figure 12;
7, deposit polycrystalline silicon gate 4-3 in the gate trench of gate oxide 4-2 is had in growth; See Figure 13;
8, inject and advance metal-oxide-semiconductor tagma P4-4; Namely
8.1, by the N-type epitaxy layer upper surface that boron ion implantation regrows to grid surrounding, see Figure 14;
8.2 and by boron ion diffuse knot formed tagma P BODY4-4; See Figure 15;
9, locate with the method for photoetching and inject and advance source region 4-5N+; Namely
9.1, at the photomask surface source region 4-5 figure of tagma 4-4; This source region 4-5 layout patterns as shown in figure 16, for three-back-shaped;
9.2, by the tagma 4-4 upper surface of boron ion implantation to grid surrounding; See Figure 17;
9.3, spread knot and form source region N+4-5; See Figure 18;
10, at whole upper surface deposition boron-phosphorosilicate glass, protection grid; See Figure 19;
11, evaporation or splash-proofing sputtering metal aluminium anti-carve grid G ate and source S ource contact hole; Namely
11.1, lithography contact hole above working lining 4; As shown in figure 20, contact hole 5-1 is matrix form distribution to its litho pattern;
11.2, the grid of power field effect pipe and the welding zone 5 of source electrode is anti-carved out by the method for evaporation or splash-proofing sputtering metal aluminium; See Figure 21;
12, thinning N+ substrate 2, and the drain electrode forming power field effect pipe at thinning N+ substrate 2 lower surface back of the body gold, see Figure 22.
A kind of buried type potential barrier dividing potential drop field effect transistor made by aforementioned production method, as shown in Figure 2, forms primarily of the back of the body layer gold 1, N+ substrate 2, buried layer 3, working lining 4 and welding zone 5.Buried layer 3 is arranged on the top of N+ substrate 2.Second N-type epitaxy layer 4-1 is positioned at the top of buried layer 3, and welding zone 5 is arranged on the top of the second N-type epitaxy layer 4-1.Back of the body layer gold 1 is coated in the lower surface of N+ substrate 2.
Buried layer 3 is made up of the first N-type epitaxy layer 3-1, good conductor 3-2, silicon dioxide oxide layer 3-3 and buried layer cover glass 3-4.Latticed good conductor 3-2 is all embedded in the first N-type epitaxy layer 3-1, and latticed good conductor 3-2 distributes in trench shape matrix form in the first N-type epitaxy layer 3-1.Side and the bottom surface of each good conductor 3-2 are covered with silicon dioxide oxide layer 3-3, end face is covered with buried layer cover glass 3-4.
Working lining 4 is made up of the second N-type epitaxy layer 4-1, polysilicon gate 4-3, gate oxide 4-2, tagma 4-4, source region 4-5 and gate protection glass 4-6.The bottom of latticed polysilicon gate 4-3 embeds in the second N-type epitaxy layer 4-1.In the present invention, the bottom of polysilicon gate 4-3 embeds the top of the second N-type epitaxy layer 4-1.The side of polysilicon gate 4-3 and bottom surface are covered with gate oxide 4-2, and top is covered with gate protection glass 4-6.Tagma 4-4 is arranged on the top of the second N-type epitaxy layer 4-1, the surrounding of polysilicon gate 4-3.The top of each tagma 4-4 is provided with source region 4-5, and in the present invention, source region 4-5 is three-back-shaped.Described polysilicon gate 4-3 is identical with the shape of good conductor 3-2, although distribution on polysilicon gate 4-3 and good conductor 3-2 all in matrix distribution, its in vertical direction, without the need in strict accordance with one to one just to distribute mode.But in a preferred embodiment of the invention, an all corresponding good conductor 3-2 immediately below each polysilicon gate 4-3 and good conductor 3-2, namely in vertical direction, polysilicon gate 4-3 and good conductor 3-2 adopts one to one just to distribution mode.
Namely welding zone 5 comprises the welding zone of grid and source electrode, and grid welding zone and Source bonding area in welding zone 5 on gate protection glass 4-6, and are connected to polysilicon gate 4-3 and source region 4-5 by the contact hole 5-1 of the grid that is opened in welding zone bottom and source electrode.Described source contact openings 5-1 is the distribution in matrix form on gate protection glass 4-6, and is drawn by Source bonding area 5.Described polysilicon gate 4-3 connects together in the form of a grid, and is drawn from grid welding zone 5 by gate contact hole 5-1 after crossing terminator.
Claims (9)
1. a production method for buried type potential barrier dividing potential drop field effect transistor, is characterized in that comprising the steps:
(1) on N+ substrate (2), N-type epitaxy layer is grown;
(2) etch in the N-type epitaxy layer of growth and latticedly bury groove, and the N-type epitaxy layer of growth upper surface and bury in groove and grow silicon dioxide oxide layer (3-3);
(3) what have a silicon dioxide oxide layer (3-3) in growth to bury in groove plated metal or polysilicon as good conductor (3-2), and from the edge of this power field effect pipe, this good conductor (3-2) is connected to source electrode;
(4) with boron-phosphorosilicate glass fill and lead up deposit good conductor (3-2) bury groove, corrode silicon dioxide oxide layer (3-3), in the first N-type epitaxy layer of N+ substrate (2) top, define buried layer (3) thus;
(5) on buried layer (3), N-type epitaxy layer is regrowed;
(6) in the N-type epitaxy layer regrowed, etch latticed gate trench, and grow gate oxide (4-2) in the upper surface and gate trench of the N-type epitaxy layer regrowed;
(7) deposit polycrystalline silicon gate (4-3) in the gate trench of gate oxide (4-2) is had in growth;
(8) by the N-type epitaxy layer upper surface that boron ion implantation regrows to grid surrounding, and boron ion diffuse knot is formed tagma (4-4);
(9) at photomask surface source region (4-5) figure of tagma (4-4), and by tagma (4-4) upper surface of boron ion implantation to grid surrounding, and knot formation source region (4-5) is spread;
(10) at the upper surface deposition boron-phosphorosilicate glass of whole upper surface and grid, source region (4-5) and tagma (4-4), on buried layer (3), working lining (4) is formed thus;
(11) photoetching erode away contact hole (5-1) on the boron-phosphorosilicate glass of working lining (4), and anti-carve out the grid of this power field effect pipe and the welding zone (5) of source electrode by the method for evaporation or splash-proofing sputtering metal aluminium;
(12) thinning N+ substrate (2), and the drain electrode forming power field effect pipe at thinning N+ substrate (2) lower surface back of the body gold.
2. the production method of a kind of buried type potential barrier dividing potential drop field effect transistor according to claim 1, it is characterized in that, source region (4-5) figure of described step (9) is three-back-shaped.
3. the production method of a kind of buried type potential barrier dividing potential drop field effect transistor according to claim 1, is characterized in that, the contact hole of described step (11) is matrix form distribution.
4. a kind of buried type potential barrier dividing potential drop field effect transistor made by production method of buried type potential barrier dividing potential drop field effect transistor according to claim 1, is characterized in that: form primarily of back of the body layer gold (1), N+ substrate (2), buried layer (3), working lining (4) and welding zone (5); Buried layer (3) is arranged on the top of N+ substrate (2); Second N-type epitaxy layer (4-1) is positioned at the top of buried layer (3), and welding zone (5) is arranged on the top of the second N-type epitaxy layer (4-1); Back of the body layer gold (1) is coated in the lower surface of N+ substrate (2);
Buried layer (3) is made up of the first N-type epitaxy layer (3-1), good conductor (3-2), silicon dioxide oxide layer (3-3) and buried layer cover glass (3-4); Latticed good conductor (3-2) is all embedded in the first N-type epitaxy layer (3-1), and latticed good conductor (3-2) distributes in trench shape matrix form in the first N-type epitaxy layer (3-1); The side of each good conductor (3-2) and bottom surface are covered with silicon dioxide oxide layer (3-3), end face is covered with buried layer cover glass (3-4);
Working lining (4) is made up of the second N-type epitaxy layer (4-1), polysilicon gate (4-3), gate oxide (4-2), tagma (4-4), source region (4-5) and gate protection glass (4-6); The bottom of latticed polysilicon gate (4-3) embeds in the second N-type epitaxy layer (4-1), and the side of polysilicon gate (4-3) and bottom surface are covered with gate oxide (4-2), and the top of polysilicon gate (4-3) is covered with gate protection glass (4-6); Tagma (4-4) is arranged on the surrounding of upper, the polysilicon gate (4-3) of the second N-type epitaxy layer (4-1); The top in each tagma (4-4) is provided with source region (4-5);
Welding zone (5) comprises the welding zone of grid and source electrode; Grid welding zone and Source bonding area are located at gate protection glass (4-6) top, and are connected to polysilicon gate (4-3) and source region (4-5) by the contact hole (5-1) of the grid and source electrode that are opened in welding zone bottom.
5. require a kind of buried type potential barrier dividing potential drop field effect transistor described in 4 according to claim, it is characterized in that: the bottom of described polysilicon gate (4-3) embeds the top of the second N-type epitaxy layer (4-1).
6. require a kind of buried type potential barrier dividing potential drop field effect transistor described in 4 according to claim, it is characterized in that: a corresponding good conductor (3-2) immediately below each polysilicon gate (4-3).
7. require a kind of buried type potential barrier dividing potential drop field effect transistor described in 4 according to claim, it is characterized in that: described source region (4-5) is in three-back-shaped.
8. require a kind of buried type potential barrier dividing potential drop field effect transistor described in 4 according to claim, it is characterized in that: described source contact openings (5-1) in the upper distribution in matrix form of gate protection glass (4-6), and is drawn by Source bonding area (5).
9. require a kind of buried type potential barrier dividing potential drop field effect transistor described in 4 according to claim, it is characterized in that: described polysilicon gate (4-3) connects together in the form of a grid, and drawn from grid welding zone (5) by gate contact hole (5-1).
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| CN111834462A (en) * | 2018-06-28 | 2020-10-27 | 华为技术有限公司 | Semiconductor device and manufacturing method |
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| CN1767214A (en) * | 2004-10-29 | 2006-05-03 | 夏普株式会社 | Trench mosfet and method of manufacturing same |
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| KR20120126439A (en) * | 2011-05-11 | 2012-11-21 | 에스케이하이닉스 주식회사 | Sens-amp transistor of semiconductor device and manufacturing method of the same |
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| US20050242392A1 (en) * | 2004-04-30 | 2005-11-03 | Siliconix Incorporated | Super trench MOSFET including buried source electrode and method of fabricating the same |
| CN1767214A (en) * | 2004-10-29 | 2006-05-03 | 夏普株式会社 | Trench mosfet and method of manufacturing same |
| US20110169103A1 (en) * | 2010-01-12 | 2011-07-14 | Maxpower Semiconductor Inc. | Devices, components and methods combining trench field plates with immobile electrostatic charge |
| KR20120126439A (en) * | 2011-05-11 | 2012-11-21 | 에스케이하이닉스 주식회사 | Sens-amp transistor of semiconductor device and manufacturing method of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111834462A (en) * | 2018-06-28 | 2020-10-27 | 华为技术有限公司 | Semiconductor device and manufacturing method |
| CN111834462B (en) * | 2018-06-28 | 2024-02-09 | 华为技术有限公司 | Semiconductor device and manufacturing method |
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Effective date of registration: 20211229 Address after: 541004 floor 1, SMD new chip transistor production building, plot 8, information industry park, Guilin National High tech Zone, Qixing District, Guilin, Guangxi Zhuang Autonomous Region Patentee after: Guilin sizhuanggui Microelectronics Co.,Ltd. Address before: 541004 d-8, information industry park, Guilin National High tech Zone, Guangxi Zhuang Autonomous Region Patentee before: GUILIN STRONG MICROELECTRONICS Co.,Ltd. |