CN104157696B - Thin film transistor and preparation method thereof, as well as array baseplate and liquid crystal display device - Google Patents
Thin film transistor and preparation method thereof, as well as array baseplate and liquid crystal display device Download PDFInfo
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- CN104157696B CN104157696B CN201410340379.0A CN201410340379A CN104157696B CN 104157696 B CN104157696 B CN 104157696B CN 201410340379 A CN201410340379 A CN 201410340379A CN 104157696 B CN104157696 B CN 104157696B
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Abstract
The invention provides a thin film transistor and a preparation method thereof, as well as an array baseplate and a liquid crystal display device, relates to the technical field of display, can enable a preparation technology of the thin film transistor to be simpler, and can avoid generating photoinduced leakage current and hole leakage current. The thin film transistor comprises a gate electrode, an amorphous silicon layer and an ohmic contact layer which are arranged on an underlay baseplate in sequence; the size of the gate electrode is smaller than that of the amorphous silicon layer; on the basis, the thin film transistor further comprises a light blocking layer which is arranged between the amorphous silicon layer and the underlay baseplate, corresponding to the rest part, not being blocked by the gate electrode, of the amorphous silicon layer, and beyond the amorphous silicon layer. The invention is used for designing and manufacturing the thin film transistor, the array baseplate comprising the thin film transistor, and the liquid crystal display device comprising the array baseplate.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of thin film transistor (TFT) and preparation method, array base palte, liquid crystal
Display device.
Background technology
In liquid crystal indicator, the leakage current of thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) is to thin
The characteristic of film transistor can produce serious influence, and therefore, the leakage current all the time how reducing thin film transistor (TFT) is ability
The problem of field technique personnel research.
As shown in Figure 1, 2, 3, thin film transistor (TFT) 10 can include grid 101, the gate insulation being arranged on underlay substrate 100
Layer 102, amorphous silicon layer 103, ohmic contact layer 104 (n+ amorphous silicon layer) and source electrode 105 and drain electrode 106.
The structure of the thin film transistor (TFT) 10 of ideal type as shown in figure 1, wherein, the size one of grid 101 and amorphous silicon layer 103
Cause.Thus it is possible, on the one hand, when this thin film transistor (TFT) 10 is applied to array base palte, when this array base palte is applied to liquid crystal indicator,
Opaque grid 101 can prevent bottom backlight from irradiating amorphous silicon layer 103 and producing induced leakage current, on the other hand,
Grid 101 and the overlapping region of source electrode 105 and drain electrode 106, the hole accumulation layer in amorphous silicon layer 103 and ohmic contact layer 104
Form PN junction, can prevent the hole in hole accumulation layer from flowing in source electrode 105 and drain electrode 106 or in source electrode 105 and drain electrode 106
Electronics flow into amorphous silicon layer 103 hole accumulation layer in and produce hole leakage current.
However, situation as shown in Figures 2 and 3 often occurs in actual process.Wherein, Fig. 2 show grid 101
It is smaller in size than the situation of amorphous silicon layer 103 size, because grid 101 can not block amorphous silicon layer 103 completely, can lead to the bottom of from
The light of portion's backlight shines amorphous silicon layer 103, thus producing induced leakage current.It is illustrated in figure 3 grid 101 size and be more than amorphous
The situation of silicon layer 103 size, because grid 101 is still had with source electrode 105 and drain electrode 106 in the part beyond amorphous silicon layer 103
Overlap, and it is provided only with gate insulation layer 102 and source electrode between grid 101 and source electrode 105 and drain electrode 10 in this overlapping region
105 directly contact so that hole accumulation layer in amorphous silicon layer 103 and source electrode 105 and leak with drain electrode 106 with amorphous silicon layer 103
Lead to hole to flow in source electrode 105 and drain electrode 106 or source electrode 105 and drain electrode 106 between pole 106 due to the presence not having PN junction
In electronics flow in the hole accumulation layer of amorphous silicon layer 103, produce hole leakage current.
Content of the invention
Embodiments of the invention provide a kind of thin film transistor (TFT) and preparation method, array base palte, liquid crystal indicator, permissible
Make the preparation technology of thin film transistor (TFT) more simple, and induced leakage current and the generation of hole leakage current can be avoided.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
On the one hand, provide a kind of thin film transistor (TFT), including the grid being successively set on underlay substrate, amorphous silicon layer and Europe
Nurse contact layer, the size being smaller in size than described amorphous silicon layer of described grid；On this basis, described thin film transistor (TFT) also wraps
Include：It is arranged on the light blocking layer between described amorphous silicon layer and described underlay substrate, described light blocking layer is not blocked by described grid with
Amorphous silicon layer remainder corresponding and exceed described amorphous silicon layer.
Preferably, described light blocking layer is arranged between described underlay substrate and described grid, and described light blocking layer also with institute
State grid to correspond to.
Further, the material of described light blocking layer is opaque resin.
Preferably, described light blocking layer and described grid with layer and are integrated；Wherein, described light blocking layer is away from described
The material on the surface of underlay substrate be described grid material is aoxidized after obtain, the material of the remainder of described light blocking layer
Identical with described grid material.
On the other hand, also provide a kind of array base palte, including the thin film transistor (TFT) described in any of the above-described.
Another further aspect, also provides a kind of liquid crystal indicator, including above-mentioned array base palte.
Another aspect, also provides a kind of preparation method of thin film transistor (TFT), including sequentially form on underlay substrate grid,
Amorphous silicon layer and ohmic contact layer, the size being smaller in size than described amorphous silicon layer of described grid；On this basis, methods described
Also include：Form light blocking layer between described amorphous silicon layer and described underlay substrate, described light blocking layer is not hidden by described grid with
The remainder of the amorphous silicon layer of gear is corresponding and exceeds described amorphous silicon layer.
Preferably, described light blocking layer is formed between described underlay substrate and described grid, and described light blocking layer also with institute
State grid to correspond to.
Further, the material of described light blocking layer is opaque resin；On this basis, described grid, described gear are formed
Photosphere specifically includes：
The layer film that is in the light, grid metal film are sequentially formed on underlay substrate, and light is formed on described grid metal film
Photoresist；Using normal masks plate, the substrate being formed with described photoresist is exposed, forms photoresist after development and be fully retained
Part and photoresist remove part completely；Wherein, described photoresist is fully retained the size more than described grid for the size of part,
And described photoresist is fully retained part and described grid is completely covered, described photoresist removes partly correspond to other regions completely；
Remove partly corresponding described grid metal film completely using wet-etching technology pair and described photoresist to perform etching, form institute
State grid；Part is fully retained as mask with described photoresist, using dry etch process, the described layer film that is in the light is carved
Erosion, forms described light blocking layer；The photoresist that described photoresist is fully retained part is removed using stripping technology.
Preferably, described light blocking layer and described grid with layer and are integrated；On this basis, described grid are formed
Pole, described light blocking layer specifically include：
Underlay substrate forms grid metal film, and photoresist is formed on described grid metal film；Using half rank or
Gray-tone mask plate (GTM) is exposed to the substrate being formed with described photoresist, forms photoresist part, photoetching are fully retained after development
Glue half member-retaining portion and photoresist remove part completely；Wherein, described photoresist is fully retained the area partly corresponding to described grid
Domain, the region of the corresponding described light blocking layer of described photoresist half member-retaining portion, described photoresist removes partly correspond to other areas completely
Domain；The described grid metal film that described photoresist removes part completely is removed using etching technics；Using plasma is to described
Photoresist half member-retaining portion is bombarded, and removes the photoresist of described photoresist half member-retaining portion；And adjust plasma parameter,
The surface oxidation of described grid metal film corresponding with described photoresist half member-retaining portion is made to form described light blocking layer, with described light
Photoresist is fully retained partly corresponding described grid metal film and forms grid, removes described photoresist simultaneously and part is fully retained
Photoresist.
Embodiments of the invention provide a kind of thin film transistor (TFT) and preparation method, array base palte, liquid crystal indicator, and this is thin
Film transistor includes grid, amorphous silicon layer and the ohmic contact layer being successively set on underlay substrate, and the size of described grid is little
Size in described amorphous silicon layer；On this basis, described thin film transistor (TFT) also includes：Be arranged on described amorphous silicon layer with described
Light blocking layer between underlay substrate, described light blocking layer is corresponding and super with the remainder of the amorphous silicon layer not blocked by described grid
Go out described amorphous silicon layer.
With respect to the process complexity preparing the grid of consistent size and the thin film transistor (TFT) of amorphous silicon layer, the present invention is implemented
Thin film transistor (TFT) in the array base palte that example provides is because the size being smaller in size than described amorphous silicon layer of described grid is so that make
Standby technique is more simple；On this basis, on the one hand, due to the size being smaller in size than described amorphous silicon layer of described grid, make
Obtain the overlapping region in described grid and described source electrode and drain electrode, the hole accumulation layer in amorphous silicon layer and ohmic contact layer are formed
PN junction, thus avoid the generation of hole leakage current；On the other hand, effect is shared by described light blocking layer and described grid, permissible
Stop that illumination is mapped to described amorphous silicon layer, thus avoiding the generation of induced leakage current.
Brief description
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Have technology description in required use accompanying drawing be briefly described it should be apparent that, drawings in the following description be only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, acceptable
Other accompanying drawings are obtained according to these accompanying drawings.
A kind of structural representation of ideal type thin film transistor (TFT) for providing in prior art for the Fig. 1；
Fig. 2 is less than the structural representation of the thin film transistor (TFT) of amorphous silicon layer size for the grid size providing in prior art
Figure；
Fig. 3 is more than the structural representation of the thin film transistor (TFT) of amorphous silicon layer size for the grid size providing in prior art
Figure；
Fig. 4 is a kind of structural representation one of thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 5 is a kind of structural representation two of thin film transistor (TFT) provided in an embodiment of the present invention；
Fig. 6 is a kind of structural representation one of array base palte provided in an embodiment of the present invention；
Fig. 7 is a kind of structural representation two of array base palte provided in an embodiment of the present invention；
Fig. 8 a-8e is a kind of process schematic one forming grid and light blocking layer provided in an embodiment of the present invention；
Fig. 9 a-9d is a kind of process schematic two forming grid and light blocking layer provided in an embodiment of the present invention.
Reference：
10- thin film transistor (TFT)；100- underlay substrate；101- grid；101a- grid metal film；102- gate insulation layer；103-
Amorphous silicon layer；104- ohmic contact layer；105- source electrode；106- drains；107- light blocking layer；107a- is in the light layer film；20- pixel
Electrode；30- public electrode；40- photoresist；401- photoresist is fully retained part；402- photoresist removes part completely；403-
Photoresist half member-retaining portion.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of protection of the invention.
Embodiments provide a kind of thin film transistor (TFT) 10, as shown in Figure 4 and Figure 5, this thin film transistor (TFT) 10 includes：
It is successively set on grid 101 on underlay substrate 100, amorphous silicon layer 103 and ohmic contact layer 104, the size of described grid 101
Size less than described amorphous silicon layer 103；On this basis, described thin film transistor (TFT) 10 also includes：It is arranged on described non-crystalline silicon
Layer 103 and described underlay substrate 100 between light blocking layer 107, described light blocking layer 107 with not by described grid 101 block non-
The remainder of crystal silicon layer is corresponding and exceeds described amorphous silicon layer 103.
Certainly, described thin film transistor (TFT) 10 also includes：It is arranged between described grid 101 and described amorphous silicon layer 103
Gate insulation layer 102, be arranged on described ohmic contact layer 104 away from the source electrode 105 of underlay substrate 100 side and drain electrode 106.
It should be noted that first, the size being smaller in size than described amorphous silicon layer 103 of described grid 101, as：Institute
State grid 101 and be smaller in size than projection on underlay substrate 100 for the described amorphous silicon layer 103 in the projection on underlay substrate 100
Size.
Certainly, it will be recognized by those skilled in the art that described amorphous silicon layer 103 is exactly semiconductor active layer, and described grid
Pole 101 and described amorphous silicon layer 103 are completely corresponding, that is, projection on underlay substrate 100 for the described grid 101 is complete
Covered by projection on underlay substrate 100 for the described amorphous silicon layer 103.
Second, described light blocking layer 103 corresponding with the remainder of the amorphous silicon layer 103 not blocked by described grid 101 and
Beyond described amorphous silicon layer 103, as：Described light blocking layer 103 removes and includes and the amorphous silicon layer not blocked by described grid 101
101 remainder is corresponding partly outer, also includes exceeding the part of described amorphous silicon layer 103.
3rd, due to the size being smaller in size than described amorphous silicon layer 103 of described grid 101, in this case when described
Thin film transistor (TFT) 10 is applied to array base palte, and when this array base palte is applied to liquid crystal indicator, certainly will lead to from bottom
The illumination of backlight is mapped to amorphous silicon layer 103 and produces induced leakage current, and an object of the present invention is to solve photic electric leakage
The problem of stream, therefore, light blocking layer 107 and its set location that those skilled in the art mention from the embodiment of the present invention, just
It will be appreciated that arranging one of purpose of described light blocking layer 107 is to be mapped to not by grid from the illumination of bottom backlight for stop
The remainder of the amorphous silicon layer 103 that 101 block, thus come to avoid produce induced leakage current, therefore, described light blocking layer 107
Material should be can light absorbing opaque material.
On this basis, include and the amorphous silicon layer 101 not blocked by described grid 101 because described light blocking layer 107 removes
Remainder corresponding partly outer, also include exceeding the part of described amorphous silicon layer 103, in the case, if described be in the light
Layer 107 is conductive and if contact with described grid 101, is equivalent to the size extending grid 101 and makes the grid after extension
101 sizes are more than described amorphous silicon layer 103, if based between light blocking layer this described 107 and described source electrode 105 and drain electrode 106
Alternating floor gate insulation layer 102, then can lead to the generation of hole leakage current, therefore, described light blocking layer 103 in the embodiment of the present invention
If conductor material, and in the case that it is contacted with grid 101, also need to be in described light blocking layer 103 and described source electrode 105 and leakage
Form the insulating barrier for intercepting electric field between pole 106.
Embodiments provide a kind of thin film transistor (TFT) 10, including：It is successively set on the grid on underlay substrate 100
101st, amorphous silicon layer 103 and ohmic contact layer 104, the size being smaller in size than described amorphous silicon layer 103 of described grid 101；?
On the basis of this, described thin film transistor (TFT) 10 also includes：It is arranged between described amorphous silicon layer 103 and described underlay substrate 100
Light blocking layer 107, described light blocking layer 107 is corresponding with the remainder of the amorphous silicon layer not blocked by described grid 101 and exceeds institute
State amorphous silicon layer 103.
So, with respect to the grid 101 of preparation consistent size and the process complexity of amorphous silicon layer 103, the present invention is implemented
Example is smaller in size than the size of described amorphous silicon layer 103 so that preparation technology is more simple due to described grid 101；In this base
On plinth, on the one hand, because the size being smaller in size than described amorphous silicon layer 103 of described grid 101 is so that in described grid 101
With the overlapping region of described source electrode 105 and drain electrode 106, the hole accumulation layer in amorphous silicon layer 103 formed with ohmic contact layer 104
PN junction, thus avoid the generation of hole leakage current；On the other hand, shared by described light blocking layer 107 and described grid 101 and make
With stopping that illumination is mapped to described amorphous silicon layer 103, thus avoiding the generation of induced leakage current.
Preferably, as shown in figure 4, described light blocking layer 107 is arranged between described underlay substrate 101 and described grid 101,
And described light blocking layer 107 is also corresponding with described grid 101.
I.e.：The size of described light blocking layer 107 is more than the size of described amorphous silicon layer 103, and described light blocking layer 107 is described
Projection on underlay substrate 100 is completely covered projection on described underlay substrate 100 for the described amorphous silicon layer 103.
On this basis, if the material of described light blocking layer 107 be insulant, described light blocking layer 107 can with described
Grid 101 directly contact；If the material of described light blocking layer 107 is conductor material, described light blocking layer 107 and described grid 101
Between a layer insulating can be set, specifically can be configured according to practical situation, here does not limit.
So, only additionally need to make one layer of light blocking layer 107, and make described light blocking layer 107 when preparing thin film transistor (TFT)
Size be more than described amorphous silicon layer 103 size, just can avoid the generation of induced leakage current and hole leakage current, simultaneously so that
Preparation technology is relatively easy.
Further, the material of described light blocking layer 107 is opaque resin.
Described opaque resin can be for example and make black matrix identical material.
Preferably, as shown in figure 5, described light blocking layer 107 and is integrated with layer with described grid 101；Wherein, institute
State the surface away from described underlay substrate 100 for the light blocking layer 107 material be described grid 101 material is aoxidized after obtain,
The material of remainder of described light blocking layer 107 is identical with described grid 101 material.
Here, the integral structure of described light blocking layer 107 and described grid 101 can for example be realized in the following way,
I.e.：When preparing thin film transistor (TFT), it is initially formed, by patterning processes, the grid metal that size is more than amorphous silicon layer 103 size
Layer, this barrier metal layer includes to be formed being smaller in size than the grid 101 of amorphous silicon layer 103 size and being located at around grid 101
Light blocking layer 107 to be formed, then makes the grid material surface oxidation in described light blocking layer 107 region by related process, thus
Form light blocking layer 107, and make not oxidized barrier metal layer part form described grid 101.
It should be noted that first, when selecting grid 101 material, it is nonconducting grid 101 material after answering selective oxidation
Material.
Although the bottom of the second light blocking layer 107 is not oxidized part still contacting with grid 101, due to being in the light
The insulating barrier being formed after the surface of layer 107 is oxidized can intercept electric field, therefore, still can avoid the product of hole leakage current
Raw.
So, only described light blocking layer 107 be need to form forming grid 101 simultaneously, induced leakage current and sky just can be avoided
The generation of cave leakage current, and also the increase of patterning processes and the increase of thin film transistor (TFT) 10 integral thickness can be avoided.
The embodiment of the present invention additionally provides a kind of array base palte, as shown in fig. 6, this array base palte includes above-mentioned thin film crystalline substance
Body pipe 10, can also include the pixel electrode 20 electrically connecting with the drain electrode 106 of described thin film transistor (TFT) 10 certainly.
With respect to the process complexity preparing the grid 101 of consistent size and the thin film transistor (TFT) of amorphous silicon layer 103, this
Thin film transistor (TFT) 10 in the array base palte that bright embodiment provides is smaller in size than described amorphous silicon layer due to described grid 101
103 size is so that preparation technology is more simple；On this basis, on the one hand, institute is smaller in size than by described grid 101
State the size of amorphous silicon layer 103 so that described grid 101 and described source electrode 105 and drain 106 overlapping region, non-crystalline silicon
Hole accumulation layer in layer 103 forms PN junction with ohmic contact layer 104, thus avoiding the generation of hole leakage current；The opposing party
Face, shares effect by described light blocking layer 107 and described grid 101, can stop that illumination is mapped to described amorphous silicon layer 103, thus
Avoid the generation of induced leakage current.
On this basis, as shown in fig. 7, described array base palte can also include public electrode 30.
Wherein, array base palte provided in an embodiment of the present invention goes for Senior super dimension field switch technology (Advanced
Super Dimensional Switching, abbreviation ADS) type liquid crystal indicator production.Wherein, advanced super dimension switch
Technology, its core technology characteristic is described as：By electric field and gap electrode produced by gap electrode edge in same plane
The electric field formation multi-dimensional electric field that layer is produced with plate electrode interlayer, makes in liquid crystal cell between gap electrode, all directly over electrode takes
Rotation can be produced to liquid crystal molecule, thus improve liquid crystal work efficiency and increasing light transmission efficiency.Senior super Wei Chang turns
The technology of changing can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide viewing angle, Gao Kai
The advantages of mouth rate, low aberration, ripple without water of compaction (Push Mura).
The embodiment of the present invention additionally provides a kind of liquid crystal indicator, including above-mentioned array base palte.
Herein, display device described in the embodiment of the present invention can be specifically liquid crystal display, LCD TV, DPF,
Mobile phone, panel computer etc. have product or the part of any display function.
The embodiment of the present invention additionally provides a kind of preparation method of thin film transistor (TFT) 10, with reference to shown in Fig. 4 and Fig. 5, the party
Method includes sequentially forming grid 101, amorphous silicon layer 103 and ohmic contact layer 104 on underlay substrate 100, described grid 101
It is smaller in size than the size of described amorphous silicon layer 103；On this basis, methods described also includes：In described amorphous silicon layer 103 and institute
State formation light blocking layer 107, described light blocking layer 107 and the amorphous silicon layer not blocked by described grid 101 between underlay substrate 100
Remainder is corresponding and exceeds described amorphous silicon layer 103.
Certainly, methods described also includes：Formation gate insulation layer between described grid 101 and described amorphous silicon layer 103
102nd, source electrode 105 and drain electrode 106 are formed in described ohmic contact layer 104 away from underlay substrate 100 side.
With respect to the process complexity of grid 101 and the amorphous silicon layer 103 of preparation consistent size, the embodiment of the present invention due to
Described grid 101 be smaller in size than the size of described amorphous silicon layer 103 so that preparation technology is more simple；On this basis, one
Aspect, because the size being smaller in size than described amorphous silicon layer 103 of described grid 101 is so that in described grid 101 and described source
Pole 105 and the overlapping region of drain electrode 106, the hole accumulation layer in amorphous silicon layer 103 forms PN junction with ohmic contact layer 104, from
And avoid the generation of hole leakage current；On the other hand, effect is shared by described light blocking layer 107 and described grid 101, can hinder
It is in the light and is irradiated to described amorphous silicon layer 103, thus avoiding the generation of induced leakage current.
Preferably, with reference to shown in Fig. 4, described light blocking layer 107 be formed at described underlay substrate 100 and described grid 101 it
Between, and described light blocking layer 107 is also corresponding with described grid 101.
I.e.：The size of described light blocking layer 107 is more than the size of described amorphous silicon layer 103, and described light blocking layer 107 is described
Projection on underlay substrate 100 is completely covered projection on described underlay substrate 100 for the described amorphous silicon layer 103.
On this basis, if the material of described light blocking layer 107 be insulant, described light blocking layer 107 can with described
Grid 101 directly contact；If the material of described light blocking layer 107 is conductor material, described light blocking layer 107 and described grid 101
Between can form a layer insulating, specifically can be configured according to practical situation, here does not limit.
So, only additionally need to make one layer of light blocking layer 107, and make described light blocking layer 107 when preparing thin film transistor (TFT)
Size be more than described amorphous silicon layer 103 size, just can avoid the generation of induced leakage current and hole leakage current, simultaneously so that
Preparation technology is relatively easy.
Further, the material of preferably described light blocking layer 107 is opaque resin, that is,：Can on underlay substrate 100 first
Form described light blocking layer 107, then form described grid 101 above light blocking layer 107, and described light blocking layer 107 and described grid
Pole 101 contacts.
Specifically, form described grid 101, described light blocking layer 107 comprises the steps：
S101, as shown in Figure 8 a, sequentially forms, on underlay substrate 100, be in the light layer film 107a, grid metal film 101a,
And photoresist 40 is formed on described grid metal film 101a.
S102, as shown in Figure 8 b, is exposed to the substrate being formed with described photoresist 40 using normal masks plate, development
Formation photoresist is fully retained part 401 and photoresist removes part 402 completely afterwards；Wherein, described photoresist is fully retained portion
Points 401 size is more than the size of described grid 101, and described photoresist is fully retained part 401 and described grid is completely covered
101, described photoresist removes part 402 completely and corresponds to other regions.
S103, as shown in Figure 8 c, removes the corresponding institute of part 402 completely using wet-etching technology pair and described photoresist
State grid metal film 101a to perform etching, form described grid 101.
Adopt wet-etching technology in this step, be because that wet etching has anisotropy, do not only have vertical etch,
Also have horizontal undercutting, remove the corresponding described grid metal film of part 402 such that it is able to not only etching completely with described photoresist
101a, can also etch grid metal film 101a that part 401 lower section is fully retained positioned at described photoresist, and then form size
The described grid 101 of part 401 is fully retained less than described photoresist.
It should be noted that by the etching parameters controlling wet etching, can controlling and protect completely positioned at described photoresist
Stay the degree that grid metal film 101a of part 401 lower section is etched, thus controlling the size of the grid 101 of formation.
S104, as shown in figure 8d, is fully retained part 401 as mask with described photoresist, using dry etch process pair
The described layer film 107a that is in the light performs etching, and forms described light blocking layer 107.
Adopt dry etch process in this step, be because that dry etching only can have vertical etch, thus only will be with
Described photoresist removes the corresponding layer film 107a that is in the light of part 402 completely and etches away.
It should be noted that the size of part 401 and the size one of described light blocking layer 107 are fully retained due to photoresist
Cause, and the purpose forming described light blocking layer 107 is to stop that illumination is mapped to remaining of the amorphous silicon layer 103 not blocked by grid 101
Part, therefore, it will be recognized by those skilled in the art that in above-mentioned steps S102, be fully retained portion controlling described photoresist
When points 401 size is more than the size of described grid 101, need to consider to make the size of amorphous silicon layer 103 that is subsequently formed between
The size of described grid 101 and described photoresist are fully retained between the size of part 401.
S105, as figure 8 e shows, removes, using stripping technology, the photoresist that described photoresist is fully retained part.
On this basis, with reference to shown in Fig. 4, when forming described amorphous silicon layer 103, its size only need to be made to be more than described grid
The size of pole 101 and the size less than described light blocking layer 107.
By above-mentioned steps S101-S105, only can pass through patterning processes, just can form described light blocking layer 107 He
Described grid 101.
Preferably, described light blocking layer 107 and described grid 101 with layer and are integrated.On this basis, form institute
State grid 101, described light blocking layer 107 specifically may include steps of：
S201, as illustrated in fig. 9, forms grid metal film 101a on underlay substrate 100, and in described grid metal film
Photoresist 40 is formed on 101a.
S202, as shown in figure 9b, is exposed to the substrate being formed with described photoresist using half rank or gray-tone mask plate (GTM),
After development, formation photoresist is fully retained part 401, photoresist half member-retaining portion 403 and photoresist and removes part 402 completely；Its
In, described photoresist is fully retained the region of the corresponding described grid 101 of part 401, and described photoresist half member-retaining portion 403 is corresponding
The region of described light blocking layer 107, described photoresist removes part 402 completely and corresponds to other regions.
It should be noted that being to stop that illumination is mapped to not blocked by grid 101 due to forming the purpose of described light blocking layer 107
Amorphous silicon layer 103 remainder, therefore, it will be recognized by those skilled in the art that setting photoresist half member-retaining portion 403
Size when, need to consider to make the size of amorphous silicon layer 103 that is subsequently formed between the size of described grid 101 and described grid
Between 101 and the overall dimensions of described light blocking layer 107.
S203, as is shown in fig. 9 c, using etching technics remove described photoresist remove completely part described grid metal thin
Film 101a.
S204, as shown in figure 9d, using plasma bombards to described photoresist half member-retaining portion 403, removes institute
State the photoresist of photoresist half member-retaining portion 403；And adjust plasma parameter, make and described photoresist half member-retaining portion 403
The surface oxidation of corresponding described grid metal film 101a forms described light blocking layer 107, part is fully retained with described photoresist
401 corresponding described grid metal films 101a form grid 101, remove the light that described photoresist is fully retained part 401 simultaneously
Photoresist.
Here, Ar/O can for example be used2, or Ar/O2/N2Plasma is carried out to described photoresist half member-retaining portion 403
Two step bombardments.The first step quickly bombards the photoresist removing described photoresist half member-retaining portion 403, second step reduce above-mentioned grade from
O2 content in daughter, slow bombardment so that with corresponding described grid metal film 101a of described photoresist half member-retaining portion 403
Surface oxidation form described light blocking layer 107, and remove the photoresist that described photoresist is fully retained part 401 simultaneously.
Wherein, oxidation depth for example can reach 50～80nm.
It should be noted that, although the bottom of light blocking layer 107 is not oxidized part still contacting with grid 101, but
Because the oxidized rear insulating barrier being formed in the surface of light blocking layer 107 can intercept electric field, therefore, hole still can be avoided to leak electricity
The generation of stream.
On this basis, with reference to shown in Fig. 5, when forming described amorphous silicon layer 103, its size only need to be made to be more than described grid
The size of pole 101 and the overall dimensions less than described grid 101 and described light blocking layer 107.
By above-mentioned steps S201-S204, only can pass through patterning processes, just can form described light blocking layer 107 He
Described grid 101.
The above, the only specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, and any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, all should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by described scope of the claims.
Claims (4)
1. a kind of thin film transistor (TFT), including the grid being successively set on underlay substrate, amorphous silicon layer and ohmic contact layer, it is special
Levy and be, the size being smaller in size than described amorphous silicon layer of described grid；
Described thin film transistor (TFT) also includes：It is arranged on the light blocking layer between described amorphous silicon layer and described underlay substrate, described gear
Photosphere is corresponding with the remainder of the amorphous silicon layer not blocked by described grid and exceeds described amorphous silicon layer；
Described light blocking layer and is integrated with layer with described grid；Wherein, described light blocking layer is away from described underlay substrate
The material on surface be described grid material is aoxidized after obtain, the material of the remainder of described light blocking layer and described grid
Material is identical.
2. a kind of array base palte is it is characterised in that include the thin film transistor (TFT) described in claim 1.
3. a kind of liquid crystal indicator is it is characterised in that include the array base palte described in claim 2.
4. a kind of preparation method of thin film transistor (TFT), connects including sequentially forming grid, amorphous silicon layer and ohm on underlay substrate
Contact layer is it is characterised in that the size being smaller in size than described amorphous silicon layer of described grid；
Methods described also includes：Between described amorphous silicon layer and described underlay substrate formed light blocking layer, described light blocking layer with not
The remainder of the amorphous silicon layer being blocked by described grid is corresponding and exceeds described amorphous silicon layer；
Wherein, described light blocking layer and described grid with layer and are integrated；
Form described grid, described light blocking layer specifically includes：
Underlay substrate forms grid metal film, and photoresist is formed on described grid metal film；
Using half rank or gray-tone mask plate (GTM), the substrate being formed with described photoresist is exposed, forms photoresist after development complete
Member-retaining portion, photoresist half member-retaining portion and photoresist remove part completely；Wherein, described photoresist is fully retained and partly corresponds to
The region of described grid, the region of the corresponding described light blocking layer of described photoresist half member-retaining portion, described photoresist removal portion completely
Divide other regions corresponding；
The described grid metal film that described photoresist removes part completely is removed using etching technics；
Using plasma bombards to described photoresist half member-retaining portion, removes the photoetching of described photoresist half member-retaining portion
Glue；And adjust plasma parameter, make the surface oxidation of described grid metal film corresponding with described photoresist half member-retaining portion
Form described light blocking layer, partly corresponding described grid metal film is fully retained with described photoresist and forms grid, remove simultaneously
Described photoresist is fully retained the photoresist of part.
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| CN104992948B (en) * | 2015-06-03 | 2018-07-06 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT), array substrate and preparation method thereof |
| US20200212227A1 (en) * | 2016-08-17 | 2020-07-02 | Boe Technology Group Co., Ltd. | Thin film transistor, manufacturing method thereof, array substrate, display device |
| CN107768306A (en) * | 2017-10-12 | 2018-03-06 | 惠科股份有限公司 | Display panel and method for manufacturing the same |
| CN108022875B (en) * | 2017-11-30 | 2020-08-28 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of thin film transistor and manufacturing method of array substrate |
| CN108447873A (en) * | 2018-03-19 | 2018-08-24 | 武汉华星光电技术有限公司 | A kind of array substrate and preparation method |
| CN108682693A (en) * | 2018-05-28 | 2018-10-19 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor (TFT) |
| CN109494257B (en) * | 2018-10-26 | 2021-01-01 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN112490282B (en) | 2020-12-03 | 2022-07-12 | Tcl华星光电技术有限公司 | Thin film transistor and preparation method thereof |
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| CN103474430B (en) * | 2012-06-07 | 2016-08-17 | 群康科技(深圳)有限公司 | Thin film transistor base plate and preparation method thereof and display |
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