CN104124272B - Integrated non-polar GaN nano wire HEMT and preparation method thereof - Google Patents
Integrated non-polar GaN nano wire HEMT and preparation method thereof Download PDFInfo
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- CN104124272B CN104124272B CN201410334651.4A CN201410334651A CN104124272B CN 104124272 B CN104124272 B CN 104124272B CN 201410334651 A CN201410334651 A CN 201410334651A CN 104124272 B CN104124272 B CN 104124272B
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- 239000002070 nanowire Substances 0.000 title claims abstract description 154
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 96
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 62
- 239000000463 material Substances 0.000 claims description 43
- 239000000377 silicon dioxide Substances 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 239000003989 dielectric material Substances 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000012545 processing Methods 0.000 abstract description 4
- 239000002131 composite material Substances 0.000 abstract 1
- 238000013386 optimize process Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 27
- 229910052581 Si3N4 Inorganic materials 0.000 description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 19
- 238000000407 epitaxy Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 11
- 229910002704 AlGaN Inorganic materials 0.000 description 10
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- 238000010276 construction Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012620 biological material Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses integrated non-polar GaN nano wire HEMT and preparation method thereof, insulating medium layer including substrate and on substrate, multiple spaced grooves are etched with the insulating medium layer, growth has heterojunction nano-wire respectively in the multiple groove, source electrode and drain electrode are formed with the insulating medium layer, the source electrode and drain electrode are respectively positioned at the two ends of heterojunction nano-wire and with being connected respectively with each heterojunction nano-wire, grid is formed between the source electrode and drain electrode, gate dielectric layer is provided between the grid and heterojunction nano-wire.Epitaxial growth and the preparation organic unity of device can be enormously simplify processing step, optimize process by the present invention.The present invention solve current nano-wire transistor using solution dilute coated come uncontrollability and randomness, effectively increase nano-wire transistor prepare success rate.It the composite can be widely applied to semiconductor applications.
Description
Technical field
Moved the present invention relates to technical field of semiconductor device, more particularly to a kind of integrated high electronics of non-polar GaN nano wire
Shifting rate transistor and preparation method thereof.
Background technology
Microelectronic integrated circuit and key factor and core technology that technology is hyundai electronicses information technology fast development.With
The development of microelectronics integrated technology, the integrated level more and more higher of the microelectronic component based on Si materials, the feature chi of device
It is very little to require less and less.When minimum feature size is 10nm, reach the physics limit of microelectronic component, More's law no longer into
It is vertical.Because reaching the Nanosemiconductor Device of this size, its working mechanism, material and technology are all different from micro- electricity
Sub- device.
Nanometer electronic device is referred to as third generation electronic device, and it makes optoelectronic information transmission, storage, processing, computing and display
In terms of performance greatly improve, it is integrated to constitute VHD, is following personal computer, high-performance computer and automation
Basis, will be the primary clustering of the functional instrument of information-intensive society.
Development Nanosemiconductor Device has two kinds of approach：One is by the inorganic semiconductor based on Si, Ge, GaAs and GaN etc.
Device size is small, i.e. technology " from top to bottom "；Two be by give inorganic semiconductor atom, molecule and organic polymer and
The function element size of biologic material assembling is become heavy, i.e. technology " from bottom to top ".But " from top to bottom " technology is to be carved
The condition limitations such as etching technique resolution ratio, the edge damage that brings of processing and impurity pollution, cause the pre- of the performance of device and theory
Time value differs greatly.And with semiconductor strain self assembly and gas-liquid-solid（V-L-S）Deng so-called " from bottom to top " for representative
Growing technology, immense success is obtained in terms of flawless Nanosemiconductor Device is prepared, and illustrates potential application prospect.
But the integrated preparation of current nano-wire transistor is also immature, the method for preparing high-performance nano line transistor, first
It is that nano wire grown by gas-liquid-solid method on substrate, shells from former substrate nano wire followed by lift-off technology
From, and diluted with solution, nanowire suspension is formed, and then be coated on another new substrate and deposit source-drain electrode, finally make
Make gate dielectric layer and gate electrode.Nanowire epitaxy growth and device preparative separation are added complex process journey by this technology of preparing
Degree.Nano wire is shifted by the way of nanowire suspension is coated so that nano wire arrangement is uneven, unordered, and yield rate is relatively low,
It is unable to reach integrated controllable, the purpose of batch production.
The content of the invention
In order to solve the above-mentioned technical problem, it is orderly controllable it is an object of the invention to provide one kind arrangement, and finished product can be improved
A kind of integrated non-polar GaN nano wire HEMT of rate and preparation method thereof.
The technical solution adopted in the present invention is：
Integrated non-polar GaN nano wire HEMT, including substrate and the dielectric on substrate
Growth respectively is etched with multiple grooves, the multiple groove on layer, the insulating medium layer heterojunction nano-wire, described exhausted
Be formed with source electrode and drain electrode on edge dielectric layer, the source electrode and drain electrode respectively positioned at the two ends of heterojunction nano-wire and with respectively with
Each heterojunction nano-wire connection, is formed with grid between the source electrode and drain electrode, is set between the grid and heterojunction nano-wire
There is gate dielectric layer.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
Junction nanowire is located at recess sidewall, and in triangular prism structure.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
Junction nanowire includes nanometer core, the shell for wrapping up nanometer core and the cushion positioned at nanometer core and recess sidewall.
It is the multiple as the further improvement of described integrated non-polar GaN nano wire HEMT
Groove is in arrange at equal intervals.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
Junction nanowire lateral dimension is 500nm~3um.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
The length of junction nanowire is identical with the length of the recess sidewall.
As the further improvement of described integrated non-polar GaN nano wire HEMT, the grid are situated between
Matter layer is the single layer structure that any one material is constituted in silica, silicon nitride or high-K dielectric materials, either
The sandwich construction that any different materials are constituted in silica, silicon nitride or high-K dielectric materials.
Integrated non-polar GaN nano wire HEMT preparation method, comprises the following steps：
A, offer patterned semiconductor substrat structure, the semiconductor substrate structure include substrate and exhausted on substrate
Edge dielectric layer；
B, on insulating medium layer etching form multiple grooves；
C, each recess sidewall Epitaxial growth formation heterojunction nano-wire；
D, formation source electrode and drain electrode on the insulating medium layer positioned at heterojunction nano-wire both sides, and make source electrode and drain electrode equal
It is connected respectively with each heterojunction nano-wire；
E, form grid structure between source electrode and drain electrode, the grid structure includes grid and positioned at grid and hetero-junctions
Gate dielectric layer between nano wire.
As the further improvement of described integrated non-polar GaN nano wire HEMT preparation method,
The step B includes：
B1, in dielectric layer surface coat photoresist layer；
B2, groove pattern is defined on photoresist layer；
B3, to insulating medium layer carry out wet etching；
B4, the remaining photoresist of removal；
B5, wet etching groove floor and recess sidewall.
The beneficial effects of the invention are as follows：
Integrated non-polar GaN nano wire HEMT of the present invention and preparation method thereof uses patterned substrate
Epitaxial growth heterojunction nano-wire and then making electronic device, without substep, by first growing heterojunction nano-wire, retransfer lining
Bottom prepares device, so as to by the preparation organic unity of epitaxial growth and device, enormously simplify processing step, optimize technique
Method.The present invention, so as to which the arrangement of heterojunction nano-wire and integrated quantity is determined initial stage in preparation, is solved by etched recesses
Determined current nano-wire transistor using solution dilute coated come uncontrollability and randomness, effectively increase nano wire crystalline substance
The standby success rate of body control.
Brief description of the drawings
The embodiment to the present invention is described further below in conjunction with the accompanying drawings：
Fig. 1 is the structural representation of integrated non-polar GaN nano wire HEMT of the invention；
Fig. 2 is that the structure of integrated non-polar GaN nano wire HEMT heterojunction nano-wire of the invention is shown
It is intended to；
Fig. 3 is the step flow chart of integrated non-polar GaN nano wire HEMT preparation method of the invention.
Embodiment
With reference to Fig. 1-Fig. 2, integrated non-polar GaN nano wire HEMT of the invention, including substrate 1 and position
Given birth to respectively in being etched with the insulating medium layer 2 on substrate 1, the insulating medium layer 2 in multiple grooves 3, the multiple groove 3
With heterojunction nano-wire 4, source electrode 5 and drain electrode 6 are formed with the insulating medium layer 2, position is distinguished in the source electrode 5 and drain electrode 6
In the two ends of heterojunction nano-wire 4 and with being connected respectively with each heterojunction nano-wire 4, it is formed between the source electrode 5 and drain electrode 6
Grid 7, is provided with gate dielectric layer 8 between the grid 7 and heterojunction nano-wire 4.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
Junction nanowire 4 is located at the side wall 31 of groove 3, and in triangular prism structure.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
Junction nanowire 4 includes nanometer core 41, the shell 42 for wrapping up nanometer core 41 and positioned at nanometer core 41 and the side wall of groove 3
31 cushion 43.
It is the multiple as the further improvement of described integrated non-polar GaN nano wire HEMT
Groove 3 is in arrange at equal intervals.
Wherein, the spread geometry of groove 3 is can specifically to determine it according to circuit devcie layout design and circuit function
Spread geometry species, number and nano wire direction.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
The lateral dimension of junction nanowire 4 is 500nm~3um.
It is described heterogeneous as the further improvement of described integrated non-polar GaN nano wire HEMT
The length of junction nanowire 4 is identical with the length of the side wall 31 of groove 3.
As the further improvement of described integrated non-polar GaN nano wire HEMT, the grid are situated between
Matter layer 8 is the single layer structure that any one material is constituted in silica, silicon nitride or high-K dielectric materials, or
It is the sandwich construction that any different materials are constituted in silica, silicon nitride or high-K dielectric materials.
With reference to Fig. 3, integrated non-polar GaN nano wire HEMT preparation method comprises the following steps：
A, the structure of offer patterned semiconductor substrate 1, the structure of Semiconductor substrate 1 include substrate 1 and on substrate 1
Insulating medium layer 2；
B, on insulating medium layer 2 etching form multiple grooves 3；
C, each Epitaxial growth of 3 side wall of groove 31 formation heterojunction nano-wire 4；
D, formation source electrode 5 and drain electrode 6 on the insulating medium layer 2 positioned at the both sides of heterojunction nano-wire 4, and make the He of source electrode 5
Drain electrode 6 is respectively connected with each heterojunction nano-wire 4；
E, source electrode 5 and drain electrode 6 between formed the structure of grid 7, the structure of grid 7 include grid 7 and positioned at grid 7 with
Gate dielectric layer 8 between heterojunction nano-wire 4.
As the further improvement of described integrated non-polar GaN nano wire HEMT preparation method,
The step B includes：
B1, on the surface of insulating medium layer 2 coat photoresist layer；
B2, the figure of groove 3 is defined on photoresist layer；
B3, to insulating medium layer 2 carry out wet etching；
B4, the remaining photoresist of removal；
B5, the bottom surface of wet etching groove 3 and the side wall 31 of groove 3.
The specific embodiment of the present invention is as follows：
Embodiment 1, with reference to Fig. 1~Fig. 3 is referred to, performing step A, there is provided the structure of Semiconductor substrate 1, the Semiconductor substrate
1 structure includes substrate 1, the insulating medium layer 2 on substrate 1.The material of substrate 1 is monocrystalline silicon；Insulation on substrate 1
The material of dielectric layer 2 is silicon dioxide layer or silicon nitride, but is not limited only to this two media layer, can be people in the art
Other known dielectric layers of member.The graphical Semiconductor substrate 1, forms the rectangular recess 3 of array.Wherein form the square of array
Connected in star 3 includes：In silica layer surface coating photoresist layer；The rectangular recess of array is defined in the photoresist layer
3 figures；Silicon dioxide layer described in wet etching；Remove photoresist；The bottom surface of groove 3 described in wet etching and the side wall 31 of groove 3.Battle array
The figure of rectangular recess 3 of row is is spaced consistent longitudinal arrangement figure, and the number of groove 3 is 20, each size of groove 3 be 3um ×
5um.Its length of further groove 3 is the length of nano wire, and the spacing of groove 3 is 2um.The depth for etching the bottom surface of groove 3 is
1um。
Heterojunction nano-wire 4 is grown in the array groove 3 of the patterned semiconductor substrate 1.Fig. 2 is hetero-junctions nanometer
The part sectioned view of line 4.Heterojunction nano-wire 4 is grown on the side wall 31 of groove 3.Wherein described heterojunction nano-wire 45 is three
Prism structure.The epitaxial structure of heterojunction nano-wire 45 is AlN/GaN/AlGaN.But it is not limited only to this epitaxial structure, Ke Yishi
Meet other epitaxial structures of nano wire HEMT characteristic.Wherein shell 42 is AlGaN material, nanometer core
Core 41 is GaN material.Cushion 43 is AlN.The method of heterojunction nano-wire 4 is grown in the specific embodiment of the invention to utilize
MOCVD epitaxy technology growth heterojunction nano-wire 4, but MOCVD epitaxy technology is not limited to, can be as well known to those skilled in the art
Other epitaxy technologies.
Source electrode 5 and drain electrode 6 are formed on the patterned semiconductor substrate 1 for having heterojunction nano-wire 4 in described grow.Described
Source electrode 5 and drain electrode 6 are located at the both sides of heterojunction nano-wire 4 respectively, and covering heterojunction nano-wire 4 in part makes the different of each array
Matter junction nanowire 4 couples.
The structure of grid 7 is formed between the source electrode 5 and drain electrode 6, the structure of grid 7 includes grid 7 and positioned at described
Gate dielectric layer 8 between grid 7 and heterojunction nano-wire 4.Wherein described gate dielectric layer 8 be by silica, silicon nitride or
The single layer structure that any one material is constituted in high-K dielectric materials, or by silica, silicon nitride or high-K
The sandwich construction that any different materials are constituted in dielectric material.The wherein described material of grid 7 is heavily doped polysilicon or metal.
Embodiment 2, with reference to Fig. 1~Fig. 3 is referred to, there is provided the structure of Semiconductor substrate 1, the structure of Semiconductor substrate 1 includes
Substrate 1, the insulating medium layer 2 on substrate 1.The material of substrate 1 is the insulating medium layer 2 on monocrystalline silicon, substrate 1
Material be silicon dioxide layer or silicon nitride, but be not limited only to this two media layer, can be well known to a person skilled in the art
Other dielectric layers.The graphical Semiconductor substrate 1, forms the rectangular recess 3 of array.Wherein form the rectangular recess 3 of array
Including：In silica layer surface coating photoresist layer；The figure of rectangular recess 3 of array is defined in the photoresist layer；
Silicon dioxide layer described in wet etching；Remove photoresist；The bottom surface of wet etching groove 3 and the side wall 31 of groove 3.The rectangle of array is recessed
The figure of groove 3 is is spaced consistent longitudinal arrangement figure, and the number of groove 3 is 50, and each size of groove 3 is 3um × 10um.Its concave
The length of groove 3 is the length of nano wire, and the spacing of groove 3 is 2um.The depth of the bottom surface substrate 1 of etched recesses 3 is 2um.
Heterojunction nano-wire 4 is grown in the array groove 3 of the patterned semiconductor substrate 1.Fig. 2 is hetero-junctions nanometer
The part sectioned view of line 4.Heterojunction nano-wire 4 is grown on the side wall 31 of groove 3.Wherein described heterojunction nano-wire 45 is three
Prism structure.The epitaxial structure of heterojunction nano-wire 45 is AlN/GaN/AlGaN.But it is not limited only to this epitaxial structure, Ke Yishi
Meet other epitaxial structures of nano wire HEMT characteristic.Wherein shell 42 is AlGaN material, nanometer core
Core 41 is GaN material.Cushion 43 is AlN.The method of heterojunction nano-wire 4 is grown in the specific embodiment of the invention to utilize
MOCVD epitaxy technology growth heterojunction nano-wire 4, but MOCVD epitaxy technology is not limited to, can be as well known to those skilled in the art
Other epitaxy technologies.
Source electrode 5 and drain electrode 6 are formed on the patterned semiconductor substrate 1 for having heterojunction nano-wire 4 in described grow.Described
Source electrode 5 and drain electrode 6 are located at the both sides of heterojunction nano-wire 4 respectively, and covering heterojunction nano-wire 4 in part makes the different of each array
Matter junction nanowire 4 couples.
The structure of grid 7 is formed between the source electrode 5 and drain electrode 6, the structure of grid 7 includes grid 7 and positioned at described
Gate dielectric layer 8 between grid 7 and heterojunction nano-wire 4.Wherein described gate dielectric layer 8 be by silica, silicon nitride or
The single layer structure that any one material is constituted in high-K dielectric materials, or by silica, silicon nitride or high-K
The sandwich construction that any different materials are constituted in dielectric material.The wherein described material of grid 7 is heavily doped polysilicon or metal.
Embodiment 3, with reference to Fig. 1~Fig. 3 is referred to, performing step A, there is provided the structure of Semiconductor substrate 1, the Semiconductor substrate
1 structure includes substrate 1, the insulating medium layer 2 on substrate 1.The material of substrate 1 is monocrystalline silicon；Insulation on substrate 1
The material of dielectric layer 2 is silicon dioxide layer or silicon nitride, but is not limited only to this two media layer, can be people in the art
Other known dielectric layers of member.The graphical Semiconductor substrate 1, forms the rectangular recess 3 of array.Wherein form the square of array
Connected in star 3 includes：In silica layer surface coating photoresist layer；The rectangular recess of array is defined in the photoresist layer
3 figures；Silicon dioxide layer described in wet etching；Remove photoresist；The bottom surface of groove 3 described in wet etching and the side wall 31 of groove 3.Battle array
The figure of rectangular recess 3 of row is is spaced consistent longitudinal arrangement figure, and the number of groove 3 is 50, each size of groove 3 be 5um ×
10um.Its length of further groove 3 is the length of nano wire, and the spacing of groove 3 is 5um.The depth for etching the bottom surface of groove 3 is
1um。
Heterojunction nano-wire 4 is grown in the array groove 3 of the patterned semiconductor substrate 1.Fig. 2 is hetero-junctions nanometer
The part sectioned view of line 4.Heterojunction nano-wire 4 is grown on the side wall 31 of groove 3.Wherein described heterojunction nano-wire 45 is three
Prism structure.The epitaxial structure of heterojunction nano-wire 45 is AlN/GaN/AlGaN.But it is not limited only to this epitaxial structure, Ke Yishi
Meet other epitaxial structures of nano wire HEMT characteristic.Wherein shell 42 is AlGaN material, nanometer core
Core 41 is GaN material.Cushion 43 is AlN.The method of heterojunction nano-wire 4 is grown in the specific embodiment of the invention to utilize
MOCVD epitaxy technology growth heterojunction nano-wire 4, but MOCVD epitaxy technology is not limited to, can be as well known to those skilled in the art
Other epitaxy technologies.
Source electrode 5 and drain electrode 6 are formed on the patterned semiconductor substrate 1 for having heterojunction nano-wire 4 in described grow.Described
Source electrode 5 and drain electrode 6 are located at the both sides of heterojunction nano-wire 4 respectively, and covering heterojunction nano-wire 4 in part makes the different of each array
Matter junction nanowire 4 couples.
The structure of grid 7 is formed between the source electrode 5 and drain electrode 6, the structure of grid 7 includes grid 7 and positioned at described
Gate dielectric layer 8 between grid 7 and heterojunction nano-wire 4.Wherein described gate dielectric layer 8 be by silica, silicon nitride or
The single layer structure that any one material is constituted in high-K dielectric materials, or by silica, silicon nitride or high-K
The sandwich construction that any different materials are constituted in dielectric material.The wherein described material of grid 7 is heavily doped polysilicon or metal.
Embodiment 4, with reference to Fig. 1~Fig. 3 is referred to, performing step A, there is provided the structure of Semiconductor substrate 1, the Semiconductor substrate
1 structure includes substrate 1, the insulating medium layer 2 on substrate 1.The material of substrate 1 is monocrystalline silicon；Insulation on substrate 1
The material of dielectric layer 2 is silicon dioxide layer or silicon nitride, but is not limited only to this two media layer, can be people in the art
Other known dielectric layers of member.The graphical Semiconductor substrate 1, forms the rectangular recess 3 of array.Wherein form the square of array
Connected in star 3 includes：In silica layer surface coating photoresist layer；The rectangular recess of array is defined in the photoresist layer
3 figures；Silicon dioxide layer described in wet etching；Remove photoresist；The bottom surface of groove 3 described in wet etching and the side wall 31 of groove 3.Battle array
The figure of rectangular recess 3 of row is is spaced consistent longitudinal arrangement figure, and the number of groove 3 is 100, each size of groove 3 be 5um ×
15um.Its length of further groove 3 is the length of nano wire, and the spacing of groove 3 is 5um.The depth for etching the bottom surface of groove 3 is
2um。
Heterojunction nano-wire 4 is grown in the array groove 3 of the patterned semiconductor substrate 1.Fig. 2 is hetero-junctions nanometer
The part sectioned view of line 4.Heterojunction nano-wire 4 is grown on the side wall 31 of groove 3.Wherein described heterojunction nano-wire 45 is three
Prism structure.The epitaxial structure of heterojunction nano-wire 45 is AlN/GaN/AlGaN.But it is not limited only to this epitaxial structure, Ke Yishi
Meet other epitaxial structures of nano wire HEMT characteristic.Wherein shell 42 is AlGaN material, nanometer core
Core 41 is GaN material.Cushion 43 is AlN.The method of heterojunction nano-wire 4 is grown in the specific embodiment of the invention to utilize
MOCVD epitaxy technology growth heterojunction nano-wire 4, but MOCVD epitaxy technology is not limited to, can be as well known to those skilled in the art
Other epitaxy technologies.
Source electrode 5 and drain electrode 6 are formed on the patterned semiconductor substrate 1 for having heterojunction nano-wire 4 in described grow.Described
Source electrode 5 and drain electrode 6 are located at the both sides of heterojunction nano-wire 4 respectively, and covering heterojunction nano-wire 4 in part makes the different of each array
Matter junction nanowire 4 couples.
The structure of grid 7 is formed between the source electrode 5 and drain electrode 6, the structure of grid 7 includes grid 7 and positioned at described
Gate dielectric layer 8 between grid 7 and heterojunction nano-wire 4.Wherein described gate dielectric layer 8 be by silica, silicon nitride or
The single layer structure that any one material is constituted in high-K dielectric materials, or by silica, silicon nitride or high-K
The sandwich construction that any different materials are constituted in dielectric material.The wherein described material of grid 7 is heavily doped polysilicon or metal.
Embodiment 5, with reference to Fig. 1~Fig. 3 is referred to, performing step A, there is provided the structure of Semiconductor substrate 1, the Semiconductor substrate
1 structure includes substrate 1, the insulating medium layer 2 on substrate 1.The material of substrate 1 is monocrystalline silicon；Insulation on substrate 1
The material of dielectric layer 2 is silicon dioxide layer or silicon nitride, but is not limited only to this two media layer, can be people in the art
Other known dielectric layers of member.The graphical Semiconductor substrate 1, forms the rectangular recess 3 of array.Wherein form the square of array
Connected in star 3 includes：In silica layer surface coating photoresist layer；The rectangular recess of array is defined in the photoresist layer
3 figures；Silicon dioxide layer described in wet etching；Remove photoresist；The bottom surface of groove 3 described in wet etching and the side wall 31 of groove 3.Battle array
The figure of rectangular recess 3 of row is is spaced consistent longitudinal arrangement figure, and the number of groove 3 is 150, and each size of groove 3 is 10um
×20um.Its length of further groove 3 is the length of nano wire, and the spacing of groove 3 is 5um.The depth for etching the bottom surface of groove 3 is
5um。
Heterojunction nano-wire 4 is grown in the array groove 3 of the patterned semiconductor substrate 1.Fig. 2 is hetero-junctions nanometer
The part sectioned view of line 4.Heterojunction nano-wire 4 is grown on the side wall 31 of groove 3.Wherein described heterojunction nano-wire 45 is three
Prism structure.The epitaxial structure of heterojunction nano-wire 45 is AlN/GaN/AlGaN.But it is not limited only to this epitaxial structure, Ke Yishi
Meet other epitaxial structures of nano wire HEMT characteristic.Wherein shell 42 is AlGaN material, nanometer core
Core 41 is GaN material.Cushion 43 is AlN.The method of heterojunction nano-wire 4 is grown in the specific embodiment of the invention to utilize
MOCVD epitaxy technology growth heterojunction nano-wire 4, but MOCVD epitaxy technology is not limited to, can be as well known to those skilled in the art
Other epitaxy technologies.
Source electrode 5 and drain electrode 6 are formed on the patterned semiconductor substrate 1 for having heterojunction nano-wire 4 in described grow.Described
Source electrode 5 and drain electrode 6 are located at the both sides of heterojunction nano-wire 4 respectively, and covering heterojunction nano-wire 4 in part makes the different of each array
Matter junction nanowire 4 couples.
The structure of grid 7 is formed between the source electrode 5 and drain electrode 6, the structure of grid 7 includes grid 7 and positioned at described
Gate dielectric layer 8 between grid 7 and heterojunction nano-wire 4.Wherein described gate dielectric layer 8 be by silica, silicon nitride or
The single layer structure that any one material is constituted in high-K dielectric materials, or by silica, silicon nitride or high-K
The sandwich construction that any different materials are constituted in dielectric material.The wherein described material of grid 7 is heavily doped polysilicon or metal.
Above is the preferable implementation to the present invention is illustrated, but the invention is not limited to the implementation
Example, those skilled in the art can also make a variety of equivalent variations or replace on the premise of without prejudice to spirit of the invention
Change, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (8)
1. integrated non-polar GaN nano wire HEMT, it is characterised in that：Including substrate and on substrate
Growth respectively is etched with multiple grooves, the multiple groove on insulating medium layer, the insulating medium layer hetero-junctions nanometer
Source electrode and drain electrode are formed with line, the insulating medium layer, the source electrode and drain electrode are located at the two ends of heterojunction nano-wire respectively
And be connected respectively with each heterojunction nano-wire, grid, the grid and hetero-junctions nanometer are formed between the source electrode and drain electrode
Gate dielectric layer is provided between line, the gate dielectric layer is any one material institute in silica or high-K dielectric materials
The single layer structure of composition, or the multilayer knot that any different materials are constituted in silica or high-K dielectric materials
Structure.
2. integrated non-polar GaN nano wire HEMT according to claim 1, it is characterised in that：Institute
Heterojunction nano-wire is stated positioned at recess sidewall, and in triangular prism structure.
3. integrated non-polar GaN nano wire HEMT according to claim 2, it is characterised in that：Institute
Heterojunction nano-wire is stated including nanometer core, the shell for wrapping up nanometer core and positioned at the slow of nanometer core and recess sidewall
Rush layer.
4. integrated non-polar GaN nano wire HEMT according to claim 1, it is characterised in that：Institute
It is in arrange at equal intervals to state multiple grooves.
5. integrated non-polar GaN nano wire HEMT according to claim 1, it is characterised in that：Institute
Heterojunction nano-wire lateral dimension is stated for 500nm~3um.
6. integrated non-polar GaN nano wire HEMT according to claim 1, it is characterised in that：Institute
The length for stating heterojunction nano-wire is identical with the length of the recess sidewall.
7. integrated non-polar GaN nano wire HEMT preparation method, it is characterised in that：Comprise the following steps：
A, offer semiconductor substrate structure, the semiconductor substrate structure include substrate and the insulating medium layer on substrate；
B, on insulating medium layer etching form multiple grooves；
C, the heterojunction nano-wire in each recess sidewall Epitaxial growth formation non-polar GaN；
D, formation source electrode and drain electrode on the insulating medium layer positioned at heterojunction nano-wire both sides, and make source electrode and drain electrode respectively
It is connected with each heterojunction nano-wire；
E, form grid structure between source electrode and drain electrode, the grid structure includes grid and positioned at grid and hetero-junctions nanometer
Gate dielectric layer between line.
8. integrated non-polar GaN nano wire HEMT preparation method according to claim 7, its feature
It is：The step B includes：
B1, in dielectric layer surface coat photoresist layer；
B2, groove pattern is defined on photoresist layer；
B3, to insulating medium layer carry out wet etching；
B4, the remaining photoresist of removal；
B5, wet etching groove floor and recess sidewall.
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| CN105118860B (en) * | 2015-08-18 | 2018-05-08 | 华南师范大学 | One kind integrates orderly GaN base nano-wire array HEMT and preparation method thereof |
| CN105845714B (en) * | 2016-02-27 | 2019-12-03 | 黄辉 | A kind of nano-wire devices and preparation method thereof based on bridge joint growth |
| CN106082121A (en) * | 2016-06-16 | 2016-11-09 | 华南师范大学 | Nano-wire array preparation method, nano-wire array integrated device and preparation method thereof |
| CN106981506B (en) * | 2017-04-19 | 2023-09-29 | 华南理工大学 | Nanowire GaN high electron mobility transistor |
| CN107195586B (en) * | 2017-04-27 | 2019-08-09 | 华南师范大学 | A kind of GaN horizontal nanowire electronic device preparation method |
| CN110116987A (en) * | 2019-03-15 | 2019-08-13 | 大连理工大学 | A kind of semiconductor nanowires sensor |
| CN111653613A (en) * | 2020-05-19 | 2020-09-11 | 中国科学院微电子研究所 | Two-dimensional material superlattice device and manufacturing method thereof |
| CN111969056A (en) * | 2020-08-31 | 2020-11-20 | 华南师范大学 | Core-shell structure AlGaN/GaN heterojunction nanowire-based transistor and preparation method thereof |
| CN112164717A (en) * | 2020-09-15 | 2021-01-01 | 五邑大学 | Normally-off GaN/AlGaN HEMT device and preparation method thereof |
| CN113594004B (en) * | 2021-07-29 | 2022-07-08 | 中国科学院上海微系统与信息技术研究所 | Vacuum channel transistor and preparation method thereof |
| CN113809152A (en) * | 2021-08-11 | 2021-12-17 | 浙江芯国半导体有限公司 | Gallium nitride microwire-based high electron mobility transistor array and preparation method thereof |
| CN113809153B (en) * | 2021-08-11 | 2024-04-16 | 浙江芯科半导体有限公司 | Silicon carbide-based aluminum gallium nitride/gallium nitride micron line HEMT power device and preparation method thereof |
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