CN104020621B - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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CN104020621B
CN104020621B CN201410224631.1A CN201410224631A CN104020621B CN 104020621 B CN104020621 B CN 104020621B CN 201410224631 A CN201410224631 A CN 201410224631A CN 104020621 B CN104020621 B CN 104020621B
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electrode
thin film
base palte
array base
tft
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CN104020621A (zh
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曹占锋
丁录科
张文林
孔祥春
张锋
姚琪
章志兴
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BOE Technology Group Co Ltd
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Priority to PCT/CN2014/086809 priority patent/WO2015180302A1/zh
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Abstract

本发明实施例公开了一种阵列基板及其制备方法、显示装置，涉及显示技术领域，能够防止铜等金属在对透明导电薄膜进行构图工艺的过程中发生氧化，保证源极和漏极的导电能力。该种阵列基板，包括多个阵列排布的像素单元区域，所述像素单元区域包括薄膜晶体管和像素电极，所述薄膜晶体管的有源层和所述像素电极之间形成有第一绝缘层，所述第一绝缘层形成有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。

Description

一种阵列基板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
由于使用工作电压低、功耗小、显示方式灵活、辐射低等优点，液晶显示器(LiquidCrystal Display，LCD)广泛应用于各种领域，如计算机、手机、电视及测量显示等领域。LCD包括液晶显示面板，液晶显示面板包括设置有薄膜晶体管的阵列基板、与阵列基板对盒的彩膜基板以及夹设在两基板之间的液晶层，LCD工作过程中，由阵列基板上的像素电极和彩膜基板上的公共电极之间产生电压差来驱动液晶层中的液晶分子，液晶层中各处的液晶分子的偏转角度不一致，使得LCD可以进行显示。
发明人发现，由于在形成阵列基板的各层结构的过程中，首先利用铜等金属形成源极和漏极等结构，之后形成一透明导电薄膜，并对该透明导电薄膜进行构图工艺形成像素电极，在对透明导电薄膜进行构图工艺的过程中，铜等金属制成的源极和漏极等结构暴露在外，金属表面容易发生氧化，并且金属表面的氧化层的厚度会随着时间的推移继续增加，当氧化层的厚度较大时，影响了源极和漏极的导电能力，阵列基板有可能无法正常工作，影响了产品的良率，并且降低了用户的使用体验。
发明内容
本发明所要解决的技术问题在于提供一种阵列基板及其制备方法、显示装置，能够防止铜等金属在对透明导电薄膜进行构图工艺的过程中发生氧化，保证源极和漏极的导电能力。
为解决上述技术问题，本发明采用如下技术方案：
本发明第一方面提供了一种阵列基板，包括多个阵列排布的像素单元区域，所述像素单元区域包括薄膜晶体管和像素电极，所述薄膜晶体管的有源层和所述像素电极之间形成有第一绝缘层，所述第一绝缘层形成有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
在本发明实施例的技术方案中，由于所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层，可以首先制成像素电极之后，再形成源极和漏极，防止了现有技术中先形成源极、漏极之后再形成像素电极的过程中，铜等金属制成的源极和漏极等结构暴露在外造成的源极和漏极等结构被氧化等不良现象，保证了源极和漏极的导电能力，保证了阵列基板能够正常工作，同时保证了产品的良率，保证了用户的使用体验。
所述阵列基板还包括数据线，所述数据线与所述薄膜晶体管的源极和漏极位于同一图层。
所述阵列基板还包括位于所述像素电极之上的第二绝缘层和公共电极。
所述阵列基板还包括位于所述薄膜晶体管之下的第二绝缘层和公共电极。
所述阵列基板还包括黑矩阵和彩膜。
本发明第二方面提供了一种显示装置，包括上述的阵列基板。
本发明第三方面提供了一种阵列基板的制备方法，包括：
形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形，所述第一绝缘层包括第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端；
形成包括薄膜晶体管的源极和漏极的图形，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
所述形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形包括：
形成有源层的图形；
形成第一绝缘层和透明导电薄膜；
对所述第一绝缘层和所述透明导电薄膜进行构图工艺，形成所述第一绝缘层的第一过孔和第二过孔，并形成所述像素电极。
所述形成包括薄膜晶体管的源极和漏极的图形包括：
形成薄膜晶体管的源极和漏极的图形、数据线。
所述的制备方法还包括：
形成第二绝缘层和公共电极，所述第二绝缘层位于所述像素电极和所述公共电极之间。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中的阵列基板的平面示意图一；
图2为图1的A-A＇截面示意图；
图3为本发明实施例中的阵列基板的结构示意图一；
图4为本发明实施例中的阵列基板的结构示意图二；
图5为本发明实施例中的阵列基板的结构示意图三；
图6为本发明实施例中的阵列基板的结构示意图四；
图7为本发明实施例中的阵列基板的制备方法的流程图一；
图8为本发明实施例中的阵列基板的平面示意图二；
图9为本发明实施例中的阵列基板的制备方法的流程图二；
图10为本发明实施例中的阵列基板的平面示意图三；
图11为本发明实施例中的阵列基板的平面示意图四；
图12为图11的A-A＇截面示意图；
图13为本发明实施例中的阵列基板的结构示意图五；
图14为本发明实施例中的阵列基板的结构示意图六；
图15为本发明实施例中的阵列基板的平面示意图一；
图16为图15的A-A＇截面示意图；
图17为本发明实施例中的阵列基板的平面示意图一；
图18为图17的A-A＇截面示意图；
图19为本发明实施例中的阵列基板的结构示意图七。
附图标记说明：
1—衬底基板； 2—薄膜晶体管； 21—有源层；
22—栅极； 23—栅极绝缘层； 24—源极；
25—漏极； 3—像素电极； 4—第一绝缘层；
5—第一过孔； 6—第二过孔； 7—数据线；
8—栅线； 9—第二绝缘层； 10—公共电极；
11—黑矩阵； 12—彩膜； 13—透明导电薄膜；
14—光刻胶层； 141—完全曝光区域； 142—未曝光区域；
143—部分曝光区域； 15—第一透明导电部分； 16—第二透明导电部分；
17—缝隙。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供一种阵列基板，如图1和图2所示，包括多个阵列排布的像素单元区域，所述像素单元区域包括薄膜晶体管2和像素电极3，所述薄膜晶体管2的有源层21和所述像素电极3之间形成有第一绝缘层4，所述第一绝缘层4形成有第一过孔5和第二过孔6，所述第一过孔5和所述第二过孔6分别对应所述有源层21的两端，所述薄膜晶体管2的源极24通过所述第一过孔5连接所述有源层21，所述薄膜晶体管2的漏极25搭接在所述像素电极3之上并通过所述第二过孔6连接所述有源层21。
显然，在本发明实施例中，由于所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层，可以首先制成像素电极之后，再形成源极和漏极，防止了现有技术中先形成源极、漏极之后再形成像素电极的过程中，铜等金属制成的源极和漏极等结构暴露在外造成的源极和漏极等结构被氧化等不良现象，保证了源极和漏极的导电能力，保证了阵列基板能够正常工作，同时保证了产品的良率，保证了用户的使用体验。
显然，如图1和图2所示，所述阵列基板还包括数据线7，一般的，所述数据线7与所述薄膜晶体管2的源极24和漏极25可位于同一图层，即所述数据线7、所述源极24和所述漏极25可在同一次构图工艺中形成，此时，数据线7、源极24和漏极25均在形成像素电极3等结构之后才形成，可防止数据线7、源极24和漏极25等结构在形成像素电极3的过程中被氧化。
需要说明的是，在形成有源层21、第一绝缘层4和像素电极3的图形之前，结合图1和图2可知，需要在阵列基板的衬底基板1之上形成有栅线8(图中未示出)、与栅线8一体成型的薄膜晶体管2的栅极22和栅极绝缘层23等结构。
显然，图1和图2所示的阵列基板为扭曲向列型(Twisted Nematic，简称TN)模式的阵列基板。在此基础上，可以考虑对图2所示的阵列基板的结构进行改进，例如，如图3所示，该阵列基板在图2所示的阵列基板的基础上还包括位于所述像素电极3之上的第二绝缘层9和公共电极10，第二绝缘层9位于公共电极10和像素电极3之间，保证了公共电极10和像素电极3的绝缘，以保证公共电极10和像素电极3之间产生一定的电压差，以驱动液晶分子的偏转，此时该阵列基板为高级超维场转换(Advanced Super Dimension Switch，简称ADS)模式的阵列基板。
所谓高级超维场转换技术(ADvanced Super Dimension Switch)，简称ADS,其核心技术特性描述为：通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。针对不同应用，ADS技术的改进技术有高透过率I-ADS技术、高开口率H-ADS和高分辨率S-ADS技术等。
为保证公共电极10和像素电极3可以形成多维电场，图3中的公共电极10为狭缝状电极，像素电极3为板状电极。
类似的，公共电极10和第二绝缘层9也可设置于像素电极3之下，具体的，如图4所示，所述阵列基板还包括位于所述薄膜晶体管2之下的第二绝缘层9和公共电极10，即该阵列基板的衬底基板1由下至上依次设置有公共电极10、第二绝缘层9、同层设置的栅线8(图4中未示出)和栅极22、栅极绝缘层23、薄膜晶体管2和数据线7等结构。
此时，为保证公共电极10和像素电极3可以形成多维电场，图4中的公共电极10为平板状，像素电极3为狭缝状电极。
由于近年来人们对于显示装置的透光率、分辨率、功耗等的要求越来越高，显示装置都在向着高透过率、高分辨率、低功耗等方向发展。其中，分辨率越高，使得每一个像素单元的尺寸越小，当像素单元的边长由几十微米变为十几微米时，显然，像素单元的尺寸得到了大幅度的减小，此时，若划分像素单元的黑矩阵的宽度仍然保持不变，相对于像素单元而言，黑矩阵将变得明显，将会影响显示装置的显示效果。因此，黑矩阵的宽度应相应的减小以保证显示装置的显示效果。之后，在黑矩阵圈出来的对应像素单元的显示区域上方形成彩膜。
但是，黑矩阵的宽度减小有可能导致阵列基板和彩膜基板之间的对盒出现偏差，导致漏光等不良现象的产生，因此位于彩膜基板上的黑矩阵的宽度不能任意减小。人们为了克服黑矩阵减小带来的漏光等不良现象，将黑矩阵和彩膜挪到阵列基板上。由于此时黑矩阵位于阵列基板上，在适当减小黑矩阵的宽度时，也能保证黑矩阵能够充分遮挡栅线、数据线和薄膜晶体管等需遮光的结构，同时，减少漏光现象发生的可能性，在提高分辨率、透过率的同时又保证了显示装置的显示效果。这种技术又叫做COA(Color Filter on Array)技术。
在本发明实施例中，可以如图5所示，在图2所形成的结构之下、衬底基板1之上形成黑矩阵11和彩膜12，以形成COA阵列基板。类似的，如图6所示，还可在图4所示的阵列基板的层结构之下、衬底基板1之上形成黑矩阵11和彩膜12，以形成COA的ADS阵列基板，在此不再赘述。
其中，第一绝缘层4、栅极绝缘层23和第二绝缘层9等结构都可采用氧化硅、氮化硅、氧化铪、树脂等绝缘材料制成。
进一步的，本发明实施例还提供了一种显示装置，包括上述任意一种阵列基板。具体的，该显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
实施例二
本发明实施例提供一种阵列基板的制备方法，如图7所示，该制备方法包括：
步骤S101、形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形，所述第一绝缘层包括第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端。
步骤S102、形成包括薄膜晶体管的源极和漏极的图形，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
显然，在本实施例的技术方案中，采用首先形成像素电极等结构，之后再形成源极和漏极的图形的方法，可有效防止了现有技术中先形成源极、漏极之后再形成像素电极的过程中，铜等金属制成的源极和漏极等结构暴露在外造成的源极和漏极等结构被氧化等不良现象，保证了源极和漏极的导电能力，保证了阵列基板能够正常工作，同时保证了产品的良率，保证了用户的使用体验。
显然，在步骤S101之前，如图8所示，阵列基板上首先形成有同层形成的栅线8和栅极22等结构、以及栅极绝缘层23，其中，由于栅极绝缘层23为透明绝缘层结构，因此图8中未示出。
具体的，在本发明实施例中，如图9所示，步骤S101包括：
步骤S1011、形成有源层的图形。
如图10所示，在图8的基础上，之后通过等离子体增强化学气相沉积法(PlasmaEnhanced Chemical Vapor Deposition，简称PECVD)的方法沉积半导体薄膜，通过构图工艺，形成有源层21的图形。
步骤S1012、形成第一绝缘层和透明导电薄膜。
如图11所示，在图10的基础上，首先通过涂覆等方式形成第一绝缘层4，之后，采用磁控溅射或热蒸发等方式，在第一绝缘层4之上形成透明导电薄膜13，类似的，由于第一绝缘层4为透明绝缘层结构，因此图11中未示出。
如图12所示，为图11所示的阵列基板的截面图，图12中可看到第一绝缘层4位于透明导电薄膜13之下。
步骤S1013、对所述第一绝缘层和所述透明导电薄膜进行构图工艺，形成所述第一绝缘层的第一过孔和第二过孔，并形成所述像素电极。
具体的，如图13所示，首先在图12的基础上，在透明导电薄膜13之上通过涂覆等方式形成光刻胶层14，采用掩模板曝光，使光刻胶层14形成完全曝光区域141、未曝光区域142和部分曝光区域143，如图14所示。
通过刻蚀工艺，刻蚀掉完全曝光区域141对应的透明导电薄膜13和第一绝缘层4，形成像素电极3、第一透明导电部分15和第二透明导电部分16，像素电极3、第一透明导电部分15和第二透明导电部分16之间均通过刻蚀形成缝隙17，每一缝隙17的宽度均大于3微米，可保证像素电极3、第一透明导电部分15和第二透明导电部分16相互绝缘，具体的，第一透明导电部分15、第二透明导电部分16分别覆盖有源层21的源极对应区域和漏极对应区域，如图15和16所示。
其中，需要说明的是，由于光刻胶层14为透明结构，因此图15中并未示出，以下类似，不再赘述。
显然，所述像素电极3、第一透明导电部分15和第二透明导电部分16之下还设置有第一绝缘层4，如图16所示。
通过灰化工艺去除部分曝光区域143的光刻胶层，暴露出第一过孔5对应的第一绝缘层4和透明导电薄膜13，以及第二过孔6对应的第一绝缘层4和透明导电薄膜13，通过相应的刻蚀手段依次刻蚀除去第一过孔5和第二过孔6对应的第一绝缘层4和透明导电薄膜13，如图17和18所示。
最后，去除未曝光区域141的光刻胶层14，即可实现在同一次构图工艺中分别形成第一绝缘层4的图形和像素电极3等结构的图形，如图19所示。
之后就可执行步骤S102，形成源极22和漏极，完成薄膜晶体管2的制作过程。需要说明的是，若采用上述步骤S1011～步骤S1013的制作方法形成像素电极3和第一绝缘层4的图形，则由于步骤S1013中形成的第一透明导电部分15和第二透明导电部分16之间的缝隙17将有源层21的对应区域暴露，如图19所示，因此，为了防止在源极24和漏极25的构图工艺中，源极24和漏极25对应的刻蚀液会对有源层21造成腐蚀，而由于金属铜的刻蚀液对有源层21几乎无影响，因此优选利用金属铜来形成源极24和漏极25。
最后，形成如图1和2所示的阵列基板。
其中，由于源极24下铺设有第一透明导电部分15，使得源极24和第一透明导电部分15并联，相当于减小有源层21和数据线7之间的电阻值，更有利于电信号的传输。类似的，漏极25下铺设有第二透明导电部分16，相应的可减小有源层21和像素电极3之间的电阻值。
进一步的，在本发明实施例中，所述数据线7可与源极24和漏极25在同一次构图工艺中形成，即所述形成包括薄膜晶体管2的源极24和漏极25的图形包括：形成薄膜晶体管2的源极24和漏极25的图形、数据线7。
更进一步的，本发明实施例的阵列基板还可为ADS型阵列基板，因此，该阵列基板的制备方法还可包括：
形成第二绝缘层和公共电极，所述第二绝缘层位于所述像素电极和所述公共电极之间。
具体的，第二绝缘层9和公共电极10可以在图2所示的阵列基板的基础上形成，形成如图3的阵列基板的结构；也可设置在形成栅线8(图中未示出)和栅极22等结构、以及栅极绝缘层23之前形成公共电极10和第二绝缘层9，形成如图4的阵列基板的结构。
更进一步的，本发明实施例的阵列基板也可为COA型阵列基板，因此，该阵列基板的制备方法还可包括：
形成黑矩阵和彩膜。
在本发明实施例中，可以如图5所示，在图2所形成的结构之下、衬底基板1之上形成黑矩阵11和彩膜12，以形成COA阵列基板。类似的，如图6所示，还可在图4所示的阵列基板的层结构之下、衬底基板1之上形成黑矩阵11和彩膜12，以形成COA的ADS阵列基板，在此不再赘述。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (9)

1.一种阵列基板，包括多个阵列排布的像素单元区域，所述像素单元区域包括薄膜晶体管和像素电极，所述薄膜晶体管的有源层和所述像素电极之间形成有第一绝缘层，其特征在于，所述薄膜晶体管的源极与所述第一绝缘层之间设有第一透明导电部分、所述薄膜晶体管的漏极与所述第一绝缘层之间设有第二透明导电部分，所述像素电极、所述第一透明导电部分与所述第二透明导电部分之间均形成有缝隙，所述第一绝缘层和所述第一透明导电部分上形成有第一过孔、所述第一绝缘层和所述第二透明导电部分上形成有第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端，所述薄膜晶体管的源极通过所述第一过孔直接连接所述有源层，所述薄膜晶体管的漏极通过所述第二过孔直接连接所述有源层，并且，所述薄膜晶体管的漏极覆盖所述像素电极与所述第二透明导电部分之间的缝隙并直接搭接在所述像素电极之上。
2.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括数据线，所述数据线与所述薄膜晶体管的源极和漏极位于同一图层。
3.根据权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括位于所述像素电极之上的第二绝缘层和公共电极。
4.根据权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括位于所述薄膜晶体管之下的第二绝缘层和公共电极。
5.根据权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括黑矩阵和彩膜。
6.一种显示装置，其特征在于，包括如权利要求1-5任一项所述的阵列基板。
7.一种阵列基板的制备方法，其特征在于，包括：
形成有源层的图形；
形成第一绝缘层和透明导电薄膜；
对所述第一绝缘层和所述透明导电薄膜进行构图工艺，形成相互之间具有缝隙的像素电极、第一透明导电部分、第二透明导电部分，并在所述第一透明导电部分与所述第一绝缘层上形成第一过孔、在第二透明导电部分和第一绝缘层上形成第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端；
形成包括薄膜晶体管的源极和漏极的图形，所述薄膜晶体管的源极通过所述第一过孔直接连接所述有源层，所述薄膜晶体管的漏极通过所述第二过孔直接连接所述有源层，并且，所述薄膜晶体管的漏极覆盖所述像素电极与所述第二透明导电部分之间的缝隙并直接搭接在所述像素电极之上。
8.根据权利要求7所述的制备方法，其特征在于，所述形成包括薄膜晶体管的源极和漏极的图形包括：
形成薄膜晶体管的源极和漏极的图形、数据线。
9.根据权利要求8所述的制备方法，其特征在于，还包括：
形成第二绝缘层和公共电极，所述第二绝缘层位于所述像素电极和所述公共电极之间。
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