CN102881688B - 一种阵列基板、显示面板及阵列基板的制造方法 - Google Patents

一种阵列基板、显示面板及阵列基板的制造方法 Download PDF

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CN102881688B
CN102881688B CN201210349520.4A CN201210349520A CN102881688B CN 102881688 B CN102881688 B CN 102881688B CN 201210349520 A CN201210349520 A CN 201210349520A CN 102881688 B CN102881688 B CN 102881688B
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transparent conductive
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CN102881688A (zh
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邓检
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种阵列基板、显示面板及阵列基板的制造方法,所述阵列基板包括多个像素单元,每个像素单元包括薄膜晶体管、透明导电金属层和像素电极,所述薄膜晶体管包括栅极、有源层、源极和漏极,其中,所述有源层位于栅极的上方或者下方;所述透明导电金属层与有源层层叠接触;所述源极和漏极形成有源层的沟道,且所述漏极与像素电极连接。由于透明导电金属与有源层层叠接触,在阵列基板的制造过程中,在沉积透明导电薄膜和有源层薄膜之后,只需通过一次半色调掩模构图工艺即可形成像素电极图形和有源层图形,大大简化了生产工艺,同时也减少了该次掩模构图工艺可能带来的产品缺陷,大大提高了产能。

Description

一种阵列基板、显示面板及阵列基板的制造方法
技术领域
本发明涉及薄膜晶体管液晶显示技术领域,特别是涉及一种阵列基板、显示面板及阵列基板的制造方法。
背景技术
在平板显示装置中,薄膜晶体管液晶显示器(Thin Film Transistor LiquidCrystal Display,简称TFT-LCD)具有体积小、功耗低、制造成本相对较低和无辐射等特点,在当前的平板显示器市场占据了主导地位。
目前,TFT-LCD的显示模式主要有TN(Twisted Nematic,扭曲向列)模式、VA(Vertical Alignment,垂直取向)模式、IPS(In-Plane-Switching,平面方向转换)模式和AD-SDS(ADvanced Super Dimension Switch,高级超维场转换技术,简称ADS)模式等。
其中,ADS模式的液晶显示器主要是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场,使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转,从而提高了液晶工作效率并增大了透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质,具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。
以ADS模式的TFT-LCD阵列基板为例,该阵列基板包括:一组栅极扫描线和与栅极扫描线垂直交叉的一组数据扫描线,彼此交叉的栅极扫描线和数据扫描线限定了一个像素区。如图1所示,每一个像素区包括形成于基板10之上的栅极11、栅极绝缘层12、有源层13、源极15、漏极16、像素电极14(即板状电极)、钝化层17和公共电极18(即狭缝电极),其中,公共电极18在像素区内具有多个狭缝结构。
在现有阵列基板的制造过程中,形成栅极和栅极扫描线图形,有源层图形,源极、漏极和数据扫描线图形,像素电极图形和过孔图形各需采用一次掩模构图工艺,图1所示的ADS模式的TFT-LCD阵列基板则需采用1+5次掩模构图工艺形成。
形成有源层和像素电极各自均需采用一次掩模构图工艺,而每次掩模构图工艺均包括多个步骤,这无疑使得阵列基板的制造工艺较为繁琐,产能较难提升。
发明内容
本发明提供了一种阵列基板、显示面板及阵列基板的制造方法,用以解决现有技术中阵列基板的制造工艺较为繁琐,产能较难提升的技术问题。
本发明阵列基板,包括多个像素单元,每个像素单元包括薄膜晶体管、透明导电金属层和像素电极,所述薄膜晶体管包括栅极、有源层、源极和漏极,其中,
所述有源层位于栅极的上方或者下方;
所述透明导电金属层与有源层层叠接触;
所述源极和漏极形成有源层的沟道,且所述漏极与像素电极连接。
本发明显示装置,包括前述技术方案所述的阵列基板。
本发明阵列基板的制造方法,包括:
在基板上沉积透明导电薄膜和有源层薄膜,通过一次半色调或灰色调掩模构图工艺形成像素电极图形、透明导电金属层图形和有源层图形,其中,所述透明导电金属层与有源层层叠接触。
在本发明技术方案中,由于透明导电金属与有源层为层叠接触,因此,在阵列基板的制造过程中,在沉积透明导电薄膜和有源层薄膜之后,只需通过一次半色调或灰色调掩模构图工艺即可形成像素电极图形和有源层图形,对比于现有技术,省去了一次掩模构图工艺,大大简化了生产工艺,同时也减少了该次掩模构图工艺可能带来的产品缺陷,大大提高了产能。
附图说明
图1为现有阵列基板结构示意图(ADS模式);
图2为本发明阵列基板结构示意图(以ADS模式为例);
图3为本发明阵列基板制造方法流程示意图(以ADS模式为例);
图4为本发明阵列基板制造方法中半色调掩模工艺流程示意图;
图5a~图5e为基板的半色调掩模工艺示意图;
图6为本发明阵列基板结构示意图(以TN模式为例)。
附图标记:
10-透明基板11-栅极
12-栅极绝缘层13-有源层(现有技术)
14-像素电极(现有技术)15-源极
16-漏极17-钝化层
18-公共电极23-有源层
24-像素电极230-有源层薄膜
240-透明导电薄膜100-光刻胶
25-透明导电金属层
具体实施方式
为了解决现有技术中阵列基板的制造工艺较为繁琐,产能较难提升的技术问题,本发明实施例提供了一种阵列基板、显示面板及阵列基板的制造方法。
如图6所示实施例,本发明阵列基板,包括多个像素单元(图中以一个像素单元的截面为例),每个像素单元包括薄膜晶体管、透明导电金属层25和像素电极24,所述薄膜晶体管包括栅极11、有源层23、源极15和漏极16,其中,
所述有源层23位于栅极11的上方或者下方;
所述透明导电金属层25与有源层23层叠接触;
所述源极15和漏极16形成有源层23的沟道,且所述漏极16与像素电极24连接。
本发明所述阵列基板的类型不限,例如可以为底栅型阵列基板(此时有源层位于栅极的上方)或者顶栅型阵列基板(此时有源层位于栅极的上方)等。阵列基板各膜层的结构位置可以有很多种变化,只要制作出显示装置驱动所必要的元素(比如栅极、有源层、源极、漏极和像素电极等),确保显示装置正常驱动即可。所述透明导电金属层和像素电极的材质优选相同,这样,像素电极和透明导电金属层便可以同层制作形成。
以底栅型阵列基板为例,还具体包括:透明基板10、与栅极11连接的栅极扫描线(图中未示出)、栅极绝缘层12、与源极15连接的数据扫描线(图中未示出),其中,
所述栅极11和栅极扫描线,形成于透明基板10之上;
所述栅极绝缘层12,形成于栅极11和栅极扫描线之上并覆盖基板;
所述像素电极24和透明导电金属层25,形成于栅极绝缘层12之上,且所述透明导电金属层25位于栅极11的上方;
所述有源层23,形成于透明导电金属层25之上并与透明导电金属层25层叠接触;
所述源极15和漏极16形成于有源层23之上。
在本发明实施例的阵列基板中,透明导电金属层25的存在可以使像素电极24和有源层23在一次半色调或灰色调掩模构图工艺中形成,透明导电金属层25的存在对阵列基板的功能不产生影响。对比于现有技术,省去了一次掩模构图工艺,大大简化了生产工艺,同时也减少了该次掩模构图工艺可能带来的产品缺陷,大大提高了产能。
在图6所示的实施例中,所述阵列基板还进一步包括钝化层17,所述钝化层17位于薄膜晶体管、透明导电金属层25和像素电极24所组成的结构之上并覆盖基板,且在基板的信号引导区具有过孔(图中未示出)。该结构阵列基板可应用于TN模式的显示装置,在TN模式的显示装置中,公共电极设置于彩膜基板上。
请参考图2所示,当阵列基板为ADS模式的阵列基板时,所述阵列基板还进一步包括:
钝化层17,形成于源极15、漏极16和数据扫描线之上并覆盖基板,且在基板的信号引导区具有过孔(图中未示出);
公共电极18,形成于钝化层17之上,且具有狭缝结构。
在本发明的其它实施例中,阵列基板的结构还可以是,像素电极具有狭缝结构,阵列基板进一步包括公共电极,该公共电极位于像素电极的下方并与像素电极绝缘隔离。当阵列基板为ADS模式时,只要保证上面的电极具有狭缝结构,下面的电极具有板状结构即可。公共电极可以位于栅极绝缘层的上方,或者与栅极在一次构图工艺中形成均可。
本发明实施例还提供了一种显示装置,其包括上述任意一种阵列基板。所述显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明阵列基板的制造方法,包括:
在基板上沉积透明导电薄膜和有源层薄膜,通过一次半色调或灰色调掩模构图工艺形成像素电极图形、透明导电金属层图形和有源层图形,其中,所述透明导电金属层与有源层层叠接触。
所述通过一次半色调或灰色调掩模构图工艺形成像素电极图形、透明导电金属层图形和有源层图形,包括:
本发明具体可以采用具有全透光区、半透光区和不透光区的掩模板对基板进行曝光,其中,全透光区对应的位置全部曝光,刻蚀后露出栅极绝缘层;半透光区对应的位置部分曝光,刻蚀后形成像素电极图形;不透光区对应的位置未曝光,刻蚀后形成透明导电金属层图形和有源层图形。
掩模板的半透光区起半透光效果的可以为两个狭缝,掩模时利用双缝干涉达到部分透光,也可以为使光线部分透过的半透膜;半透膜的光线透过率为35%~45%;半透膜材质可以为铬、镆、锰的氧化物、氮化物、有机玻璃、透明热固性高分子材料、或甲基戊烯聚合物。
在形成像素电极图形、透明导电金属层图形和有源层图形的步骤之前,进一步包括:
在透明基板上形成栅极及栅极扫描线图形和栅极绝缘层;
在形成像素电极图形、透明导电金属层图形和有源层图形之后,进一步包括:
在有源层之上形成相对而置的、并形成沟道的源极和漏极图形,同时在基板上形成与源极连接的数据扫描线图形;
在源极、漏极和数据扫描线之上形成覆盖基板的钝化层,并在基板的信号引导区形成过孔图形。
其中,制造ADS模式的阵列基板,在形成钝化层和过孔图形之后,进一步包括:
在钝化层之上形成具有狭缝结构的公共电极图形。
图2所示的ADS模式的TFT-LCD阵列基板共需采用1+4次掩模构图工艺形成,如图3所示,其主要实施过程包括:
步骤201:在透明基板上沉积栅金属薄膜,通过第一次掩模构图工艺形成栅极和栅极扫描线图形;
栅金属薄膜可以采用铝、铬、钨、钽、钛、钼或钼镍的单层薄膜,也可以采用由上述单层薄膜构成的多层复合薄膜,对于金属薄膜,沉积方式采用物理气相淀积的方式成膜。
步骤202:在完成步骤201的基板上沉积栅极绝缘层、第一透明导电薄膜和有源层薄膜,通过一次半色调掩模构图工艺(即第二次掩模构图工艺)形成像素电极图形、透明导电金属层图形和有源层图形;
栅极绝缘层的绝缘成分可以为氮化硅等,采用化学气相淀积的方式成膜;第一透明导电薄膜材质可以为氧化铟锡等,采用物理气相淀积的方式成膜;有源层薄膜材质可以为非晶硅、氢化非晶硅等,采用化学气相淀积法成膜。
步骤203:在完成步骤202的基板上沉积源漏电极金属薄膜,通过第三次掩模构图工艺形成源极、漏极和数据扫描线图形;
源漏电极金属薄膜可以采用铝、铬、钨、钽、钛、钼或钼镍的单层薄膜,也可以采用由上述单层薄膜构成的多层复合薄膜,对于金属薄膜,沉积方式采用物理气相淀积的方式成膜。
步骤204:在完成步骤203的基板上沉积钝化层,通过第四次掩模构图工艺形成信号引导区过孔图形;
钝化层材质可选用氮化硅等。
步骤205:在完成步骤204的基板上沉积第二透明导电薄膜,通过第五次掩模构图工艺形成具有狭缝结构的公共电极图形;
第二透明导电薄膜可采用与第一透明导电薄膜相同的材质,例如氧化铟锡等,采用物理气相淀积的方式成膜。
结合图4和图5a至图5e所示,步骤202具体为:
步骤2021:在完成步骤201的基板上采用化学气相淀积的方式沉积栅极绝缘层12、采用物理气相淀积的方式沉积第一透明导电薄膜(即透明导电薄膜240)和采用化学气相淀积的方式沉积有源层薄膜230;
步骤2022:在完成步骤2021的基板上涂覆一层正性光刻胶100;
步骤2023:使用设计的具有全透光区、半透光区和不透光区结构的掩模板对基板进行曝光,其中,掩模板的全透光区对应的光刻胶全部曝光,半透光区对应的光刻胶部分曝光,不透光区对应的光刻胶未被曝光;
步骤2024:对完成步骤2023的基板进行显影,完全曝光的区域光刻胶溶解并去除,部分曝光的区域光刻胶部分溶解并去除,未曝光区域光刻胶100保留,成为保护掩模,如图5a所示;
步骤2025:对完成步骤2024的基板进行刻蚀,完全曝光区域刻蚀后露出栅极绝缘层12,如图5b所示;
步骤2026:对完成步骤2025的基板通过灰化工艺去除部分曝光区域残留的部分光刻胶,暴露出该区域的有源层薄膜230,对该薄膜进行刻蚀,至暴露出像素电极24,如图5c和图5d所示;
步骤2027:将完成步骤2026的基板的残余光刻胶剥离,暴露出有源层23,如图5e所示。
所述步骤202中形成的所述像素电极图形可以具有狭缝结构,因此,在步骤S202之前可以包括:形成位于需要形成的狭缝结构的所述像素电极的下方并与所述像素电极绝缘隔离的公共电极图形。
当需要制备的阵列基板为ADS模式时,制备时只要保证上面的电极具有狭缝结构,下面的电极具有板状结构即可。公共电极可以位于栅极绝缘层的上方,或者与栅极在一次构图工艺中形成均可。
本发明阵列基板的制造方法同样适用于TN模式(经步骤201~204可生产出TN模式的阵列基板)、IPS模式等其他显示模式。图6所示的TN模式的阵列基板,通过一次半色调掩模构图工艺即可形成像素电极图形和有源层图形。
在本发明技术方案中,由于透明导电金属层与有源层层叠接触,因此,在阵列基板的制造过程中,在沉积透明导电薄膜和有源层薄膜之后,只需通过一次半色调掩模构图工艺即可形成像素电极图形和有源层图形,对比于现有技术,省去了一次掩模构图工艺,大大简化了生产工艺,同时也减少了该次掩模构图工艺可能带来的产品缺陷,大大提高了产能。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。

Claims (11)

1.一种阵列基板,其特征在于,包括多个像素单元,每个像素单元包括薄膜晶体管、透明导电薄膜层和像素电极,所述薄膜晶体管包括栅极、有源层、源极和漏极,其中,
所述有源层位于栅极的上方或者下方;
所述透明导电薄膜层与有源层层叠接触;
所述源极和漏极形成有源层的沟道,且所述漏极与像素电极连接;
所述阵列基板还包括:透明基板、与栅极连接的栅极扫描线、栅极绝缘层、与源极连接的数据扫描线,其中,
所述栅极和栅极扫描线,形成于透明基板之上;
所述栅极绝缘层,形成于栅极和栅极扫描线之上并覆盖基板;
所述像素电极和透明导电薄膜层,形成于栅极绝缘层之上,且所述透明导电薄膜层位于栅极的上方;
所述有源层,形成于透明导电薄膜层之上并与透明导电薄膜层层叠接触;
所述源极和漏极形成于有源层之上。
2.如权利要求1所述的阵列基板,其特征在于,所述透明导电薄膜层和像素电极材质相同。
3.如权利要求1所述的阵列基板,其特征在于,进一步包括钝化层,所述钝化层位于薄膜晶体管、透明导电薄膜层和像素电极所组成的结构之上并覆盖基板,且在基板的信号引导区具有过孔。
4.如权利要求3所述的阵列基板,其特征在于,进一步包括:形成于钝化层之上且具有狭缝结构的公共电极。
5.如权利要求3所述的阵列基板,其特征在于,进一步包括:位于像素电极的下方并与像素电极绝缘隔离的公共电极,其中,所述像素电极具有狭缝结构。
6.一种显示装置,其特征在于,包括如权利要求1~5任一项所述的阵列基板。
7.一种阵列基板的制造方法,其特征在于,包括:
在透明基板上形成栅极和与之连接的栅极扫描线;
形成栅极绝缘层,所述栅绝缘层形成在所述栅极和栅极扫描线之上并覆盖基板;
在栅极绝缘层上沉积透明导电薄膜和有源层薄膜,通过一次半色调或灰色调掩模构图工艺形成像素电极图形、透明导电薄膜层图形和有源层图形,其中,所述透明导电薄膜层位于栅极的上方,所述有源层位于所述透明导电薄膜层之上并与所述透明导电薄膜层层叠接触;
在有源层之上形成相对而置的、并形成沟道的源极和漏极图形,同时在基板上形成与源极连接的数据扫描线图形;
将所述漏极与像素电极连接。
8.如权利要求7所述的制造方法,其特征在于,所述通过一次半色调或灰色调掩模构图工艺形成像素电极图形、透明导电薄膜层图形和有源层图形的步骤,包括:
采用具有全透光区、半透光区和不透光区的掩模板对基板进行曝光,其中,全透光区对应的位置全部曝光,刻蚀后露出栅极绝缘层;半透光区对应的位置部分曝光,刻蚀后形成像素电极图形;不透光区对应的位置未曝光,刻蚀后形成透明导电薄膜层图形和有源层图形。
9.如权利要求7所述的制造方法,其特征在于,
在形成像素电极图形、透明导电薄膜层图形和有源层图形的步骤之后,进一步包括:
在源极、漏极和数据扫描线之上形成覆盖基板的钝化层,并在基板的信号引导区形成过孔图形。
10.如权利要求9所述的制造方法,其特征在于,在源极、漏极和数据扫描线之上形成覆盖基板的钝化层,并在基板的信号引导区形成过孔图形的步骤之后,进一步包括:
在钝化层之上形成具有狭缝结构的公共电极图形。
11.如权利要求7所述的制造方法,其特征在于,所述形成像素电极图形具有狭缝结构,所述形成像素电极图形、透明导电薄膜层图形和有源层图形的步骤之前包括:形成位于需要形成的狭缝结构的所述像素电极的下方并与所述像素电极绝缘隔离的公共电极图形。
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