CN103996661B - Method for generating SRAM layout - Google Patents
Method for generating SRAM layout Download PDFInfo
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- CN103996661B CN103996661B CN201410253555.7A CN201410253555A CN103996661B CN 103996661 B CN103996661 B CN 103996661B CN 201410253555 A CN201410253555 A CN 201410253555A CN 103996661 B CN103996661 B CN 103996661B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
The invention provides a method for generating an SRAM layout. The method comprises the steps that firstly, a first unit is formed; secondly, the first unit is copied, so that a second unit is formed; thirdly, the first unit is connected with the second unit, so that an SRAM is formed; finally, identical parameters in the SRAM are grouped, and then the SRAM layout can be automatically generated. In this way, different sizes of SRAM layouts can be effectively generated, design of the SRAM layout is simplified, so that the error rate caused during manual design of the layout is reduced, and the implementation time of the SRAM layout is shortened.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, to a kind of generation method of SRAM domain.
Background technology
SRAM (Static Random Access Memory, static random storage memory) is as long as be a kind of just power supply
Keep the semiconductor memory of data.It is fast and excellent with CMOS logic process compatible etc. that SRAM has low-power consumption, data access speed
Point, is widely used in various electronic devices.Therefore, SRAM is the indispensable portion of any one logic semiconductor processing procedure
Point.
Basic sram cell is by two cross-linked phase inverters and two access transistor (usually NMOS crystal
Pipe) constitute, belong to typical six layer transistor SRAM (6T SRAM).Specifically, SRAM can be divided into the first phase inverter
(Inverter), the second phase inverter and two nmos pass transistors (referred to as NPASS), the wherein first phase inverter is brilliant by a PMOS
Body pipe and the first nmos pass transistor composition, the second phase inverter is made up of the second PMOS transistor and the second nmos pass transistor, adds
Two nmos pass transistors are made up of six transistors (Transistor) altogether.
The generation method of traditional SRAM domain is respectively each transistor to be generated by software, is then combined into
SRAM.Although the generation method of traditional SRAM domain can meet the design requirement of current SRAM domain, due in SRAM
There are 6 transistors, and each transistor all has multiple sizes to need definition, such as grid size, active area dimensions and note
Enter layer and the size of well layer is required to define, therefore, the generation method of traditional SRAM domain is inefficient, especially when SRAM needs
When size being modified, the size that needs are changed is more, and such manual operation is often to SRAM version map generalization
Produce unnecessary mistake, and take a substantial amount of time and energy.
Content of the invention
It is an object of the invention to provide a kind of generation method of SRAM domain, identical parameter can be sorted out, realize
Automatically generating of SRAM domain, improves efficiency.
To achieve these goals, the present invention proposes a kind of generation method of SRAM domain, including step：
Define the shape and size of the first inverter gate；
By the shape and size of described first inverter gate define the first PMOS transistor in the first phase inverter and
The shape and size of the first nmos pass transistor active area；
Define the shape and size of first input end NMOS gate；
Define described first input end NMOS active area with the shape and size of described first input end NMOS gate
Shape and size；
Define the first implanted layer and the shape of the first well layer with the shape and size of described first input end NMOS active area
Shape and size；
So that described first PMOS transistor and the drain electrode of the first nmos pass transistor is linked together, make described first input end
The active area of NMOS and the first nmos pass transistor links together, and makes described first input end NMOS and a NMOS crystal
The drain electrode of pipe also links together, thus constituting first module；
Replicate described first module, rotate 180 degree, form second unit；
The first PMOS transistor drain electrode in described first module is made to be connected with the second inverter gate in second unit,
The second PMOS transistor drain electrode in described second unit is made to be connected with the first inverter gate in first module, thus generating
SRAM domain.
Further, through hole line is passed through in the drain electrode of described first PMOS transistor and the first nmos pass transistor and metal connects
Line links together.
Further, the drain electrode of described first input end NMOS and the first nmos pass transistor is connected to one by through hole line
Rise.
Further, the second anti-phase grid in the first PMOS transistor drain electrode and second unit in described first module
Pole is passed through through hole line and is connected.
Further, the first anti-phase grid in the second PMOS transistor drain electrode and first module in described second unit
Pole is passed through through hole line and is connected.
Further, described through hole line is all drawn by metal connecting line.
Compared with prior art, the beneficial effects are mainly as follows：It is initially formed first module, then replicate first
Unit forms second unit, connects first module and second unit constitutes SRAM, identical parameter in SRAM is sorted out, Ke Yishi
Automatically generating such that it is able to efficiently complete the realization of different size size SRAM domain of existing SRAM domain, simplifies SRAM domain
Design, thus reducing the error rate producing in engineer's layout process, and shorten SRAM domain and realize the time.
Brief description
Fig. 1 is the flow chart of the generation method of SRAM domain in one embodiment of the invention；
Fig. 2 is the structural representation of first module in one embodiment of the invention；
Fig. 3 is the structural representation of SRAM domain in one embodiment of the invention.
Specific embodiment
Generation method below in conjunction with the SRAM domain to the present invention for the schematic diagram is described in more detail, and wherein represents
The preferred embodiments of the present invention are it should be appreciated that those skilled in the art can change invention described herein, and still real
The advantageous effects of the existing present invention.Therefore, description below be appreciated that widely known for those skilled in the art, and simultaneously
Not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
It is necessary to make a large amount of implementation details to realize the specific objective of developer in sending out, such as according to relevant system or relevant business
Limit, another embodiment is changed into by an embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only routine work to those skilled in the art.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Seek book, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is all in the form of very simplification and all using non-
Accurately ratio, only in order to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
The core concept of the present invention is, because 6T SRAM has the first phase inverter, first input end NMOS, second anti-phase
Device and the second input NMOS composition, and in the first phase inverter the first nmos pass transistor, the first PMOS transistor respectively and
The second nmos pass transistor in second phase inverter, the second PMOS transistor parameter are identical, and first input end NMOS
Also identical with the parameter of the second input NMOS, therefore can be sorted out having a large amount of identical parameters, be formed the
Unit one, then replicates first module and carries out rotation acquisition second unit, first module and second unit are attached
To obtain 6T SRAM domain.
Specifically, refer to Fig. 1, Fig. 2 and Fig. 3, Fig. 1 is the stream of the generation method of SRAM domain in one embodiment of the invention
Cheng Tu, Fig. 2 are the structural representation of first module in one embodiment of the invention, and Fig. 3 is SRAM domain in one embodiment of the invention
Structural representation；In the present embodiment, the generation method of the SRAM domain of proposition, including step：
S100：Define the shape and size of the first inverter gate 61；
In the step s 100, the shape and size of the first inverter gate 61 can be determined according to specific technological requirement
Fixed, different grid 61 sizes can obtain various sizes of SRAM domain.
S200：Define the PMOS in the first phase inverter 10 by the shape and size of described first inverter gate 61
Transistor 12 and the shape and size of the first nmos pass transistor 11 active area；
S300：Define the shape and size of first input end NMOS gate 62；
Likewise, in step S300, the shape and size of first input end NMOS gate 62 can be according to specific work
Skill requires to determine, different first input end NMOS gate 62 sizes can obtain various sizes of SRAM domain.
S400：Define described first input end NMOS30 with the shape and size of described first input end NMOS gate 62
The shape and size of active area；
S500：Define the first implanted layer 13 and first with the shape and size of described first input end NMOS30 active area
The shape and size of well layer 14；
S600：So that described first PMOS transistor 12 and the drain electrode of the first nmos pass transistor 11 is linked together, make described
The active area of first input end NMOS30 and the first nmos pass transistor 11 links together, and makes described first input end
The drain electrode of NMOS30 and the first nmos pass transistor 11 also links together, thus constituting first module, as shown in Figure 2；
S700：Replicate described first module, rotate 180 degree, form second unit；
Wherein, described second unit includes the second phase inverter 20, the second input NMOS40, the second implanted layer and second
Well layer, described second phase inverter 20 includes the second inverter gate 63, the first PMOS transistor 22 and the first nmos pass transistor
21, described second input NMOS40 includes the second input NMOS gate 64, as shown in figure 3, here, letter for accompanying drawing
Clean, eliminate the first implanted layer 13, the first well layer 14, the second implanted layer, the second well layer and part metals line in Fig. 3.
S800：The first PMOS transistor 12 in described first module is made to drain and the second anti-phase grid in second unit
Pole 63 is connected, and so that the second PMOS transistor 22 in described second unit is drained and the first inverter gate 61 in first module
It is connected, thus generating SRAM domain.
In the present embodiment, through hole line is passed through in the drain electrode of described first PMOS transistor 12 and the first nmos pass transistor 11
50 and metal connecting line 70 link together；Through hole is passed through in the drain electrode of described first input end NMOS30 and the first nmos pass transistor 11
Line 50 links together；The second phase inverter in the first PMOS transistor 12 drain electrode and second unit in described first module
Grid 63 passes through through hole line 50 and is connected；In described second unit in the second PMOS transistor drain electrode 22 and first module the
One inverter gate 61 is passed through through hole line 50 and is connected；In actual production, described through hole line 50 is all drawn by metal connecting line 70
Go out, to facilitate external circuitses.
The SRAM domain generation method being proposed using the present embodiment, is realized using SMARTCELL software, need not be directed to
Each transistor carries out the modification of size and definition it is only necessary to the less independent variable of modification, the such as shape of the first inverter gate
The shape and size of shape and size, first input end NMOS gate can achieve the whole shape and size to 6 transistors
Modification.Therefore, it can more efficiently obtain various sizes of SRAM, reduce the mistake that manual amendment is likely to occur compared with multiparameter
Probability.
To sum up, in the generation method of SRAM domain provided in an embodiment of the present invention, it is initially formed first module, then replicates
First module forms second unit, connects first module and second unit constitutes SRAM, identical parameter in SRAM is sorted out, can
To realize the automatically generating such that it is able to efficiently complete the realization of different size size SRAM domain of SRAM domain, simplify SRAM
The design of domain, thus reducing the error rate producing in engineer's layout process, and shortens SRAM domain and realizes the time.
Above are only the preferred embodiments of the present invention, the present invention is not played with any restriction effect.Any affiliated
Those skilled in the art, in the range of without departing from technical scheme, to the invention discloses technical scheme and
Technology contents make any type of equivalent or modification etc. and change, and all belong to the content without departing from technical scheme, still
Belong within protection scope of the present invention.
Claims (6)
1. a kind of generation method of SRAM domain, including step：
Define the shape and size of the first inverter gate；
Define the first PMOS transistor and first in the first phase inverter by the shape and size of described first inverter gate
The shape and size of nmos pass transistor active area；
Define the shape and size of first input end NMOS gate；
Define the shape of described first input end NMOS active area with the shape and size of described first input end NMOS gate
And size；
With the shape and size of described first input end NMOS active area define the first implanted layer and the first well layer shape and
Size；
So that the drain electrode of described first PMOS transistor and the drain electrode of the first nmos pass transistor is linked together, make described first input
The active area of the active area of end NMOS and the first nmos pass transistor links together, and makes the leakage of described first input end NMOS
The drain electrode of pole and the first nmos pass transistor also links together, thus constituting first module；
Replicate described first module, rotate 180 degree, form second unit；
So that the first PMOS transistor drain electrode in described first module is connected with the second inverter gate in second unit, make institute
The the second PMOS transistor drain electrode stated in second unit is connected with the first inverter gate in first module, thus generating SRAM
Domain.
2. the generation method of SRAM domain as claimed in claim 1 is it is characterised in that the drain electrode of described first PMOS transistor
Drain electrode with the first nmos pass transistor is linked together by through hole line and metal connecting line.
3. the generation method of SRAM domain as claimed in claim 2 is it is characterised in that the drain electrode of described first input end NMOS
Drain electrode with the first nmos pass transistor is linked together by through hole line.
4. the generation method of SRAM domain as claimed in claim 3 is it is characterised in that a PMOS in described first module
Transistor drain is connected by through hole line with the second inverter gate in second unit.
5. the generation method of SRAM domain as claimed in claim 4 is it is characterised in that the 2nd PMOS in described second unit
Transistor drain is connected by through hole line with the first inverter gate in first module.
6. the generation method of SRAM domain as claimed in claim 5 is it is characterised in that described through hole line is all connected by metal
Line is drawn.
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| CN201410253555.7A CN103996661B (en) | 2014-06-09 | 2014-06-09 | Method for generating SRAM layout |
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| CN201410253555.7A CN103996661B (en) | 2014-06-09 | 2014-06-09 | Method for generating SRAM layout |
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| CN103996661B true CN103996661B (en) | 2017-02-08 |
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| CN110852031B (en) * | 2019-07-02 | 2023-05-16 | 深圳信息职业技术学院 | Method for realizing sharing of active areas in stick diagram design |
| CN115394844B (en) * | 2022-10-26 | 2023-04-07 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015614A (en) * | 1999-06-30 | 2001-01-19 | Matsushita Electronics Industry Corp | Semiconductor storage device |
| CN1763928A (en) * | 2004-10-18 | 2006-04-26 | 中国科学院微电子研究所 | Rapid comprehensive design method based on static random access memory |
| CN101859774A (en) * | 2005-10-07 | 2010-10-13 | 株式会社瑞萨科技 | Semiconductor device and manufacture method thereof |
| CN102136479A (en) * | 2010-01-21 | 2011-07-27 | 上海华虹Nec电子有限公司 | Sram unit |
| CN103208496A (en) * | 2012-01-12 | 2013-07-17 | 台湾积体电路制造股份有限公司 | SRAM cells and arrays |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8853791B2 (en) * | 2006-11-06 | 2014-10-07 | Infineon Technologies Ag | SRAM memory cell having a dogleg shaped gate electrode structure |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015614A (en) * | 1999-06-30 | 2001-01-19 | Matsushita Electronics Industry Corp | Semiconductor storage device |
| CN1763928A (en) * | 2004-10-18 | 2006-04-26 | 中国科学院微电子研究所 | Rapid comprehensive design method based on static random access memory |
| CN101859774A (en) * | 2005-10-07 | 2010-10-13 | 株式会社瑞萨科技 | Semiconductor device and manufacture method thereof |
| CN102136479A (en) * | 2010-01-21 | 2011-07-27 | 上海华虹Nec电子有限公司 | Sram unit |
| CN103208496A (en) * | 2012-01-12 | 2013-07-17 | 台湾积体电路制造股份有限公司 | SRAM cells and arrays |
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