CN103685086B - Baseband signal processor supporting multi-chip architecture and processing method of baseband signal processor - Google Patents
Baseband signal processor supporting multi-chip architecture and processing method of baseband signal processor Download PDFInfo
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- CN103685086B CN103685086B CN201210330012.1A CN201210330012A CN103685086B CN 103685086 B CN103685086 B CN 103685086B CN 201210330012 A CN201210330012 A CN 201210330012A CN 103685086 B CN103685086 B CN 103685086B
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Abstract
The invention provides a baseband signal processor supporting a multi-chip architecture. The baseband signal processor comprises a main control unit, a radio frequency interface unit, a data diversity unit for the collection, packaging, unpacking and distribution of data exchange, control parameters and feedback parameters among all baseband signal processors, a chip interconnection interface unit for the high-speed data exchange among the baseband signal processors and necessary interaction of handshake signals, a symbol-level processing unit, an FFT (Fast Fourier Transform) correcting unit for correcting blocked FFT data based on an FFT time extraction algorithm to obtain high-order fast Fourier transform results, a code block-level processing unit and a memory unit. The invention further provides a processing method of the baseband signal processor. Based on the structure of the traditional baseband signal processor, part of processing units are added, so that the high-bandwidth baseband signal processor can be established by adopting the multi-chip architecture under the condition of increasing less processing resource and processing cost.
Description
Technical field
The present invention relates to wireless communication field, more particularly to a kind of baseband signal processor for supporting multi-chip framework and its
Processing method.
Background technology
Current existing baseband signal processor is substantially one chip solution, once communication bandwidth beyond
The disposal ability of single baseband signal processor, original baseband signal processor will be unable to treatment, substantially reduces base band and leads to
Believe the product life cycle of processor.
In addition the bandwidth of follow-on Wireless Broadband Communication Systems is more and more wider, meets the wireless broadband communication system of 4G standards
System has been planned for the bandwidth of 100MHz, and with the application of MIMO technology, if still using baseband signal processor
One chip solution, its cost will be more and more higher, also more and more impracticable, be using the communication terminal of highest bandwidth after all
Few scene.
The content of the invention
In order to solve above-mentioned problem, the present invention proposes a kind of baseband signal processor for supporting multi-chip framework, for
The communication system of main flow communication bandwidth and speed in the present or future regular period, baseband communication processor of the invention is used
Single chip solution；For special high bandwidth communication systems, baseband communication processor of the present invention using multi-chip scheme come
Realize the disposal ability beyond single baseband communication processor.
It is proposed by the present invention support multi-chip framework baseband signal processor, its composition structure as shown in figure 1, including with
Lower part：
1.1, main control unit, for controlling the unit in scheduling baseband signal processor, at communication protocol message
Reason, and control peripheral unit；
1.2, radio frequency interface unit, for being communicated with outside radio-frequency apparatus, being provided to radio-frequency apparatus needs to send
Base band sample data, receive radio-frequency apparatus output base band sample data；
1.3, data diversity unit, according to the configuration of main control unit, needs mass data to exchange in base band collaboration treatment
Node, there is provided the collection packing and distribution of unpacking of data exchange between each processor, above-mentioned data exchange has three keys
Node：Base band sample data switching node between radio frequency interface unit and symbol level processing unit, symbol level processing unit and
Time domain, frequency domain data switching node between FFT correction unit, the input and output number of code block level processing unit
According to switching node；Data diversity unit also provides the collection packing of the control parameter and feedback parameter between each processor and tears open
Bag distribution；
1.4, chip interconnecting interface unit is exchanged and necessary letter of shaking hands for the high-speed data between baseband signal processor
Number interaction, the main control for including receiving main control unit receives the packet of outgoing from data diversity unit, or to number
There is provided according to diversity unit and be received from the packet that other baseband signal processors send；It is additionally operable to other baseband signal processors
Data request signal is sent, or records the request of data that other baseband signal processors send, to Main Control Unit or number
According to diversity unit feedback etc.；
1.5, symbol level processing unit, the treatment for completing baseband signalling level, the treatment includes the load of up-link
Ripple mapping, multiple antennas transmission processe, inverse fast fourier transform, gain control, shaping filter etc., and downlink go it is straight
Stream, correcting frequency deviation, FFT, multiple antennas reception processing, carrier wave demapping etc.；
1.6, FFT（FFT）Correction unit, according to the configuration of main control unit, the time based on FFT takes out
Take（DIT）Algorithm, the FFT data to piecemeal treatment are corrected, and obtain high-order FFT knot
Really, the high-order FFT beyond single baseband signal processor FFT disposal abilities is realized；
1.7, code block level processing unit, the treatment for completing channel data block, the treatment includes adding for up-link
Disturb, channel coding, modulation mapping, code expand, spread spectrum, channel synthesis etc., and downlink channel estimation, Channel Detection, frequency
Deflection correction, modulation demapping, channel decoding, descrambling etc.；
1.8, memory cell, as data diversity unit, symbol level processing unit, FFT（FFT）School
Data exchange caching between positive unit, code block level processing unit.
Preferably, above-mentioned baseband signal processor possesses two kinds of mode of operations of main equipment and slave unit.Further, it is described
Chip interconnecting interface unit uses the high-speed bus for chip chamber interconnection, according to the configuration of main control unit, there is provided Zhu Congmo
Formula, supports duplex or half-duplex operation.The usual high-speed bus can use the parallel bus interface based on double digit rate,
Existing standard high speed interconnecting interface can be used, coordinates interaction handshake, realize that chip chamber is interconnected at a high speed.
Preferably, above-mentioned baseband signal processor also includes external memory interface, for the outer of the memory cell
Portion extends.
Based on above-mentioned baseband signal processor, the present invention also proposes that one kind cooperates between multiple baseband signal processors and realizes
Baseband processing method, the method is：
For downlink, comprise the following steps：
A.1, baseband signal processor main equipment receives the base band sample data from radio-frequency apparatus, removes CP（Cyclic Prefix）
Afterwards, the decimation in time algorithm based on FFT does piecemeal to the base band sample data, and high-order FFT is decomposed into multiple low orders
FFT, then it is distributed to each baseband signal processor（Including BBP main equipment）Realize low order FFT and symbol
Other treatment of number level processing stage, such as remove direct current, frequency deviation time domain correlation, these treatment before FFT, for each
Sampled point is required for treatment, does not interfere with the correction result of FFT；Or if each baseband signal processor can be received
To the base band sample data from radio-frequency apparatus, then each baseband signal processor is based on the decimation in time algorithm of FFT and selects out
The base band sample data for needing present processor to process carries out its elsewhere of low order FFT and above-mentioned symbol level processing stage
Reason；
A.2, each baseband signal processor（Including BBP main equipment）Collect the low order FFT of above-mentioned piecemeal treatment
Delta data, the decimation in time based on FFT（DIT）Algorithm, the low order FFT delta datas to piecemeal treatment are corrected, and obtain high
Rank FFT result of variations, then the frequency domain data completion subcarrier solution for needing present processor to process is selected out to high-order FFT result of variations
Mapping, channel estimation, Channel Detection, correcting frequency deviation, modulation demapping, channel decoding, descrambling, the load of final output physical layer
Data；
A.3, physical layer load data is carried out Preliminary Analysis by each baseband signal processor, by control message and business number
According to classification, baseband signal processor main equipment, Base-Band Processing are submitted to by data diversity unit and chip interconnecting interface unit
Device main equipment collects whole Physical Layer Service Datas, and carries out communication protocol message treatment, completes downlink treatment；
For up-link, comprise the following steps：
B.1, each baseband signal processor receives the physical layer processed the need for baseband signal processor main equipment is distributed
Load data, scrambled, channel coding, modulation mapping, code expand, spread spectrum and channel mapping, obtain physical layer frequency domain data；
B.2, BBP main equipment collects each baseband signal processor（Including BBP main equipment）Physics
Layer frequency domain data, the decimation in time based on FFT（DIT）Algorithm does piecemeal, and high-order IFFT conversion is decomposed into multiple low order IFFT
Conversion, is distributed to each baseband signal processor（Including BBP main equipment）Low order IFFT conversion is done, because IFFT is
The inverse operation of FFT, inverse fast fourier transform can utilize the structure of FFT to realize；
B.3, baseband signal processor main equipment collects the low order IFFT conversion data of piecemeal treatment, the time based on FFT
Extraction algorithm is corrected, and obtains high-order IFFT transformation results, then complete plus Cyclic Prefix, the precorrection of frequency deviation time domain, gain control
And shaping filter, base band sample data is sent to radio-frequency apparatus.
At symbol level processing unit, code block level in the baseband signal processor of support multi-chip framework proposed by the present invention
Reason unit, radio frequency interface unit, main control unit and memory cell are common in plain baseband signal processor necessary groups
Into unit.Data diversity unit, chip interconnecting interface unit and FFT correction unit are the present invention in plain baseband signal processor
Upper increased hardcore unit, based on above-mentioned hardcore unit, using method for processing baseband signal proposed by the present invention, can
To realize the communications baseband processor based on multi-chip framework, that is, build the height beyond single baseband signal processor disposal ability
Broadband wireless communication system BBP.
Present invention could apply to LTE, LTE-A is the ofdm system of representative, but is not limited only to ofdm system, but energy
Enough it is applied to carry out all scenario of base band signal process.Realization of the invention is also not limited to certain fixed form, institute
Stating baseband signal processor can be placed in the network element of communication network or communication terminal, it is also possible to be embedded in processor chips
In；Method for processing baseband signal can be realized by running on the software code on baseband signal processor, it is also possible to be passed through
Other hardware devices are realized.
Compared with prior art, the advantage of the invention is that：The present invention is in the structure of traditional baseband signal processor
Increase portion processing unit, improve the extended capability of baseband signal processor, little process resource and treatment can increased
Under the cost of expense, the height beyond single conventional baseband signal processor processes ability is built by the way of multi-chip framework
Bandwidth baseband signal processor.
Brief description of the drawings
Fig. 1 is the composition structural representation of baseband signal processor proposed by the present invention；
Fig. 2 is the typical application drawing of the dual chip framework baseband signal processor of the embodiment of the present invention one；
Fig. 3 is the structural representation of the FFT correction unit of the embodiment of the present invention one；
Fig. 4 is the interconnecting signal figure of the chip interconnecting interface unit of the embodiment of the present invention one；
Fig. 5 is that schematic diagram is realized in the interconnection of the chip interconnecting interface unit of the embodiment of the present invention two.
Specific embodiment
Below in conjunction with the accompanying drawings, the present invention is described in further details by specific embodiment.
The composition structure of baseband signal processor of the invention is as shown in figure 1, wherein at symbol level processing unit, code block level
Reason unit, radio frequency interface unit, main control unit and memory cell are common in plain baseband signal processor necessary groups
Into unit, data diversity unit, chip interconnecting interface unit and FFT correction unit are the present invention in plain baseband signal processor
Upper increased hardcore unit.For the communication system of general communication bandwidth and speed, based on above-mentioned common necessary group
Into unit, bandwidth requirement can be met using single chip solution；For special high bandwidth communication systems, then can be based on above-mentioned
Hardcore unit, a high bandwidth wireless communication system BBP, its disposal ability are built using multi-chip scheme
Beyond the disposal ability of single baseband communication processor, can be very good to meet high bandwidth requirement.
Embodiment one：The application of the baseband signal processor of dual chip framework
Assuming that realizing 4096 points of FFT inside single baseband signal processor of the invention, the nothing of 20MHz bandwidth can be supported
Line wide-band communication system, the present embodiment as a example by supporting the Wireless Broadband Communication Systems of 40MHz bandwidth, using as shown in Figure 2
Dual chip framework, two baseband signal processors can meet the bandwidth requirement of 40MHz using master's one slave pattern cooperation.
Below emphasis describe the present embodiment single baseband signal processor it is increased on plain baseband signal processor
Three hardcore units：Data diversity unit, chip interconnecting interface unit and FFT correction unit.
Data diversity unit：
Data diversity unit needs three of mass data exchange according to the configuration of main control unit in base band collaboration treatment
Key node, there is provided the collection packing of processor swapping data and distribution of unpacking.Above three key node is radio frequency interface
Base band sample data switching node between unit and symbol level processing unit, symbol level processing unit and FFT
Time domain, frequency domain data switching node between correction unit, the inputoutput data switching node of code block level processing unit.Data
Diversity unit is carried out for exchange data by the way of transmission of packing, and packet includes that bag parameter description field, bag data are long
Degree field, bag data payload field.Using shorter data load length（Such as 32byte）, be conducive to shortening data interaction
Postpone.Packet also includes the type for control action, parameter configuration, control command and response message etc. all with packet
Form is interacted between baseband signal processor, under the master control of baseband signal processor main equipment, is completed at communications baseband
Reason.For only need to baseband signal processor main equipment forwarding packet, data diversity unit according to bag in description field from
It is dynamic directly to be forwarded, to reduce the treatment load of main control unit.
FFT（FFT）Correction unit：
FFT corrects configuration of the unit according to main control unit, the decimation in time based on FFT（DIT）Algorithm, to piecemeal treatment
FFT data be corrected, obtain high-order FFT result, realize exceed single baseband signal
The high-order FFT of the high bandwidth wireless communication system of processor FFT disposal abilities.
The FFT correction cellular constructions of the present embodiment, should as shown in figure 3, C represents Cordic operators or complex multiplier in figure
For the phase factor rotation of FFT data stream, sum represents sum adder, and mux provides the bypass path of data.Input XiFor
I-th group of frequency domain value calculated by the FFT streamlines of i-th BBP, the present embodiment is dual chip scene, then i=
0 or 1, the data are fed into each baseband signal processor that cooperates and are used as by chip interconnecting interface unit and data diversity unit
Correction data source；XoiIt is the output of correction Hou i-th tunnels.
Chip interconnecting interface unit：
In order to tackle high-rate wireless data communication collaborative process, chip interconnecting interface unit needs to meet certain communication
Rate requirement.Assuming that payload expense needs 1.62Gbps in the dual chip framework applications of the present embodiment, count in Cooperation controlling etc. its
Its expense, then chip interconnecting interface unit need provide about 1.95Gbps traffic rate.The chip for meeting this requirement is mutually coupled with
Mouth unit can have various implementations, and the present embodiment is using the 66MHz clock frequencies of 16 bit data widths based on double number
Rate（DDR）Parallel bus interface, 2.112Gbps traffic rates can be provided, it is actual realize in order to provide communication redundancy, lead to
Frequently with the ddr mode of 133MHz.
The interconnecting signal figure of the ddr mode of the chip interconnecting interface unit of the present embodiment is as shown in figure 4, clock signal and anti-
Feedback clock signal is used to provide data transmit-receive synchronization, is provided by baseband signal processor main equipment respectively, baseband signal processor
Slave unit is fed back；Reset clear signal is initialized for communications status, and useless or wrong data is removed, by baseband signal
Reason device main equipment is provided；Slave unit selection signal, for baseband signal processor main equipment selection and multiple base band signal process
Any one of device slave unit communicates, and is controlled by baseband signal processor main equipment；Read/write control signals, for controlling to hand over
Mutual data flow, is controlled by baseband signal processor main equipment；Data request signal, for baseband signal processor slave unit
Data interaction is asked, and is provided by baseband signal processor slave unit；Data/address bus, for the transmitted in both directions of data, width depends on
In desired traffic rate, slave unit selection signal is coordinated to avoid bus collision；Master-slave equipment setting signal, for setting core
The mode of operation selection of piece interconnecting interface unit, is main equipment pattern or slave unit pattern.
The chip interconnecting interface unit of the present embodiment is accomplished that the half-duplex operation of chip chamber, and a set of bi-directional data is total
Line is changed to two sets of unidirectional data bus, you can realize the duplex communication of chip chamber.
Embodiment two：Another embodiment of chip interconnecting interface unit
On the basis of embodiment one, the chip interconnecting interface unit of the present embodiment is using an alternate embodiment come real
It is existing.The present embodiment uses the high speed interconnecting interface of existing or future maturation, and mating part handshake realizes that chip chamber is high
Speed interconnection.
The existing high speed interconnecting interface for meeting above-mentioned required communication rate is several just like description below：DigRF V4、
USB3.0, FireWire IEEE 1394-2008 and the C2C technologies of the Arteris companies based on ddr mode.It is mutual in dual chip
Under connection typical case's application, above-mentioned high speed interconnecting interface cooperation interactive handshake as shown in Figure 5 can realize data between dual chip
Exchange at a high speed, these interaction handshake functions are identical with the description in embodiment one.For the interconnecting application of more chips
Scape, will depend on whether existing or future ripe high speed interconnecting interface supports that many device bus are shared.
Embodiment one and embodiment two are that the multi-chip framework baseband signal processor of twin-core sheet form is realized, can be pushed away
The wide way of realization to more chips.Additionally, way of realization of the invention is also not limited to multi-chip way of realization, can with it is many
Chip package（MCP）Technology is combined, by multiple chip crystal（Chip DIE）According to multi-chip proposed by the present invention cooperation form
A chip internal is encapsulated in, the BBP of more high bandwidth wireless communication system is externally realized in the form of single-chip.
Describe citing in detail method for processing baseband signal proposed by the present invention below.
Embodiment three：The method for processing baseband signal of the downlink of 40MHz SISO systems
The present embodiment by taking 40MHz SISO systems as an example, using the dual chip framework baseband signal processor of embodiment one.
External radio frequency chip undertakes wireless signal transmission-receiving function, to baseband signal processor output time-domain sampled data, and receives base
The time domain that band signal processor sends sends sampled data.The present embodiment is only facing a base band using conventional radio frequency chip
Signal processor, you can give two baseband signal processors with output time-domain sampled data simultaneously, but only receive from base band letter
The time domain of number processor main equipment sends sampled data, to avoid interface bus conflict.If that can believe towards multiple base band
The radio frequency chip of number processor interface, then multiple baseband signal processors can carry out data transmit-receive towards radio frequency chip simultaneously.
BBP main equipment also accesses chip external memory using by external memory interface in the present embodiment, to memory cell
Outside extension is carried out, to meet the data exchange buffer size of Large Copacity.
The method for processing baseband signal of the downlink of the present embodiment is comprised the following steps：
Step 3.1：The radio frequency interface unit of baseband signal processor main equipment receives the descending chain of 40MHz SISO systems
Road sample sequence, after removing CP, x（n）, 0≤n≤8191 complete the pretreatment of symbol level processing stage, such as go direct current, frequency deviation
Time domain correlation etc. sends into data diversity unit；Data diversity unit is to sample sequence x（n）, the decimation in time based on FFT（DIT）
Algorithm, the subsequence that 2 length is is divided at 4096 points by input time order, and every group of subsequence is to take one every 1 sampling
Point, 0,2,4,6,8 ... ..., 8190 is first group, and 1,3,5,7,9 ... ..., 8191 is second group, then by chip interconnecting interface
One of which is sent into baseband signal processor slave unit by unit, and subsequence is sent into symbol level by baseband signal processor slave unit
Processing unit does 4096 FFTs；One group of other subsequence of baseband signal processor main equipment treatment.
Step 3.2：The FFT correction units of each baseband signal processor collect the low order FFT changes of above-mentioned piecemeal treatment
Data, the decimation in time based on FFT（DIT）Algorithm, the low order FFT delta datas to piecemeal treatment are corrected, and obtain high-order FFT
Result of variations, then complete subcarrier demapping and obtain channel data, needs this baseband signal processors is only extracted to channel data
The part of the frequency band for the treatment of, is then forwarded to code block level processing unit, and channel estimation, channel inspection are completed in code block level processing unit
Survey, correcting frequency deviation, modulation demapping, channel decoding, descrambling, the load information of final output physical layer.The present embodiment is specially：
In baseband signal processor main equipment, its FFT corrects unit and obtains what is processed by FFT from symbol level processing unit
One group of FFT result of subsequence, then obtained at baseband signal from by chip interconnecting interface unit and data diversity unit
The FFT result of another group of subsequence of device slave unit is managed, according to what is temporally selected（DIT）Base -2FFT algorithms can obtain
Xoi,
0≤k≤4095
0≤k≤4095
X (k) is 8192 FFT results, by Xo0（k）And Xo1（k）Composition.
By after FFT correction unit adjustment, 8192 points of FFT result is divided into continuous 2 groups by Xo in frequency domainiParallel
Output, every group 4096 points.The FFT correction unit selections of baseband signal processor main equipment need continuous subcarrier in frequency domain to be processed
Data, carry out subcarrier demapping, and being re-fed into code block level processing unit carries out code block level treatment, and last solution separates out physical layer load
Data.
In baseband signal processor slave unit, its FFT correction units can similarly obtain 8192 points of FFT result,
The continuous subcarrier in frequency domain data of another part are chosen, carrier wave demapping is carried out, being re-fed into code block level processing unit carries out code block level
Treatment, last solution separates out physical layer load data.
Step 3.3：Physical layer load data is carried out Preliminary Analysis by each baseband signal processor, by control message and industry
Business data classification, baseband signal processor main equipment, base band are submitted to by data diversity unit and chip interconnecting interface unit
The main control unit of processor main equipment collects whole Physical Layer Services by chip interconnecting interface unit and data diversity unit
Data, carry out communication protocol message treatment, complete the treatment of communications baseband downlink.
Example IV：The method for processing baseband signal of the up-link of 40MHz SISO systems
By taking 40MHz SISO systems as an example, chip connection applicating adn implementing example three is identical, still using embodiment for the present embodiment
One dual chip framework baseband signal processor, the method for processing baseband signal of its up-link is comprised the following steps：
Step 4.1：Baseband signal processor slave unit receives what is processed the need for baseband signal processor main equipment is distributed
The wherein physical layer load data of 20MHz bandwidth, is scrambled, channel coding, modulation mapping, code expand, spread spectrum and channel mapping,
Obtain physical layer frequency domain data；Baseband signal processor main equipment carries out the physical layer load data treatment of other 20MHz bandwidth.
Step 4.2：BBP main equipment receives the physical layer frequency domain data that BBP slave unit is provided, and carries out
After subcarrier maps, the decimation in time based on FFT（DIT）8192 point FFT are divided into algorithm 2 4096 points of FFT；By sub- load
Ripple is divided into the subsequence that 2 length is at 4096 points in order, and every group of subsequence is to be taken a bit every 1 sampling, and 0,2,4,6,
8 ... ..., 8190 is first group, and 1,3,5,7,9 ... ..., 8191 is second group, then is interconnected by data diversity unit and chip
Interface unit, sends one of which into baseband signal processor slave unit, BBP main equipment treatment another set；Each
Baseband signal processor（Including BBP main equipment）The point of low order 4096 IFFT conversion is done, because IFFT is the inverse fortune of FFT
Calculate, inverse fast fourier transform can utilize the structure of FFT to realize, such as a kind of conventionally known method is former
Reason is with reference to equation below：
Frequency domain data is taken into conjugation feeding signal processor first, conjugation finally is taken to output time-domain result again, and be multiplied by
1/N（When the index that N is 2, log is moved to right2N）, you can realize IFFT transformation results.
Step 4.3：Baseband signal processor main equipment collects the low order IFFT conversion data of packet transaction, based on FFT's
Decimation in time algorithm is corrected, and correcting algorithm obtains high-order IFFT transformation results, then complete with reference to the step of embodiment three 3.2
Plus CP, the precorrection of frequency deviation time domain, gain control and shaping filter, base band time domain sampled data is sent to radio-frequency apparatus, complete logical
Letter base band uplink processing.
Embodiment five：The method for processing baseband signal of the downlink of 40MHz 2 × 2MIMO systems
The present embodiment by taking the systems of 40MHz 2 × 2 as an example, using the dual chip framework baseband signal processor of embodiment one.
The method for processing baseband signal of its up-link is comprised the following steps：
Step 5.1：The radio frequency interface unit of baseband signal processor main equipment receives the double of 40MHz 2 × 2MIMO systems
Antenna downlink sample sequence, after removing CP, every group of sequence x（n）, 0≤n≤8191, totally 2 groups, it is necessary to process at twice；First
The pretreatment of symbol level processing stage is completed, such as goes direct current, frequency deviation time domain correlation etc. to send into data diversity unit；Data diversity
Unit is to every group of sample sequence x（n）Decimation in time based on FFT（DIT）Algorithm, 2 length are divided into by input time order
Be 4096 points of subsequence, every group of subsequence is to be taken a bit every 1 sampling, 0,2,4,6,8 ... ..., 8190 be first group, 1,
3,5,7,9 ... ..., 8191 is second group, then one of which is sent into baseband signal processor by chip interconnecting interface unit
Subsequence feeding symbol level processing unit is done 4096 FFTs by slave unit, baseband signal processor slave unit；Baseband signal
One group of other subsequence of processor main equipment treatment；2 groups of antenna samples sequences are, it is necessary to process 2 times altogether.
Step 5.2：The FFT correction units of each baseband signal processor collect the low order FFT changes of above-mentioned piecemeal treatment
Data, the decimation in time based on FFT（DIT）Algorithm, the low order FFT delta datas to piecemeal treatment are corrected, correcting algorithm ginseng
The step of according to embodiment three 3.2, high-order FFT result of variations is obtained, then complete subcarrier demapping and obtain channel data；Altogether 2
Group antenna samples sequence is, it is necessary to process 2 times；Then channel data is only extracted needs the frequency band of this baseband signal processor treatment
Part, be then forwarded to code block level processing unit, code block level processing unit complete double antenna data hierarchy, channel estimation,
Channel Detection, correcting frequency deviation, modulation demapping, channel decoding, descrambling, the load information of final output physical layer.
Step 5.3：Physical layer load data is carried out Preliminary Analysis by each baseband signal processor, by control message and industry
Business data classification, baseband signal processor main equipment, base band are submitted to by data diversity unit and chip interconnecting interface unit
The main control unit of processor main equipment collects Physical Layer Service Data by chip interconnecting interface unit and data diversity unit,
And communication protocol message treatment is carried out, complete the treatment of communications baseband downlink.
Embodiment six：The method for processing baseband signal of the up-link of 40MHz 2 × 2MIMO systems
By taking 40MHz 2 × 2MIMO systems as an example, chip connection applicating adn implementing example five is identical, still using reality for the present embodiment
The dual chip framework baseband signal processor of example one is applied, the method for processing baseband signal of its up-link is comprised the following steps：
Step 6.1：Baseband signal processor slave unit receives what is processed the need for baseband signal processor main equipment is distributed
The wherein physical layer load data of 20MHz bandwidth, is scrambled, channel coding, modulation mapping, code expand, spread spectrum and channel mapping,
Obtain physical layer frequency domain data；Baseband signal processor main equipment carries out the physical layer load data treatment of other 20MHz bandwidth；
2 × 2MIMO systems, above-mentioned treatment needs to carry out 2 wheels；After the completion of carry out multi-antenna layered coding.
Step 6.2：BBP main equipment receives the physical layer frequency domain data that BBP slave unit is provided, and carries out
After subcarrier maps, for every group of point data of antenna 8192, the decimation in time based on FFT（DIT）Algorithm decouples 8192 point FFT
It is 2 4096 points of FFT；Subcarrier is divided into the subsequence that 2 length is 4096 points in order, every group of subsequence be every
1 sampling takes a bit, and 0,2,4,6,8 ... ..., 8190 is first group, and 1,3,5,7,9 ... ..., 8191 is second group, then is passed through
Data diversity unit and chip interconnecting interface unit, send one of which subsequence into baseband signal processor slave unit, base band
Processor main equipment processes another set subsequence；Each baseband signal processor（Including BBP main equipment）Do low order
4096 point IFFT are converted, and because IFFT is the inverse operation of FFT, inverse fast fourier transform can utilize FFT
Structure is realized（With reference to step 4.2）；2 groups of antennas send sequence, it is necessary to process 2 times altogether.
Step 6.3：Baseband signal processor main equipment collected the low order IFFT conversion data of packet transaction, for every group day
Line number evidence, the decimation in time algorithm based on FFT is corrected, and correcting algorithm obtains high-order IFFT and become with reference to the step of embodiment three 2
Change result, then complete plus CP, the precorrection of frequency deviation time domain, gain control and shaping filter, send base band time domain sampled data to penetrating
Frequency equipment；2 groups of antennas send sequence, it is necessary to process 2 times altogether；It is finally completed communications baseband uplink processing.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (8)
1. a kind of baseband signal processor for supporting multi-chip framework, it is characterised in that the baseband signal processor includes：
1.1, main control unit, for controlling the unit in scheduling baseband signal processor, communication protocol message is processed, with
And control peripheral unit；
1.2, radio frequency interface unit is connected with data diversity unit, for being communicated with outside radio-frequency apparatus, is set to radio frequency
It is standby that the base band sample data for needing to send is provided, receive the base band sample data of radio-frequency apparatus output；
1.3, data diversity unit is connected with chip interconnecting interface unit, radio frequency interface unit and symbol level processing unit, is used for
The collection packing of exchange data, control parameter, feedback parameter between each baseband signal processor and distribution of unpacking, the friendship
Changing data includes base band sample data between radio frequency interface unit and symbol level processing unit, symbol level processing unit and quick
Fourier transform correction unit between time domain, frequency domain data, and code block level processing unit inputoutput data；The friendship
Data are changed to be exchanged between each baseband signal processor；
1.4, chip interconnecting interface unit is connected with the data diversity unit, for the high speed number between baseband signal processor
According to the interaction exchanged with necessary handshake；
1.5, symbol level processing unit is connected, for complete with the data diversity unit and FFT correction unit
Into the treatment of baseband signalling level, the treatment includes carrier wave mapping, multiple antennas transmission processe, the anti-fast Flourier of up-link
Go direct current, correcting frequency deviation, FFT, the multiple antennas of conversion, gain control, shaping filter, and downlink connect
Receipts treatment, carrier wave demapping；
1.6, FFT correction unit is connected between the symbol level processing unit and code block level processing unit,
For the decimation in time algorithm based on FFT, the FFT data to piecemeal treatment are corrected, and obtain high-order quick
Fourier transform results；
1.7, code block level processing unit is connected, with FFT correction unit for completing channel data block
Treatment, described treatment includes scrambling, channel coding, modulation mapping, code expansion, spread spectrum, the channel synthesis of up-link, and descending
The channel estimation of link, Channel Detection, correcting frequency deviation, modulation demapping, channel decoding, descrambling；
1.8, memory cell, as data diversity unit, symbol level processing unit, FFT correction unit, code
Data exchange caching between block level processing unit.
2. the baseband signal processor described in a kind of claim 1, it is characterised in that：The baseband signal processor possesses master and sets
Standby and two kinds of mode of operations of slave unit.
3. the baseband signal processor described in a kind of claim 2, it is characterised in that：The chip interconnecting interface unit uses base
In the parallel bus interface of double digit rate.
4. the baseband signal processor described in a kind of claim 2, it is characterised in that：The chip interconnecting interface unit is using high
Fast interconnecting interface, coordinates interaction handshake, realizes that chip chamber is interconnected at a high speed.
5. the baseband signal processor described in a kind of claim 1, it is characterised in that：The baseband signal processor also includes outer
Portion's memory interface, for the outside extension of the memory cell.
6. the processing method of a kind of baseband signal processor for described in claim 1, it is characterised in that：
For downlink, comprise the following steps：
A.1, baseband signal processor main equipment receives the base band sample data from radio-frequency apparatus, after removing Cyclic Prefix, is based on
The decimation in time algorithm of FFT does piecemeal to the base band sample data, and high-order FFT is decomposed into multiple low order FFTs,
Each baseband signal processor is distributed to again does low order FFT；Or each baseband signal processor can be received and come from
The base band sample data of radio-frequency apparatus, each baseband signal processor selects out needs according to the decimation in time algorithm based on FFT
The base band sample data of present processor treatment carries out low order FFT；
A.2, each baseband signal processor collects the low order FFT data of piecemeal treatment, and the decimation in time based on FFT is calculated
Method, the low order FFT delta datas to piecemeal treatment are corrected, and obtain high-order FFT result of variations；Again to high-order FFT result of variations
Select out need present processor process frequency domain data carry out subcarrier demapping, channel estimation, Channel Detection, correcting frequency deviation,
Modulation demapping, channel decoding and descrambling, the load data of final output physical layer；
A.3, each baseband signal processor carries out Preliminary Analysis to physical layer load data, by control message and business datum point
Class, then baseband signal processor main equipment is submitted to, baseband signal processor main equipment collects whole Physical Layer Service Datas, and
Communication protocol message treatment is carried out, downlink treatment is completed；
For up-link, comprise the following steps：
B.1, each baseband signal processor receives the physical layer load processed the need for baseband signal processor main equipment is distributed
Data, scrambled, channel coding, modulation mapping, code expand, spread spectrum and channel mapping, obtain physical layer frequency domain data；
B.2, baseband signal processor main equipment collects the physical layer frequency domain data of each baseband signal processor, based on FFT's
Decimation in time algorithm does piecemeal, then is distributed to each baseband signal processor and does low order IFFT conversion；
B.3, baseband signal processor main equipment collects the low order IFFT conversion data of piecemeal treatment, the decimation in time based on FFT
Algorithm is corrected, obtain high-order IFFT transformation results, then complete plus Cyclic Prefix, the precorrection of frequency deviation time domain, gain control and into
Shape is filtered, and sends base band sample data to radio-frequency apparatus；
Wherein, described each baseband signal processor include the baseband signal processor main equipment and baseband signal processor from
Equipment.
7. method according to claim 6, it is characterised in that a.1, the low order FFT includes step, is low order FFT
Before conversion, direct current and the treatment of frequency deviation time domain correlation are done for each sampled point.
8. method according to claim 6, it is characterised in that baseband signal processor main equipment and baseband signal processor
Slave unit, packing transmission interaction is carried out to control parameter and feedback parameter by data diversity unit, and collaboration completes baseband signal
Treatment.
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| CN104683249A (en) * | 2015-02-26 | 2015-06-03 | 浪潮电子信息产业股份有限公司 | Independent configurable interconnection module implementation method for multi-chip interconnection system |
| CN106470175B (en) * | 2015-08-20 | 2019-10-18 | 深圳市中兴微电子技术有限公司 | A kind of baseband chip and signal processing method |
| US10162789B2 (en) * | 2015-09-03 | 2018-12-25 | Altera Corporation | Distributed multi-die protocol application interface |
| CN108738035B (en) * | 2017-04-13 | 2021-07-20 | 深圳市中兴微电子技术有限公司 | Data processing method and device of multi-system baseband chip and processing equipment |
| CN109672456B (en) * | 2018-11-28 | 2020-03-24 | 北京理工大学 | Variable speed modulator based on off-chip storage and signal generation method |
| CN114257476B (en) * | 2020-09-23 | 2024-01-02 | 华为技术有限公司 | Communication method and communication device |
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| CN1561579A (en) * | 2001-09-28 | 2005-01-05 | 国际商业机器公司 | Analog baseband signal processing system and method |
| CN1602012A (en) * | 2004-06-10 | 2005-03-30 | 上海交通大学 | Realizing method of communicating controller |
| CN101150324A (en) * | 2006-09-21 | 2008-03-26 | 美国博通公司 | RF receiver and its operation method |
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| CN1561579A (en) * | 2001-09-28 | 2005-01-05 | 国际商业机器公司 | Analog baseband signal processing system and method |
| CN1602012A (en) * | 2004-06-10 | 2005-03-30 | 上海交通大学 | Realizing method of communicating controller |
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