CN103579007B - For the post tensioned unbonded prestressed concrete area of isolation formation method of fin formula field effect transistor device - Google Patents

For the post tensioned unbonded prestressed concrete area of isolation formation method of fin formula field effect transistor device Download PDF

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CN103579007B
CN103579007B CN201310278544.XA CN201310278544A CN103579007B CN 103579007 B CN103579007 B CN 103579007B CN 201310278544 A CN201310278544 A CN 201310278544A CN 103579007 B CN103579007 B CN 103579007B
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area
grid
isolation
layer
fin
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CN103579007A (en
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B·S·哈兰
S·梅塔
T·E·斯坦戴尔特
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a kind of method formed for fin formula field effect transistor (finFET) device, comprising: on substrate, form multiple fin; Area of grid is formed on multiple fin; And after forming area of grid, form the area of isolation being used for finFET device, wherein form the area of isolation being used for finFET device and comprise one of the oxidation or removal that perform the subset of multiple fin.

Description

For the post tensioned unbonded prestressed concrete area of isolation formation method of fin formula field effect transistor device
Technical field
Present disclosure mainly relates to semiconductor device and makes field, and relates more specifically to fin formula field effect transistor (FinFET) making.
Background technology
Integrated circuit can comprise various semiconductor device, and these semiconductor device comprise fin formula field effect transistor (finFET).FinFET is following device, and these devices comprise the three-dimensional silicon layer being called fin that serves as active channel region and area of grid is positioned on fin.FinFET can be relatively little high performance device.During formation finFET device, multiple fin can be formed on substrate, and the part can removing or cut these fins subsequently to form area of isolation between finFET device.After formation area of isolation, then on remaining active fin, form area of grid.But the fin removal before grid is formed may cause the pattern in finFET device to change, this may cause the problem during subsequent processing steps (such as crossing over the difference in height of device between grid), and these problems may cause the problem between contact Formation period.In order to reduce the change of such pattern, the fin in area of isolation can alternatively stay put and oxidized, and active fin is such as protected by nitride hardmask.But silica causes the volume in the fin of oxidation to increase relative to unoxidized active fin.In addition; between the heat of oxidation, protect the nitride hardmask of active fin may become after being exposed to oxidation be more difficult to and remove, making may in order to remove the nitride hardmask of oxidation to complete the fin that the etching needed the process of active fin also may remove oxidation.Therefore, fin oxidation also may cause the pattern in finFET device to change, thus causes the Similar Problems during subsequent processing steps.
Summary of the invention
In an aspect, a kind of method formed for fin formula field effect transistor (finFET) device comprises: on substrate, form multiple fin; Area of grid is formed on multiple fin; And after forming area of grid, form the area of isolation being used for finFET device, wherein form the area of isolation being used for finFET device and comprise one of the oxidation or removal that perform the subset of multiple fin.
Supplementary features are realized by the technology of this exemplary embodiment.Here specifically describe other embodiment and think that these embodiments are a part for claimed invention content.In order to better understand the feature of exemplary embodiment, with reference to description and accompanying drawing.
Accompanying drawing explanation
Referring now to accompanying drawing, wherein similar elements is numbered in the same manner in some figure:
The embodiment of the method that Fig. 1 diagram is formed for the post tensioned unbonded prestressed concrete area of isolation of finFET device.
Fig. 2 A to Fig. 2 B is the cross section of embodiment after fin-shaped becomes and the schematic block diagram of vertical view that illustrate silicon-on-insulator (SOI) substrate respectively.
Fig. 3 A to Fig. 3 B is the schematic block diagram of cross section after the embodiment of the device of pictorial image 2A to Fig. 2 B respectively forms dielectric layer on device and vertical view.
Fig. 4 A to Fig. 4 B is the schematic block diagram of cross section after the embodiment of the device of pictorial image 3A to Fig. 3 B respectively forms grid material on dielectric layer and vertical view.
Fig. 5 A to Fig. 5 B is the schematic block diagram of cross section after the embodiment of the device of pictorial image 4A to Fig. 4 B respectively forms mask layer on grid material and vertical view.
Fig. 6 A to Fig. 6 B is the cross section of embodiment after area of grid definition and the schematic block diagram of vertical view of the device of pictorial image 5A to Fig. 5 B respectively.
Fig. 7 A to Fig. 7 C is embodiment cross section after the spacers are formed and the schematic block diagram of vertical view of the device of pictorial image 6A to Fig. 6 B respectively.
Fig. 8 A to Fig. 8 C is the cross section of embodiment after formation area of isolation mask and the schematic block diagram of vertical view of the device of pictorial image 7A to Fig. 7 B respectively.
Fig. 9 A to Fig. 9 C is the schematic block diagram that the embodiment of the device of pictorial image 8A to Fig. 8 B is respectively using area of isolation mask to be etched with cross section after the sept exposed in area of isolation and vertical view.
Figure 10 A to Figure 10 C is the schematic block diagram of embodiment at the cross section of removing after the sept in area of isolation and vertical view of the device of respectively pictorial image 9A to Fig. 9 B.
Figure 11 A to Figure 11 C is the schematic block diagram of embodiment at the cross section of removing after the dielectric layer in area of isolation and vertical view of the device of respectively pictorial image 10A to Figure 10 B.
Figure 12 A to 12C is the schematic block diagram of cross section after the embodiment of the device of respectively pictorial image 11A to Figure 11 B fin in oxide isolation region and vertical view.
Figure 13 A to Figure 13 C is the schematic block diagram of embodiment at the cross section of removing after the fin in area of isolation and vertical view of the device of respectively pictorial image 11A to Figure 11 B.
Embodiment
A kind of method providing post tensioned unbonded prestressed concrete area of isolation for finFET device to be formed and a kind of embodiment with the finFET device of the area of isolation that post tensioned unbonded prestressed concrete is formed.The pattern that can reduce in finFET device by forming area of isolation after forming finFET area of grid changes.This delay in the formation of area of isolation provides non-uniform topographical between grid Formation period.Can be oxidized by fin in various embodiments or fin remove form area of isolation.The area of grid formed before area of isolation can comprise dummy gate electrode (for post tensioned unbonded prestressed concrete technique) or final grid (for first grid technology) in various embodiments.Fin oxidation and fin are removed and can be combined with first grid or post tensioned unbonded prestressed concrete technique.Formed after area of isolation and be used for the source electrode of finFET device and drain region, and in the embodiment comprising post tensioned unbonded prestressed concrete technique, also perform after forming area of isolation the replacement grid process of dummy gate electrode to form final grid.
The embodiment of the method 100 that Fig. 1 diagram is formed for the post tensioned unbonded prestressed concrete area of isolation of finFET device.About Fig. 2 A to Fig. 2 B to Figure 13 A to Figure 13 B, Fig. 1 is discussed.First, in the block 101 of Fig. 1, multiple fin is formed on soi substrates.SOI substrate can be included in can comprise buried oxide (BOX) intermediate insulator layer below the lower bulk substrate layer that can comprise silicon, and the semiconductor layer that can comprise the relative thin of silicon is positioned at top.Fin can with including but not limited to that any appropriate ways of sidewall image transfer is formed at top semiconductor layer.Any proper number and directed fin can be formed in SOI substrate during the block 101 of Fig. 1.The cross section of the embodiment that Fig. 2 A to Fig. 2 B diagram comprises the device 200 of SOI substrate after fin-shaped becomes and vertical view.Device 200 comprises SOI substrate, and this SOI substrate comprises base substrate 201, BOX202 and is positioned at the multiple fins 203 on the top of BOX202.Fin 203 can comprise silicon fin.Only for illustrative purposes Fig. 2 A and Fig. 2 B is shown; Any proper number and directed fin can be formed during the block 101 of Fig. 1.
The flow process of the method 100 of Fig. 1 forwards block 102 now to, in the block dielectric layer deposition and grid material on fin.Can only deposit the first dielectric layer in the embodiment comprising first grid technology, and the first dielectric layer can comprise high k (HK) material and/or oxide in various embodiments.Dielectric layer deposition can be carried out in certain embodiments by conformal ald (ALD).Dielectric layer can comprise the gate-dielectric for the device completed in certain embodiments.On device after dielectric layer deposition, deposition of gate material on dielectric layer.In certain embodiments, grid material can comprise dummy gate electrode material (for post tensioned unbonded prestressed concrete technique), and in other embodiments, grid material can comprise final grid material (for first grid technology).Grid material comprises in the embodiment of dummy gate electrode material wherein, and grid material can comprise polysilicon.Grid material comprises in the embodiment of final grid material wherein, and grid material can be included in the workfunction layers above gate oxide dielectric layer and the silicon layer that can comprise amorphous silicon on the top of metal level.Upon formation, the top surface of chemico-mechanical polishing (CMP) planarized gate material can such as be passed through to reduce the pattern change in device.The device 200 of Fig. 3 A to Fig. 3 B pictorial image 2A to Fig. 2 B forms cross section after dielectric layer 301 and vertical view on device 200.Dielectric layer 301 can comprise high k (HK) material or oxide in various embodiments, and can be deposited by conformal ALD.Fig. 4 A to Fig. 4 B illustrates and to be formed and the device 300 of Fig. 3 A to Fig. 3 B after planarization grid material 401 on dielectric layer 301.The metal level that grid material 401 can comprise polysilicon in certain embodiments or be included in other embodiments below polysilicon layer.Such as by the top surface of cmp planarization grid material 401.
Look back the method 100 of Fig. 1, flow process forwards block 103 now to, and in this block 103, etching grid material is used for the area of grid of device with definition.Can perform etching grid material in any appropriate manner according to the material type comprising grid material to define area of grid, this grid material comprises area of grid.Before forming area of grid, can form two layer masks at etching grid material on grid material in certain embodiments, this two layer mask is included in the bottom mask layer below hardmask layer.Bottom mask layer can comprise nitride in certain embodiments, and hardmask layer can comprise nitride or oxide in certain embodiments.Can based on the thickness of the material adjustment hardmask layer for hardmask layer.Such as, compare with oxide top hard mask layer, nitride hardmask layer can be relatively thick, makes not remove nitride hardmask layer (block 106 hereafter about Fig. 1 is discussed) completely during nitride etching sept 701.Bottom mask layer also can be relatively thick, to protect area of grid during the subsequent processing steps that can comprise multiple RIE step.Area of grid can comprise dummy gate electrode or final grid in various embodiments.Area of grid comprises in the embodiment of final grid wherein, and metal and silicon layer may need independent etching step to define area of grid.Area of grid can have any suitable pattern about fin; Such as area of grid can with fin vertical orientation.Because area of grid was formed on fin before area of isolation, so fin provides non-uniform topographical between grid Formation period.The device 400 of Fig. 5 A to Fig. 5 B pictorial image 4A to Fig. 4 B forms cross section after gate mask layer 501/502 and vertical view on grid material 401.Bottom mask layer 501 can comprise nitride in certain embodiments, and hardmask layer 502 can comprise oxide or nitride hardmask in various embodiments.Fig. 6 A to Fig. 6 B illustrates the device 500 of Fig. 5 A to Fig. 5 B after definition area of grid 601.Gate mask layer 501/502 is positioned on the top of area of grid 601.Cross section shown in Fig. 6 A is along line 603 as depicted in figure 6b, and this line 603 is passed in one of area of grid below hardmask layer 502.Area of grid 601 comprises grid material 401.Area of grid 601 can comprise dummy gate electrode or final grid in various embodiments.The dielectric layer 301 be located immediately on fin 203 is exposed by forming area of grid 601.The fin 602 in fin 203 is exposed in the sectional view of Fig. 6 A.
Then, in the block 104 of the method 100 of Fig. 1, on the device comprising fin and area of grid, sept is formed.Sept can be comprised nitride and can be deposited on device by conformal deposit.The device 600 of Fig. 7 A and Fig. 7 C pictorial image 6A to Fig. 6 B forms the cross section after sept 701 on the device comprising area of grid 601 and fin 203, and Fig. 7 B is shown in the vertical view forming device 600 after sept 701.Fig. 7 A illustrates that the cross section of the line 603 of Fig. 7 B crossed over by device 700, and this line 603 is through one of area of grid, and Fig. 7 C illustrates that the cross section of the line 702 of Fig. 7 B crossed over by device 700, and this line 702 is not through area of grid.Sept 701 can comprise nitride.
Then the flow process of method 100 forwards block 105 to, in this block 105, forms area of isolation mask on sept.Area of isolation mask defines the area of isolation for the finFET device completed, and can comprise fin cutting mask in certain embodiments or comprise fin oxidation mask in other embodiments.Area of isolation mask can be included in the organic planarization layer (OPL) below silicon anti-reflection coating (SiArc) layer, and this SiArc layer is below photoresist layer, and this photoresist layer is patterned to define the area of isolation for device.The device 700 of Fig. 8 A and Fig. 8 C pictorial image 7A to Fig. 7 B forming the cross section after area of isolation mask, and Fig. 7 B illustrated device 700 after forming area of isolation mask vertical view.Fig. 8 A illustrates that the cross section of the line 603 of Fig. 7 B crossed over by device 800, and this line 603 is through one of area of grid, and Fig. 8 C illustrates that the cross section of the line 702 of Fig. 8 B crossed over by device 800, and this line 702 is not through area of grid.Area of isolation mask comprises OPL801, SiArc802 and photoresist 803.Patterned photo glue 803, makes expose device isolation regions and be coated with source region.
Look back the method 100 of Fig. 1, then use area of isolation mask expose in area of isolation and remove sept in block 106.This can perform with any appropriate ways; In certain embodiments, exposure interval thing can comprise the pattern (such as using reactive ion etching) that to etch in SiArc and OPL and defined by photoresist and remove photoresist.After exposure interval thing, remove the spacer material of exposure.Sept can comprise nitride, and the sept removing exposure can comprise the etching relative to the selective removal nitride of oxide.The nitride removed in area of isolation exposes the dielectric layer be arranged on the undesired fin of final finFET device.The device 800 of Fig. 9 A and Fig. 9 C pictorial image 8A to Fig. 8 B cross section after the sept 701 using area of isolation mask to expose in area of isolation, and Fig. 9 B illustrated device 800 is exposing the vertical view after sept 701.Fig. 9 A illustrates that the cross section of the line 603 of Fig. 9 B crossed over by device 900, and this line line 603 is through one of area of grid, and Fig. 9 C illustrates that the cross section of the line 702 of Fig. 9 B crossed over by device 900.As shown in Fig. 9 A to Fig. 9 B, etch OPL801 and SiArc802 downwards to expose the sept 701 in area of isolation, and removed photoresist 803.The device 900 of Figure 10 A and Figure 10 C pictorial image 9A to Fig. 9 B is removing the cross section after the sept in area of isolation, and Figure 10 B illustrated device 900 is removing the vertical view after sept.Figure 10 A illustrates that the cross section of the line 603 of Figure 10 B crossed over by device 1000, and this line 603 is through one of area of grid, and Figure 10 C illustrates that the cross section of the line 702 of Figure 10 B crossed over by device 100, and this line 702 is not through area of grid.Also OPL801 and SiArc802 is removed in Figure 10 A to Figure 10 B.Sept 701 can comprise nitride, and dielectric layer 301 can comprise oxide; Therefore, the sept 701 that removal exposes can comprise the etching relative to the selective removal nitride of oxide.In area of isolation, dielectric layer 301 is exposed by the sept 701 removed in area of isolation.
Then the flow process of method 100 forwards block 107 to, removes the dielectric layer of the exposure in area of isolation in this block 107, exposes undesired any fin in final finFET device thus.The device 100 of Figure 11 A and Figure 11 C pictorial image 10A to Figure 10 B is removing the cross section after the dielectric layer 301 in area of isolation, and Figure 11 B illustrated device 100 is removing the vertical view after dielectric layer 301.Figure 11 A illustrates that the cross section of the line 603 of Figure 11 B crossed over by device 1100, and this line 603 is through one of area of grid, and Figure 11 C illustrates that the cross section of the line 702 of Figure 11 B crossed over by device 1100, and this line 603 is not through area of grid.Undesired fin is exposed, the fin 1101 in such as fin 203 by the dielectric layer 301 removed in area of isolation.
Then, in the block 108 of the method 100 of Fig. 1, the area of isolation being used for final finFET device is formed.In certain embodiments, the fin that can be exposed by oxidation forms area of isolation.Fin oxidation can be combined with post tensioned unbonded prestressed concrete technique; Namely area of grid comprises in the embodiment of dummy gate electrode wherein.Fin oxidation also can be combined with first grid technology, and namely area of grid comprises in the embodiment of final grid wherein.But in some embodiments of first grid technology, the oxidation of fin also can be oxidized the material that may reside in final grid.Therefore, in the first grid technology comprising fin oxidation, the oxidation of grid material can be considered in resulting devices.Fin oxidation converts the silicon comprising fin to oxide.In other embodiments, the fin that can be exposed by cutting forms area of isolation.Fin cutting can be combined with first grid or post tensioned unbonded prestressed concrete technique, and can comprise in certain embodiments oxide selectively based on the dry etching of chlorine.Cross section after the fin (such as fin 1201) of the exposure of device 1100 in oxide isolation region of Figure 12 A and Figure 12 C pictorial image 11A to Figure 11 B, and the vertical view of Figure 12 B illustrated device 1100 after the fin that oxidation exposes.Figure 12 A illustrates that the cross section of the line 603 of Figure 12 B crossed over by device 1200, and this line 603 is through one of area of grid, and Figure 12 C illustrates that the cross section of the line 702 of Figure 12 B crossed over by device 1200.Fin 1201 comprises oxide and serves as the area of isolation in final finFET device.As shown in figure 12a, the part be positioned at below area of grid 601 of fin 1201 can be oxidized.The device of Figure 12 A and Figure 13 C pictorial image 11A to Figure 11 B in removal fin (such as fin 1101 shown in Figure 11 A to Figure 11 B) to form the cross section after area of isolation 1301, and the device of Figure 13 B pictorial image diagram 11A to Figure 11 B at removal fin to form the vertical view after area of isolation 1301.Figure 13 A illustrates that the cross section of the line 603 of Figure 13 B crossed over by device 1300, and this line 603 is through one of area of grid, and Figure 13 C illustrates that the cross section of the line 702 of Figure 13 B crossed over by device 1300.The part be positioned at below area of grid 601 of fin 203 can not removed as shown in FIG. 13A.
Last in the block 109 of the method 100 of Fig. 1, form the final finFET device comprising N-shaped and p-type regions and source/drain.N-shaped and p-type regions and source/drain can be formed with any appropriate ways.In certain embodiments, post tensioned unbonded prestressed concrete process (namely remove and replace dummy gate electrode with final grid) also can be performed in block 109.The finFET device completed of gained can have the relatively low pattern change of crossing over device, and this can allow to be formed less and/or more high performance device.
The technique effect of exemplary embodiment and benefit comprise reducing may be affected the pattern that the grid for finFET device formed negatively and change.
Here term used only in order to describe specific embodiment and and not intended to be limiting the present invention.As used herein, singulative "/a kind of " and " being somebody's turn to do ", unless context separately has expresses, are intended to also comprise plural form.Also will understand, term " comprises " but the feature of specifying existence to state when being used in this specification, one integral piece, step, operation, element and/or parts are not got rid of existence or added one or more further feature, one integral piece, step, operation, element, parts and/or its combination.
In following claim, all devices or step add that the counter structure of function element, material, action and equivalent are intended to comprise other claimed elements combination for protecting with such as specific requirement with any structure of n-back test, material or action.But description of the invention for example and description object and presented and be not intended as exhaustive the present invention or make the present invention be limited to disclosed form.Many modifications and variations will by those of ordinary skill in the art are known and do not depart from the scope of the present invention and Spirit Essence.Select and describe embodiment principle of the present invention and practical application to be described best and to enable other those of ordinary skill of this area for having if the various embodiments of the matched various amendment of specific use with imagination are to understand the present invention.

Claims (18)

1., for the method that fin formula field effect transistor (finFET) device is formed, described method comprises:
Substrate is formed multiple fin;
Area of grid is formed on described multiple fin; And
After the described area of grid of formation, form the area of isolation being used for described fin formula field effect transistor device, wherein form the described area of isolation being used for described fin formula field effect transistor device and comprise execution to the oxidation of the subset of described multiple fin and the one in removing.
2. method according to claim 1, wherein said substrate comprises silicon-on-insulator (SOI) substrate, the top silicon layer that described silicon-on-insulator substrate comprises lower bulk substrate, is positioned at buried oxide (BOX) layer on described lower bulk substrate and is positioned in described buried oxide layer, and wherein said multiple fin-shaped is formed in the described top silicon layer of described silicon-on-insulator substrate.
3. method according to claim 1, be also included in and form before described area of grid dielectric layer deposition on described multiple fin, wherein said area of grid is formed on described dielectric layer.
4. method according to claim 3, wherein said dielectric layer comprises oxide, and wherein deposits described dielectric layer and comprise conformal ald.
5. method according to claim 3, wherein forms described area of grid and comprises on described multiple fin:
Deposition of gate material on described dielectric layer;
The top surface of grid material described in planarization;
On described grid material, deposition comprises two layer masks of bottom mask layer and hardmask layer; And
Etch described grid material to form described area of grid, wherein said two layer masks remain on the top of described area of grid after being etched with the described area of grid of formation.
6. method according to claim 5, wherein said bottom mask layer comprises nitride, and described hardmask layer comprises oxide.
7. method according to claim 5, wherein said bottom mask layer comprises nitride, and described hardmask layer comprises nitride.
8. method according to claim 5, wherein said area of grid comprises dummy gate electrode, and wherein said grid material comprises polysilicon.
9. method according to claim 5, wherein said area of grid comprises final grid, and wherein said grid material is included in the silicon layer on metal level.
10. method according to claim 1, is also included in and is formed before described area of isolation on described area of grid and to form nitride spacer being positioned on the dielectric layer on described multiple fin.
11. methods according to claim 10, wherein form the area of isolation being used for described fin formula field effect transistor device and comprise after forming described area of grid:
Area of isolation mask is formed on described nitride spacer;
Described area of isolation mask is used to remove described nitride spacer in described area of isolation to expose the described subset of described multiple fin; And
Perform one of the oxidation and removal of the subset of the described exposure of described multiple fin to form described area of isolation.
12. methods according to claim 11, wherein said area of grid comprises dummy gate electrode, and wherein forms described area of isolation and comprise oxidation.
13. methods according to claim 11, wherein said area of grid comprises final grid, and wherein forms described area of isolation and comprise oxidation.
14. methods according to claim 11, wherein said area of grid comprises dummy gate electrode, and wherein forms described area of isolation and comprise removal.
15. methods according to claim 11, wherein said area of grid comprises final grid, and wherein forms described area of isolation and comprise removal.
16. methods according to claim 11, remove described dielectric layer from the subset of the described exposure of described multiple fin before being also included in one of the oxidation or removal performed the subset of the described exposure of described multiple fin.
17. methods according to claim 12, wherein said area of isolation mask comprises:
Organic planarization layer (OPL), is positioned on the top of described nitride spacer;
Silicon anti-reflection coating (SiArc) layer, is positioned on described organic planarization layer; And
Photoresist layer, is positioned on the top of described organic planarization layer.
18. methods according to claim 17, the top that wherein said photoresist layer is positioned at the active region of described fin formula field effect transistor device exposes described area of isolation.
CN201310278544.XA 2012-07-18 2013-07-04 For the post tensioned unbonded prestressed concrete area of isolation formation method of fin formula field effect transistor device Active CN103579007B (en)

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