CN103441104B - Method for cutting wafer - Google Patents
Method for cutting wafer Download PDFInfo
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- CN103441104B CN103441104B CN201310382986.9A CN201310382986A CN103441104B CN 103441104 B CN103441104 B CN 103441104B CN 201310382986 A CN201310382986 A CN 201310382986A CN 103441104 B CN103441104 B CN 103441104B
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Abstract
The present invention provides a kind of method for cutting wafer, comprising: provide wafer, this wafer includes front and the back side answered with this vis-a-vis；By radium-shine cutting technique just cutting towards its back side from described wafer, form multiple Cutting Road with the front at described wafer；The front of wafer being formed with Cutting Road attaches and grinds glued membrane；Grinding back surface is carried out, so that described Cutting Road runs through the wafer after grinding, thus forming the chip of multiple separation to being pasted with the wafer grinding glued membrane。Will not producing cutting stress owing to have employed first radium-shine cutting, rear grinding technics, and radium-shine cutting, therefore the method for cutting wafer in the present invention is possible not only to avoid breaking of thin wafer, it is possible to be applied to cutting low-k wafer。
Description
[technical field]
The present invention relates to technical field of manufacturing semiconductors, particularly to a kind of method for cutting wafer。
[background technology]
In manufacture of semiconductor, it is necessary to wafer (wafer) is cut into chip (die) one by one, then these chips is made different semiconductor packages。Refer to shown in Fig. 1, it is the top view of a wafer 100。Described wafer 100 includes front 110 and the back side corresponding with this front 110, wherein said front 110 is provided with several longitudinal and horizontal Cutting Roads (Cuttingstreet) 120, to define several chips 130 in wafer 100。Wherein, the front 110 of wafer 100 refers to the surface forming element, lamination, interconnection line and weld pad etc. on a semiconductor substrate。
Method for cutting wafer of the prior art generally includes: wafer 100 is carried out thinning back side (backsidegrinding) by the emery wheel first with grinder, followed by cutting tool (such as, diamond knife) rearwardly cut along the Cutting Road 120 between chip 130 from the front 110 of wafer 100, chip 140 one by one is made to separate, thus forming independent chip。
In order to adapt to the light littleization development trend of ic chip package, it is desirable to the thickness of wafer and can accomplish thin (namely manufacturing ultra-thin wafers) very。But, when using traditional handicraft operation ultra-thin wafers, the easy warpage of wafer after grinding, and easily cause wafer during subsequent processing operations and break；During in particular by tradition diamond knife cutting ultra thin, low-k wafer, it is easy to metal interlevel lamination occurs。
Therefore, it is necessary to provide the technical scheme of a kind of improvement to overcome the problems referred to above。
[summary of the invention]
It is an object of the invention to provide a kind of method for cutting wafer, it can be avoided or improve, and wafer produces because of cutting breaks, it is also possible to be applied to cutting low-k wafer without causing its metal level to be layered。
In order to solve the problems referred to above, the present invention provides a kind of method for cutting wafer, comprising: provide wafer, this wafer includes front and the back side answered with this vis-a-vis；By radium-shine cutting technique just cutting towards its back side from described wafer, form multiple Cutting Road with the face side at described wafer；The front of wafer being formed with described Cutting Road attaches and grinds glued membrane；Grinding back surface is carried out, so that described Cutting Road runs through the wafer after grinding, thus forming the chip of multiple separation to being pasted with the wafer grinding glued membrane。
In one further embodiment, it is provided that described wafer also include semiconductor layer and the metal level being formed on described semiconductor layer, described metal level is positioned at the front of described wafer。
In one further embodiment, described Cutting Road runs through described metal level from the front of described wafer, and its end extends into described semiconductor layer。
In one further embodiment, described method for cutting wafer also includes: attaches fixing glued membrane at the back side of the wafer being formed with separating chips, and is fixed on wafer frame by wafer by this fixing glued membrane；With the grinding glued membrane on the front removing the wafer being fixed on described wafer frame。
In one further embodiment, described grinding glued membrane is ultraviolet glued membrane, and the grinding glued membrane removed on the front of the wafer being fixed on described wafer frame includes: this ultraviolet glued membrane is carried out ultraviolet illumination；With remove described ultraviolet glued membrane。
In one further embodiment, the fixing glued membrane attached at the back side of the wafer being formed with separating chips is dicing tape or blue film。Described semiconductor layer is silicon wafer layer。
Compared with prior art, the method for cutting wafer in the present invention, first passing through radium-shine cutting and form multiple Cutting Road in the front of wafer, by grinding technics, the back side of wafer being carried out thinning afterwards, thus forming multiple chip separated from one another。Owing to have employed first radium-shine (laser) cutting, rear grinding technics, and radium-shine cutting will not produce cutting stress, therefore the method for cutting wafer in the present invention, it is possible not only to avoid or improve thin wafer break because cutting, it is also possible to be applied to cutting low-k wafer without causing its metal level to be layered。
[accompanying drawing explanation]
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below the accompanying drawing used required during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings。Wherein:
Fig. 1 is the top view of a kind of wafer；
Fig. 2 is the schematic flow sheet of present invention method for cutting wafer in one embodiment；
Fig. 3 A-3F is the generalized section of the wafer that each step in Fig. 2 obtains in a specific embodiment。
[detailed description of the invention]
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation。
" embodiment " or " embodiment " referred to herein refers to the special characteristic, structure or the characteristic that may be included at least one implementation of the present invention。Different local in this manual " in one embodiment " occurred not refer both to same embodiment, neither be independent or selective and that other embodiments are mutually exclusive embodiment。
Method for cutting wafer in the present invention, first passes through radium-shine cutting and forms multiple Cutting Road in the front of wafer, carries out thinning by grinding technics to the back side of wafer afterwards, thus forming multiple chip separated from one another。Owing to have employed first radium-shine (laser) cutting, rear grinding technics, and radium-shine cutting will not produce cutting stress, therefore the method for cutting wafer in the present invention, it is possible not only to avoid or improve thin wafer break because cutting, can also be applied to cutting low-k wafer without causing its metal level be layered, be additionally possible to prevent grinding after wafer generation warpage。
Refer to shown in Fig. 2, it is the schematic flow sheet of present invention method for cutting wafer 200 in one embodiment。Fig. 3 A-3F is the generalized section of the wafer obtained with each step in Fig. 2 in a specific embodiment。
Step 210, it is provided that wafer 300, this wafer 300 includes front 310 and the back side 320 corresponding with this front 310。In conjunction with reference to shown in Fig. 3 A, described wafer 300 also includes semiconductor layer (in the present embodiment for silicon chip (si)) 330 and the metal level 340 being formed on described semiconductor layer 330, and described metal level 340 is positioned at the front of described wafer。
Step 220, is cut to its back side from the front 310 of described wafer 300 by radium-shine cutting technique (namely being cut by laser beam Laserbeam), forms multiple Cutting Road 350 with the face side at described wafer 300。It should be noted that in this step, wafer 300 is not cut into the chip of multiple separation, that is Cutting Road 350 does not run through whole wafer 300。Refer to shown in Fig. 3 B, described Cutting Road 350 runs through described metal level 340 from the front 310 of described wafer 300, and its end extends in described semiconductor layer 330。
Step 230, in conjunction with reference to, shown in Fig. 3 C, attaching and grind glued membrane 360, for instance UV(Ultraviolet, ultraviolet on the front 310 of wafer being formed with Cutting Road 350) glued membrane。
Step 240, in conjunction with reference to, shown in Fig. 3 D, carrying out grinding back surface to being pasted with the wafer grinding glued membrane 360, the wafer after making described Cutting Road 350 run through grinding, to form the chip 370 of multiple separation。
Step 250, attaches fixing glued membrane 380(such as dicing tape or blue film at the back side of the wafer being formed with separating chips 370), and by this fixing glued membrane 380, wafer is fixed on wafer frame 390(such as iron hoop) on, refer to shown in Fig. 3 E。So can avoid colliding with each other between the chip separated, also allow for carrying simultaneously。
Step 260, removes the grinding glued membrane 360 in described wafer frontside。Refer to shown in Fig. 3 F, due in the present embodiment, grinding glued membrane is UV glued membrane, therefore when removing this UV glued membrane, it is possible to this UV glued membrane is carried out UV illumination, eliminates its adhesion, then remove again。In other embodiments, if grinding glued membrane is non-UV glued membrane, then when the grinding glued membrane removed in wafer frontside, it is possible to do not carry out UV illumination。
In sum, method for cutting wafer in the present invention, first pass through radium-shine cutting technique to cut to its back side 320 from the front 310 of described wafer 300, run through metal level 340 until multiple Cutting Roads 350 of described semiconductor layer 330 to be formed in the face side of described wafer 300；Then the wafer being formed with Cutting Road 350 being carried out grinding back surface, the wafer after making described Cutting Road 350 run through grinding, to form the chip 370 of multiple separation。Due in the middle of the cutting process of wafer, do not use machine cuts, such that it is able to avoid the cutting stress produced due to machine cuts to cause the splintering problem of thin wafer, it also apply be applicable to cutting low-k wafer simultaneously, with the metal interlevel lamination avoiding the cutting stress produced due to machine cuts to produce。Additionally, its be also prevented from grind after wafer generation warpage。
It is pointed out that any change that the specific embodiment of the present invention done by one skilled in the art scope all without departing from claims of the present invention。Correspondingly, the scope of the claims of the present invention is also not limited only to previous embodiment。
Claims (5)
1. a method for cutting wafer, it is characterised in that comprising:
Thering is provided wafer, this wafer includes front and the back side answered with this vis-a-vis；
By radium-shine cutting technique just cutting towards its back side from described wafer, form multiple Cutting Road with the face side at described wafer；
The front of wafer being formed with described Cutting Road attaches and grinds glued membrane；
Grinding back surface is carried out to being pasted with the wafer grinding glued membrane, so that described Cutting Road runs through the wafer after grinding, thus forming the chip of multiple separation,
The described wafer provided also includes semiconductor layer and the metal level being formed on described semiconductor layer, and described metal level is positioned at the front of described wafer,
Described Cutting Road runs through described metal level from the front of described wafer, and its end extends into described semiconductor layer。
2. method for cutting wafer according to claim 1, it is characterised in that it also includes: attach fixing glued membrane at the back side of the wafer being formed with separating chips, and by this fixing glued membrane, wafer is fixed on wafer frame；With
Remove the grinding glued membrane on the front of the wafer being fixed on described wafer frame。
3. method for cutting wafer according to claim 2, it is characterised in that described grinding glued membrane is ultraviolet glued membrane,
The grinding glued membrane removed on the front of the wafer being fixed on described wafer frame includes:
This ultraviolet glued membrane is carried out ultraviolet illumination；With
Remove described ultraviolet glued membrane。
4. method for cutting wafer according to claim 1, it is characterised in that the fixing glued membrane attached at the back side of the wafer being formed with separating chips is dicing tape or blue film。
5. method for cutting wafer according to claim 4, it is characterised in that described semiconductor layer is silicon wafer layer。
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| CN201310382986.9A CN103441104B (en) | 2013-08-29 | 2013-08-29 | Method for cutting wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310382986.9A CN103441104B (en) | 2013-08-29 | 2013-08-29 | Method for cutting wafer |
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| CN103441104A CN103441104A (en) | 2013-12-11 |
| CN103441104B true CN103441104B (en) | 2016-06-22 |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6189208B2 (en) * | 2013-12-26 | 2017-08-30 | 株式会社ディスコ | Wafer processing method |
| CN105575870B (en) * | 2014-10-13 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN104637878B (en) * | 2015-02-11 | 2017-08-29 | 华天科技（昆山）电子有限公司 | The wafer-level packaging cutting method of ultra-narrow pitch |
| CN109909623A (en) * | 2017-12-12 | 2019-06-21 | 中芯国际集成电路制造(北京)有限公司 | Cutting method for wafer |
| CN108582529B (en) * | 2018-04-13 | 2020-05-05 | 无锡奥夫特光学技术有限公司 | Cutting method of optical window |
| US10388535B1 (en) * | 2018-05-25 | 2019-08-20 | Powertech Technology Inc. | Wafer processing method with full edge trimming |
| CN109545678B (en) * | 2018-11-12 | 2021-04-02 | 紫光宏茂微电子(上海)有限公司 | Wafer cutting process |
| CN111668110B (en) * | 2019-03-08 | 2022-11-01 | 矽磐微电子(重庆)有限公司 | Packaging method of semiconductor chip |
| CN109968552B (en) * | 2019-03-26 | 2021-09-17 | 紫光宏茂微电子(上海)有限公司 | Integrated wafer cutting knife and wafer cutting method |
| CN112530865A (en) * | 2019-08-30 | 2021-03-19 | 中国科学院沈阳自动化研究所 | Post-thinning wafer scribing method based on water-guided laser processing technology |
| CN111128879A (en) * | 2019-12-27 | 2020-05-08 | 青岛歌尔微电子研究院有限公司 | Wafer and cutting method thereof |
| CN111446161B (en) * | 2020-03-11 | 2023-03-21 | 绍兴同芯成集成电路有限公司 | Wafer cutting method |
| CN115020339A (en) * | 2022-05-23 | 2022-09-06 | 深圳米飞泰克科技股份有限公司 | Wafer cutting method |
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| CN1728342A (en) * | 2002-03-12 | 2006-02-01 | 浜松光子学株式会社 | Substrate dividing method |
| CN101621025A (en) * | 2008-07-02 | 2010-01-06 | 台湾积体电路制造股份有限公司 | Method for separating a plurality of semiconductor element dies on upper surface of wafer substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005252196A (en) * | 2004-03-08 | 2005-09-15 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP2010206044A (en) * | 2009-03-05 | 2010-09-16 | Toshiba Corp | Method of manufacturing semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728342A (en) * | 2002-03-12 | 2006-02-01 | 浜松光子学株式会社 | Substrate dividing method |
| CN101621025A (en) * | 2008-07-02 | 2010-01-06 | 台湾积体电路制造股份有限公司 | Method for separating a plurality of semiconductor element dies on upper surface of wafer substrate |
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Effective date of registration: 20180202 Address after: 101400 Beijing city Huairou District Yanqi Yanqi Economic Development Zone South four Street No. 25 Building No. 3 hospital No. 307 Patentee after: Beijing Zhongke micro Intellectual Property Service Co., Ltd. Address before: 214000 Jiangsu New District of Wuxi, Taihu international science and Technology Parks Linghu Road No. 200 China Sensor Network International Innovation Park building D1 Patentee before: National Center for Advanced Packaging Co., Ltd. |