CN103199705B - Reduction-voltage type voltage-stabilized power source with load minimum energy consumption point tracking function - Google Patents

Abstract

The invention provides a reduction-voltage type voltage-stabilized power source with a load minimum energy consumption point tracking function, and belongs to the technical field of electronics. The reduction-voltage type voltage-stabilized power source with the load minimum energy consumption point tracking function is used for providing power for a digital integrated circuit with low voltage and low power consumption, and comprises a BUCK power converter and a control circuit. The control circuit comprises a turn-on time generation module, a digital control module, a digital to analog converter, a comparator and a voltage-controlled oscillator. According to the reduction-voltage type voltage-stabilized power source with the load minimum energy consumption point tracking function, energy sent to an external load by the power source in various opening-closing periods of a power tube is enabled to be same through adjustment of output voltage and turn-on time of the power tube in the BUCK power converter. Meanwhile, a load minimum energy consumption point is detected through a reduction-voltage tracking manner, the turn-on time of the power tube is simultaneously adjusted during the reduction-voltage tracking process, and constant energy sent to the load every time the power tube is opened is ensured. According to the reduction-voltage type voltage-stabilized power source with the load minimum energy consumption point tracking function, a digital circuit is more adopted for achievement. Compared with the manner that double-capacitor energy is used for sampling, the reduction-voltage type voltage-stabilized power source with the load minimum energy consumption point tracking function can save areas of chips and is more beneficial for integration of the power source.

Description

There is the buck stabilized voltage power supply of least-loaded energy ezpenditure point tracking function

Technical field

There is the buck stabilized voltage power supply of least-loaded energy ezpenditure point tracking function, belong to electronic technology field, for providing power supply to the digital integrated circuit of low pressure, low-power consumption.

Background technology

The energy consumption E of digital integrated circuit _tOTcomprise two parts: dynamic energy consumption E _aCTwith static energy consumption E _lEAK.Dynamic energy consumption is caused by the switch motion of digital integrated circuit, E _aCT=α NCV _dD ², wherein α is the activity factor of digital integrated circuit, and N has been the clock cycle number of the required work of Given task, and C is the equivalent load capacitance of digital integrated circuit to power supply, V _dDit is the supply voltage of digital integrated circuit.Static energy consumption is caused by the various leakage mechanisms of digital integrated circuit, E _lEAK=I _lEAKv _dDnT _clk, wherein I _lEAKthe leakage current of digital integrated circuit, T _clkit is the operating clock cycle of digital integrated circuit.As operating voltage V _dDduring rising, circuit completes Given task, and digital integrated circuit dynamic energy consumption increases; Meanwhile, voltage V _dDrising can cause T _clkreduce, T _clkreduce then can cause and leak energy consumption reduction.So, when digital integrated circuit works, there is a voltage V _mEP, when the operating voltage of digital integrated circuit is V _mEPtime, complete Given task, circuit total energy consumption is minimum, and this operating voltage is defined as minimal energy consumption point (MEP, Minimum Energy Point).

The people such as Benton H.Calhoun demonstrate the existence (see document " Characterizing and modelingminimum energy operation for subthreshold circuits ", ISLPED, 2004, pp.90-95) of least energy point.The people such as Yogesh K.Ramadass utilize DAC, capacitive energy sampling and least energy tracing algorithm module composition loop make buck minimal energy consumption point tracking (MEPT, Minimum energy point tracking) DC-DC converter is (see document " Minimumenergy tracking loop with embedded DC – DC converter enabling ultra-low-voltage operation downto250mV in65nm CMOS ", JSSC, 2008, Vol.43, No.1, pp.256-265), the two capacitance method of this converter carries out energy sampled, electric capacity occupies larger chip area, power inverter adopts PFM(Pulse FrequencyModulation) modulating mode.

The method that the minimal energy consumption point tracking circuit that the present invention proposes combines fixing ON time constructs one can the buck stabilized voltage power supply of track digital integrated circuit minimal energy consumption point, utilize the method for fixing ON time, ensure that each energy transmitted is equal, compared to the method utilizing two electric capacity, save chip area, be more conducive to the system integration.

Summary of the invention

Technical problem to be solved by this invention, be just to provide a kind of buck stabilized voltage power supply with least-loaded energy ezpenditure point tracking function, this buck stabilized voltage power supply can find least-loaded energy ezpenditure point.The clock cycle of carry digital circuit working is T _clk.When MEPT control circuit makes each power tube open by regulation output voltage and power tube ON time, to output to the energy of load identical for power supply.Meanwhile, detect load under current output voltage, work M cycle internal power pipe conducting number, by MT under current output voltage _clkmT under the conducting number of times of the power tube in the time and last output voltage _clktime internal power pipe conducting number of times compares.Turned down by height by initial voltage by output voltage with certain step-length, the ON time of regulating power pipe, delivers to the energy constant of load when ensureing that each power tube is opened simultaneously.If certain MT _clktime internal power pipe conducting number of times is greater than MT under an output voltage _clkconducting number of times in time, output voltage upwards regulates a step-length, the minimal energy consumption point operating voltage of this output voltage and load.

Detailed technology scheme of the present invention is:

There is the buck stabilized voltage power supply of least-loaded energy ezpenditure point tracking function, as shown in Figure 1, comprise BUCK power inverter and control circuit.

Described BUCK power inverter at least comprises an a power tube PMOS MP and power NMOS tube MN, and described power tube PMOS MP and power NMOS tube MN leaks connection altogether, and wherein the source electrode of power tube PMOS MP meets DC offset voltage V _ithe source ground of power NMOS tube MN, the grid of power tube PMOS MP meets gate control voltage PG, power NMOS tube MN grid meet gate control voltage NG, the common leakage tie point of power tube PMOS MP and power NMOS tube MN exports the output voltage V of BUCK power inverter by an energy storage inductor L _o(operating voltage V needed for external load LOAD _o), output voltage V _oand be connected with a filter capacitor C between ground.

Described control circuit comprises comparator, digital control module, voltage controlled oscillator, digital to analog converter, ON time generation module.The output voltage V of BUCK power inverter _owith the reference voltage V that digital to analog converter produces _rEFthe inverting input of input comparator and in-phase input end compare respectively, and the output signal CMP_OUT of comparator is input to ON time generation module and digital control module respectively; The output voltage V of BUCK power inverter _othere is provided power supply to voltage controlled oscillator, the clock signal CLK_VCO of voltage controlled oscillator is input to digital control module; The operating clock signals CLKM of BUCK power inverter, its frequency is the switching frequency of PSM mode power pipe, is input to ON time generation module and digital control module respectively.Described digital control module has two output signals, an output signal DT inputs ON time generation module and produces different duty cycle signals control signal PG and NG to control ON time generation module, and another output signal DV inputs digital to analog converter and produces different reference voltage V with domination number weighted-voltage D/A converter _rEF; The ON time control signal PG that ON time generation module produces connects the grid of power tube PMOS MP in BUCK power inverter as the gate control voltage of power tube PMOS MP in BUCK power inverter, and the ON time control signal NG that ON time generation module produces connects the grid of power NMOS tube MN in BUCK power inverter as the gate control voltage of power NMOS tube MN in BUCK power inverter.

As shown in Figure 2, described ON time generation module, comprises a d type flip flop, submodule that a submodule producing the conducting control time signal PG of power tube PMOS MP in BUCK power inverter and one produce the conducting control time NG of power NMOS tube MN in BUCK power inverter.Produce the submodule of the conducting control time PG of power tube PMOS MP in BUCK power inverter, comprise the first delay line that k delay cell Dm is connected in series, a k road selector MUX1, with door 1 and with door 3; Wherein delay cell Dmi(i=1,2 ..., output k) connects the input of delay cell Dm (i+1) and i-th input of a k road selector MUX1 respectively.Produce the submodule of the conducting control time NG of power NMOS tube MN in BUCK power inverter, comprise the second delay line that k delay cell Dn is connected in series, the 2nd k road selector MUX2, with door 2 and with door 4; Wherein delay cell Dni(i=1,2 ..., output k) connects the input of delay cell Dn (i+1) and i-th input of the 2nd k road selector MUX1 respectively.The trigger end D(high level that the output signal CMP_OUT of comparator CMP connects d type flip flop is effective), the Q output of d type flip flop connects and door 3 and an input with door 4 respectively; In the submodule of conducting control time PG producing power tube PMOS MP in BUCK power inverter, operating clock signals CLKM mono-aspect of BUCK power inverter connects and door 1 input, connects another input with door 1 on the other hand by the inhibit signal CLKMDP produced after the first delay line and a k road selector MUX1; With the output signal of door 1 and the Q output of d type flip flop output signal through with door 3 phase with after obtain the conducting control time signal PG of power tube PMOS MP in BUCK power inverter.In the submodule of conducting control time NG producing power NMOS tube MN in BUCK power inverter, operating clock signals CLKM mono-aspect of BUCK power inverter connects and door 2 input, connects another input with door 2 on the other hand by the inhibit signal CLKMDN produced after the second delay line and the 2nd k road selector MUX2; With the output signal of door 2 and the Q output of d type flip flop output signal through with door 4 phase with after obtain the conducting control time signal NG of power NMOS tube MN in BUCK power inverter.The control end that the output signal DT of digital control module meets a k road selector MUX1 and the 2nd k road selector MUX2 respectively has the inhibit signal CLKMDP of different time of delay or CLKMDN in order to gating and exports.

Described digital control module detects at current output voltage V _ounder, external load LOAD works the number of cycles of power tube PMOS MP or power NMOS tube MN conducting in BUCK power inverter in M cycle time, and with last output voltage V _oin lower loaded work piece M cycle time, in BUCK power inverter, the number of cycles of power tube PMOS MP or power NMOS tube MN conducting is compared, and chooses suitable output voltage V with this _oas external load LOAD minimal energy consumption point voltage; The different control signal DT that digital control module exports, correspond to the ON time of power tube PMOS MP or power NMOS tube MN in different BUCK power inverters; The different control signal DV that digital control module exports, correspond to different reference voltage V _rEF.

As shown in Figure 3, described digital control module is made up of frequency divider, counter, register, digital comparator, forward-backward counter, decoder 1 and decoder 2.The delay of voltage controlled oscillator is identical with the critical path of external load LOAD, external load LOAD often works M cycle, voltage controlled oscillator produces the CLK_VCO signal in M/2 cycle, frequency divider carries out M/2 frequency division to CLK_VCO signal, like this, when external load LOAD works M cycle, frequency divider just produces a high signal.When comparator output signal CMP_OUT is high, the operating clock signals CLKM of counter to BUCK power inverter counts.When frequency divider exports generation rising edge, represent M the cycle of loaded work piece.The count value in the last M cycle stored in counter and register compares, after having compared, by the count value in this cycle stored in register by digital comparator.Forward-backward counter carries out adding 1 or subtract 1 operation according to the result compared.The Output rusults of forward-backward counter produces DT signal and is used for controlling conducting control time signal PG or NG that ON time generation module produces power tube in BUCK power inverter after decoder 1 decoding; The Output rusults of forward-backward counter produces DV signal and is used for domination number weighted-voltage D/A converter and produces different reference voltage V after decoder 2 decoding _rEF.

In described digital control module, the reference voltage V of digital to analog converter output can be set by the value arranging forward-backward counter _rEFand conducting control time signal PG or NG of power tube in BUCK power inverter, to keep power delivery in the switch periods of each power tube constant to the energy of external load LOAD.

The buck stabilized voltage power supply with least-loaded energy ezpenditure point tracking function proposed by the invention utilizes the method for fixing ON time, when ensureing that each power tube is opened, to send the energy of external load LOAD to equal for power supply, followed the trail of the minimal energy consumption point of external load LOAD by the number of times counted and compare power tube conducting.Control circuit have employed digital circuit more, and utilizes the method for two capacitive energy sampling to compare, and method proposed by the invention can saving chip area, is more conducive to the integrated of power supply.

Accompanying drawing explanation

Fig. 1 is the voltage reducing type voltage stabilizing circuit structured flowchart with least-loaded energy ezpenditure point tracking function.

Fig. 2 is ON time generation module structured flowchart.

Fig. 3 is digital control module structured flowchart.

Fig. 4 is minimal energy consumption point tracking algorithm flow chart.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.

There is the buck stabilized voltage power supply of least-loaded energy ezpenditure point tracking function, as shown in Figure 1, comprise BUCK power inverter and control circuit.

Described BUCK power inverter at least comprises an a power tube PMOS MP and power NMOS tube MN, and described power tube PMOS MP and power NMOS tube MN leaks connection altogether, and wherein the source electrode of power tube PMOS MP meets DC offset voltage V _ithe source ground of power NMOS tube MN, the grid of power tube PMOS MP meets gate control voltage PG, power NMOS tube MN grid meet gate control voltage NG, the common leakage tie point of power tube PMOS MP and power NMOS tube MN exports the output voltage V of BUCK power inverter by an energy storage inductor L _o(operating voltage V needed for external load LOAD _o), output voltage V _oand be connected with a filter capacitor C between ground.

Described control circuit comprises comparator, digital control module, voltage controlled oscillator, digital to analog converter, ON time generation module.The output voltage V of BUCK power inverter _owith the reference voltage V that digital to analog converter produces _rEFthe inverting input of input comparator and in-phase input end compare respectively, and the output signal CMP_OUT of comparator is input to ON time generation module and digital control module respectively; The output voltage V of BUCK power inverter _othere is provided power supply to voltage controlled oscillator, the clock signal CLK_VCO of voltage controlled oscillator is input to digital control module; The operating clock signals CLKM of BUCK power inverter, its frequency is the switching frequency of PSM mode power pipe, is input to ON time generation module and digital control module respectively.Described digital control module has two output signals, an output signal DT inputs ON time generation module and produces different duty cycle signals control signal PG and NG to control ON time generation module, and another output signal DV inputs digital to analog converter and produces different reference voltage V with domination number weighted-voltage D/A converter _rEF; The ON time control signal PG that ON time generation module produces connects the grid of power tube PMOS MP in BUCK power inverter as the gate control voltage of power tube PMOS MP in BUCK power inverter, and the ON time control signal NG that ON time generation module produces connects the grid of power NMOS tube MN in BUCK power inverter as the gate control voltage of power NMOS tube MN in BUCK power inverter.

Provided by the invention have in the buck stabilized voltage power supply of least-loaded energy ezpenditure point tracking function, and digital control module, ON time generation module are two key modules of the present invention.Digital control module exports different control word DT and DV to ON time generation module and digital to analog converter to produce different power tube ON time and reference voltage.Simultaneously, digital control module detects under current output voltage, in the number of cycles of given loaded work piece time internal power pipe conducting, and compared with the number of cycles of loaded work piece time internal power pipe conducting given under last output voltage, choose suitable voltage as least-loaded energy ezpenditure point voltage.The input of ON time module is the output control word DT of digital control module, different ON time that different control word is corresponding.The input of digital to analog converter is the output control word DV of digital control module, different reference voltage V that different control words is corresponding _rEF.

As shown in Figure 2, described ON time generation module, comprises a d type flip flop, submodule that a submodule producing the conducting control time signal PG of power tube PMOS MP in BUCK power inverter and one produce the conducting control time NG of power NMOS tube MN in BUCK power inverter.Produce the submodule of the conducting control time PG of power tube PMOS MP in BUCK power inverter, comprise the first delay line that k delay cell Dm is connected in series, a k road selector MUX1, with door 1 and with door 3; Wherein delay cell Dmi(i=1,2 ..., output k) connects the input of delay cell Dm (i+1) and i-th input of a k road selector MUX1 respectively.Produce the submodule of the conducting control time NG of power NMOS tube MN in BUCK power inverter, comprise the second delay line that k delay cell Dn is connected in series, the 2nd k road selector MUX2, with door 2 and with door 4; Wherein delay cell Dni(i=1,2 ..., output k) connects the input of delay cell Dn (i+1) and i-th input of the 2nd k road selector MUX1 respectively.The trigger end D(high level that the output signal CMP_OUT of comparator CMP connects d type flip flop is effective), the Q output of d type flip flop connects and door 3 and an input with door 4 respectively; In the submodule of conducting control time PG producing power tube PMOS MP in BUCK power inverter, operating clock signals CLKM mono-aspect of BUCK power inverter connects and door 1 input, connects another input with door 1 on the other hand by the inhibit signal CLKMDP produced after the first delay line and a k road selector MUX1; With the output signal of door 1 and the Q output of d type flip flop output signal through with door 3 phase with after obtain the conducting control time signal PG of power tube PMOS MP in BUCK power inverter.In the submodule of conducting control time NG producing power NMOS tube MN in BUCK power inverter, operating clock signals CLKM mono-aspect of BUCK power inverter connects and door 2 input, connects another input with door 2 on the other hand by the inhibit signal CLKMDN produced after the second delay line and the 2nd k road selector MUX2; With the output signal of door 2 and the Q output of d type flip flop output signal through with door 4 phase with after obtain the conducting control time signal NG of power NMOS tube MN in BUCK power inverter.The control end that the output signal DT of digital control module meets a k road selector MUX1 and the 2nd k road selector MUX2 respectively has the inhibit signal CLKMDP of different time of delay or CLKMDN in order to gating and exports.

Described digital control module detects at current output voltage V _ounder, external load LOAD works the number of cycles of power tube PMOS MP or power NMOS tube MN conducting in BUCK power inverter in M cycle time, and with last output voltage V _oin lower loaded work piece M cycle time, in BUCK power inverter, the number of cycles of power tube PMOS MP or power NMOS tube MN conducting is compared, and chooses suitable output voltage V with this _oas external load LOAD minimal energy consumption point voltage; The different control signal DT that digital control module exports, correspond to the ON time of power tube PMOS MP or power NMOS tube MN in different BUCK power inverters; The different control signal DV that digital control module exports, correspond to different reference voltage V _rEF.

As shown in Figure 3, described digital control module is made up of frequency divider, counter, register, digital comparator, forward-backward counter, decoder 1 and decoder 2.The delay of voltage controlled oscillator is identical with the critical path of external load LOAD, external load LOAD often works M cycle, voltage controlled oscillator produces the CLK_VCO signal in M/2 cycle, frequency divider carries out M/2 frequency division to CLK_VCO signal, like this, when external load LOAD works M cycle, frequency divider just produces a high signal.When comparator output signal CMP_OUT is high, the operating clock signals CLKM of counter to BUCK power inverter counts.When frequency divider exports generation rising edge, represent M the cycle of loaded work piece.The count value in the last M cycle stored in counter and register compares, after having compared, by the count value in this cycle stored in register by digital comparator.Forward-backward counter carries out adding 1 or subtract 1 operation according to the result compared.The Output rusults of forward-backward counter produces DT signal and is used for controlling conducting control time signal PG or NG that ON time generation module produces power tube in BUCK power inverter after decoder 1 decoding; The Output rusults of forward-backward counter produces DV signal and is used for domination number weighted-voltage D/A converter and produces different reference voltage V after decoder 2 decoding _rEF.

In described digital control module, the reference voltage V of digital to analog converter output can be set by the value arranging forward-backward counter _rEFand conducting control time signal PG or NG of power tube in BUCK power inverter, to keep power delivery in the switch periods of each power tube constant to the energy of external load LOAD.

Introduce the general principle that control circuit MEPT works below.The energy balance model of BUCK converter is

ΔE _IN=ΔE _R+ΔE _C+ΔE _L（1）

Wherein, Δ E _iN, Δ E _r, Δ E _c, Δ E _lbe respectively the variable quantity that power supply in a switch periods is supplied to the energy of BUCK input, the energy of load consumption, the variable quantity of capacitance energy storage and inductive energy storage.The variable quantity of i-th cycle capacitance energy storage, equal the i-th+1 cycle when starting the energy storage of electric capacity deduct the energy storage of i-th cycle electric capacity when starting,

ΔE _C=E _C,(i+1)T-E _C,iT（2）

In dcm mode, Δ E _l≡ 0

For input energy Δ E _iN,

${\mathrm{\ΔE}}_{\mathrm{IN}}=\underset{0}{\overset{T_{\mathrm{on}}}{\∫}}{V}_{I}i\left(t\right)\mathrm{dt}=\frac{1}{2}{V}_I{T}_{\mathrm{on}}{I}_{\mathrm{PK}}---\left(3\right)$

$I_{\mathrm{PK}}=\frac{V_I-V_O}{L}{T}_{\mathrm{on}}---\left(4\right)$

(4) are substituted into (3) obtain

${\mathrm{\ΔE}}_{\mathrm{IN}}=\frac{1}{2L}{T}_{\mathrm{on}}^2(V_I-V_O)V_I---\left(5\right)$

And within a loaded work piece M cycle of MEPT, K the clock cycle if DC-DC has worked, wherein input energy n, stride across m.

If so ignore the energy of electric capacity consumption, the energy of load consumption just equals the energy that n cycle has input altogether.

So have:

$E_R=n\frac{1}{2L}{T}_{\mathrm{on}}^{\text{2}}(V_I-V_O)V_I---\left(6\right)$

V _ifixing, by regulating V _oand T _on, it is constant to give load energy when each power tube is opened, so the energy of load M cycle internal consumption just can by judging the detection of n.

The present invention's minimal energy consumption point tracking algorithm used is as follows: as shown in Figure 4, when loop detection starts, arrange initial output voltage and corresponding ON time control word.The initial output voltage of digital to analog converter and the initial turn-on time of power tube can be set by the initial value arranging forward-backward counter, constant with hold period input energy.Setting power Guan Yi MT simultaneously _clkconducting number of times P in time, and stored in register.Afterwards, automatically by output voltage V _oreduce a fixing stepping X millivolt, simultaneously the ON time T of Modulating Power pipe _on(in whole testing process hold period input energy and periodical input energy coincidence time initial), calculates the turn-on cycle number Q at the individual all after date power tubes of loaded work piece M afterwards.Relatively the size of P and Q, if Q is less than P, so replaces P by Q stored in stockpile device, continues output voltage to be reduced a stepping X millivolt, simultaneously the ON time of Modulating Power pipe, again goes afterwards to calculate turn-on cycle number again.If Q is greater than P, so then output voltage is increased a stepping, adjust corresponding ON time simultaneously.The output voltage in this time is exactly the minimum point of load consumption energy, namely have found least energy point, terminates loop work afterwards.

The buck stabilized voltage power supply with least-loaded energy ezpenditure point tracking function proposed by the invention utilizes the method for fixing ON time, when ensureing that each power tube is opened, to send the energy of external load LOAD to equal for power supply, followed the trail of the minimal energy consumption point of external load LOAD by the number of times counted and compare power tube conducting.Control circuit have employed digital circuit more, and utilizes the method for two capacitive energy sampling to compare, and method proposed by the invention can saving chip area, is more conducive to the integrated of power supply.

Claims (4)

1. there is the buck stabilized voltage power supply of least-loaded energy ezpenditure point tracking function, comprise BUCK power inverter and control circuit;

Described BUCK power inverter at least comprises an a power tube PMOS MP and power NMOS tube MN, and described power tube PMOS MP and power NMOS tube MN leaks connection altogether, and wherein the source electrode of power tube PMOS MP meets DC offset voltage V _ithe source ground of power NMOS tube MN, the grid of power tube PMOS MP meets gate control voltage PG, power NMOS tube MN grid meet gate control voltage NG, the common leakage tie point of power tube PMOS MP and power NMOS tube MN exports the output voltage V of BUCK power inverter by an energy storage inductor L _o, output voltage V _oand be connected with a filter capacitor C between ground;

Described control circuit comprises comparator, digital control module, voltage controlled oscillator, digital to analog converter, ON time generation module; The output voltage V of BUCK power inverter _owith the reference voltage V that digital to analog converter produces _rEFthe inverting input of input comparator and in-phase input end compare respectively, and the output signal CMP_OUT of comparator is input to ON time generation module and digital control module respectively; The output voltage V of BUCK power inverter _othere is provided power supply to voltage controlled oscillator, the clock signal CLK_VCO of voltage controlled oscillator is input to digital control module; The operating clock signals CLKM of BUCK power inverter, its frequency is the switching frequency of PSM mode power pipe, is input to ON time generation module and digital control module respectively; Described digital control module has two output signals, an output signal DT inputs ON time generation module and produces different duty cycle signals control signal PG and NG to control ON time generation module, and another output signal DV inputs digital to analog converter and produces different reference voltage V with domination number weighted-voltage D/A converter _rEF; The ON time control signal PG that ON time generation module produces connects the grid of power tube PMOS MP in BUCK power inverter as the gate control voltage of power tube PMOS MP in BUCK power inverter, and the ON time control signal NG that ON time generation module produces connects the grid of power NMOS tube MN in BUCK power inverter as the gate control voltage of power NMOS tube MN in BUCK power inverter;

Described ON time generation module, comprises a d type flip flop, submodule that a submodule producing the conducting control time signal PG of power tube PMOS MP in BUCK power inverter and one produce the conducting control time NG of power NMOS tube MN in BUCK power inverter;

Produce the submodule of the conducting control time signal PG of power tube PMOS MP in BUCK power inverter, comprise the first delay line that k delay cell Dm is connected in series, a k road selector MUX1, with door 1 and with door 3; Wherein the output of delay cell Dmi connects the input of delay cell Dm (i+1) and i-th input of a k road selector MUX1 respectively; Produce the submodule of the conducting control time NG of power NMOS tube MN in BUCK power inverter, comprise the second delay line that k delay cell Dn is connected in series, the 2nd k road selector MUX2, with door 2 and with door 4; Wherein the output of delay cell Dni connects the input of delay cell Dn (i+1) and i-th input of the 2nd k road selector MUX1 respectively; Wherein i=1,2 ..., k;

The output signal CMP_OUT of comparator CMP meets the trigger end D of d type flip flop, and trigger end is that high level is effective, and the Q output of d type flip flop connects and door 3 and an input with door 4 respectively; In the submodule of conducting control time signal PG producing power tube PMOS MP in BUCK power inverter, operating clock signals CLKM mono-aspect of BUCK power inverter connects and door 1 input, connects another input with door 1 on the other hand by the inhibit signal CLKMDP produced after the first delay line and a k road selector MUX1; With the output signal of door 1 and the Q output of d type flip flop output signal through with door 3 phase with after obtain the conducting control time signal PG of power tube PMOS MP in BUCK power inverter; In the submodule of conducting control time signal NG producing power NMOS tube MN in BUCK power inverter, operating clock signals CLKM mono-aspect of BUCK power inverter connects and door 2 input, connects another input with door 2 on the other hand by the inhibit signal CLKMDN produced after the second delay line and the 2nd k road selector MUX2; With the output signal of door 2 and the Q output of d type flip flop output signal through with door 4 phase with after obtain the conducting control time signal NG of power NMOS tube MN in BUCK power inverter; The control end that the output signal DT of digital control module meets a k road selector MUX1 and the 2nd k road selector MUX2 respectively has the inhibit signal CLKMDP of different time of delay or CLKMDN in order to gating and exports.

2. the buck stabilized voltage power supply with least-loaded energy ezpenditure point tracking function according to claim 1, is characterized in that, described digital control module detects at current output voltage V _ounder, external load LOAD works the number of cycles of power tube PMOS MP or power NMOS tube MN conducting in BUCK power inverter in M cycle time, and with last output voltage V _oin lower loaded work piece M cycle time, in BUCK power inverter, the number of cycles of power tube PMOS MP or power NMOS tube MN conducting is compared, and chooses suitable output voltage V with this _oas external load LOAD minimal energy consumption point voltage; The different control signal DT that digital control module exports, correspond to the ON time of power tube PMOS MP or power NMOS tube MN in different BUCK power inverters; The different control signal DV that digital control module exports, correspond to different reference voltage V _rEF.

3. the buck stabilized voltage power supply with least-loaded energy ezpenditure point tracking function according to claim 2, it is characterized in that, described digital control module is made up of frequency divider, counter, register, digital comparator, forward-backward counter, decoder 1 and decoder 2; The delay of voltage controlled oscillator is identical with the critical path of external load LOAD, external load LOAD often works M cycle, voltage controlled oscillator produces the CLK_VCO signal in M/2 cycle, frequency divider carries out M/2 frequency division to CLK_VCO signal, like this, when external load LOAD works M cycle, frequency divider just produces a high signal; When comparator output signal CMP_OUT is high, the operating clock signals CLKM of counter to BUCK power inverter counts; When frequency divider exports generation rising edge, represent M the cycle of loaded work piece; The count value in the last M cycle stored in counter and register compares, after having compared, by the count value in this cycle stored in register by digital comparator; Forward-backward counter carries out adding 1 or subtract 1 operation according to the result compared; The Output rusults of forward-backward counter produces DT signal and is used for controlling conducting control time signal PG or NG that ON time generation module produces power tube in BUCK power inverter after decoder 1 decoding; The Output rusults of forward-backward counter produces DV signal and is used for domination number weighted-voltage D/A converter and produces different reference voltage V after decoder 2 decoding _rEF.

4. the buck stabilized voltage power supply with least-loaded energy ezpenditure point tracking function according to claim 2, is characterized in that, can be set the reference voltage V of digital to analog converter output by the value arranging forward-backward counter _rEFand conducting control time signal PG or NG of power tube in BUCK power inverter, to keep power delivery in the switch periods of each power tube constant to the energy of external load LOAD.