CN103187404A - Semiconductor chip stacking and packaging structure and process thereof - Google Patents
Semiconductor chip stacking and packaging structure and process thereof Download PDFInfo
- Publication number
- CN103187404A CN103187404A CN2011104581912A CN201110458191A CN103187404A CN 103187404 A CN103187404 A CN 103187404A CN 2011104581912 A CN2011104581912 A CN 2011104581912A CN 201110458191 A CN201110458191 A CN 201110458191A CN 103187404 A CN103187404 A CN 103187404A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- packaging
- base plate
- pad
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Wire Bonding (AREA)
Abstract
Provided are a semiconductor chip stacking and packaging structure and process thereof. The semiconductor chip stacking and packaging structure comprises a plurality of semiconductor chips, a packaging substrate and plastic package material, and is characterized in that an active surface of a semiconductor chip A on the lowermost layer according to the vertical sequence faces downwards, the semiconductor chip A is connected on a circuit layer of the packaging substrate through a solder ball array, bottom filler is filled in the lower surface of the semiconductor chip A, a semiconductor chip B is bonded on the back of the semiconductor chip A by utilizing a bonding layer, and a semiconductor chip C, a semiconductor chip D and semiconductor chips above are stacked above the semiconductor chip B in a layered mode. A pad of the semiconductor chip B, a pad of the semiconductor chip C, a pad of the semiconductor chip D and pads of the semiconductor chips above are connected with the circuit layer on the packaging substrate through welding lines, and packaging chips of the stacking and packaging structure are stacked in a layered mode. The semiconductor chip stacking and packaging structure and the process thereof have the advantages that the manufacturing process is simple, demands of high packaging density can be met, packaging cost is reduced, and meanwhile reliability of packaging is improved.
Description
Technical field
The present invention relates to a kind of structure and manufacture method thereof of semiconductor device, particularly a kind of semiconductor chip piles up encapsulating structure and technology thereof.
Background technology
The integrated level of semiconductor product was doubled by the mole law in per 18 months.Along with the deep development of semiconductor industry, Moore's Law is subjected to increasing obstruction, realize that the cost that Moore's Law pays is more and more higher, yet people stops never but for the semiconductor product performance demands.At present, the approach of seeking to enhance product performance by the direction that changes the semiconductor product packing forms is a new direction, and the three-dimensional systematic encapsulation also produces thereupon.
Three-dimensional stacked encapsulation can be in littler space integrated more semiconductor chip, adopt the product of three-dimensional stacked encapsulation to have higher performance, higher reliability, and lower price.At present, adopt the product of three-dimensional stacked encapsulation, for example memory can be realized bigger memory space, and has realized suitability for industrialized production.
Summary of the invention
The objective of the invention is at the defective that exists in the prior art, provide a kind of semiconductor chip to pile up encapsulating structure and technology thereof.
The present invention includes several semiconductor chips, base plate for packaging, capsulation material, it is characterized in that by the active surface of the lowermost semiconductor chip A of order up and down down, semiconductor chip A is connected on the circuit layer of base plate for packaging through welded ball array, semiconductor chip A lower surface filling underfill material, to improve the reliability of soldered ball, by adhesive layer semiconductor chip B is bonded in the semiconductor chip A back side, semiconductor chip C, semiconductor chip D and above semiconductor chip are stacked in layers above semiconductor chip B, through bonding wire with semiconductor chip B, semiconductor chip C, pad on semiconductor chip D and the above semiconductor chip links to each other with circuit layer on the base plate for packaging.
Described semiconductor chip A adopts inverted structure, and semiconductor chip B, semiconductor chip C, semiconductor chip D and above semiconductor chip adopt positive assembling structure.Semiconductor chip A is connected with base plate for packaging by array of solder balls, and the spacing of welded ball array is 0.050～0.500mm, and the soldered ball diameter is 0.050～0.500mm, the composition of soldered ball is Pb/Sn, SnAgCu, SnAg, welded ball array can be distribution fully or part distributes.Through capsulation material all semiconductor chips and bonding wire are sealed on the base plate for packaging.
One deck or multi-lager semiconductor chip can optionally be piled up in the top of described semiconductor chip B, adopt adhesive layer and wall to fix between the semiconductor chip, reserve the space of bonding wire by wall.
The pad of all semiconductor chip surface, bonding wire are metals such as gold, copper or aluminium.Adhesive layer can adopt the organic polymer elargol, perhaps the inorganic polymer elargol.Base plate for packaging adopts silicon substrate, ceramic substrate, plastic base.
Semiconductor chip piles up the packaging technology of encapsulating structure, it is characterized in that comprising successively following steps:
(1) base plate for packaging of preparation encapsulation usefulness;
(2) the salient point soldered ball of preparation semiconductor chip A lower surface, adopt scolder welding, hot pressing welding or hot sonic soldering to connect mode semiconductor chip A lower surface salient point soldered ball is welded on the pad of base plate for packaging upper surface, semiconductor chip A links to each other with pad on the base plate for packaging through array of solder balls;
(3) at the peripheral injection bottom inserts of semiconductor chip A lower surface and finish curing;
(4) semiconductor chip B is fixed on the upper surface of semiconductor chip A by adhesive layer;
(5) by adhesive layer and wall semiconductor chip C is fixed on the upper surface of semiconductor chip B, and is the bonding wire headspace at wall;
(6) by adhesive layer and wall semiconductor chip D is fixed on the upper surface of semiconductor chip C, and is the bonding wire headspace at wall;
(7) by adhesive layer and wall semiconductor chip E is fixed on the upper surface of semiconductor chip D, and is the bonding wire headspace at wall;
(8) adopting ultrasonic bonding, thermocompression bonding or hot ultrasonic bonding technology welding bonding wire on the pad of semiconductor chip B, semiconductor chip C, semiconductor chip D and semiconductor chip E upper surface and the base plate for packaging between the pad, realize being electrically connected;
(9) by plastic package process with all semiconductor chips and bonding wire sealed package;
(10) pad at the base plate for packaging lower surface is coated with by silk-screen printing technique, plating or evaporation process, by the preparation soldered ball that refluxes, is connected by the soldered ball of base plate for packaging internal circuit with the base plate for packaging lower surface again.
Advantage of the present invention is that technological process of the present invention is simple, cost is low, is fit to large-scale industrial production, and the three-dimensional stacked encapsulating structure of semiconductor chip of the present invention has the reliability height simultaneously, can satisfy high integration to the requirement of semiconductor properties of product.
Description of drawings
The generalized section that Fig. 1 semiconductor chip of the present invention piles up encapsulating structure;
The structural representation of Fig. 2 base plate for packaging;
Fig. 3 adopts flip chip semiconductor chip A to be fixed on the structural representation of base plate for packaging upper surface;
Fig. 4 fills the structural representation of underfill material at semiconductor chip A lower surface;
Fig. 5 is at the fixing structural representation of semiconductor chip B of the upper surface of semiconductor chip A;
Fig. 6 is at the structural representation of the solid semiconductor chip C of upper surface of semiconductor chip B;
Fig. 7 is at the fixing structural representation of semiconductor chip D of the upper surface of semiconductor chip C;
Fig. 8 is at the fixing structural representation of semiconductor chip E of the upper surface of semiconductor chip D;
Fig. 9 realizes the structural representation of electrical connection by bonding wire between semiconductor chip and base plate for packaging;
Figure 10 is by the structural representation of plastic package process with semiconductor chip and bonding wire sealing;
Figure 11 makes the schematic diagram of welded ball array at the base plate for packaging lower surface;
The structural representation of Figure 12 embodiment two;
The structural representation of Figure 13 embodiment three.
Among the figure: 1 semiconductor chip A, 2 semiconductor chip B, 3 adhesive layers, 4 epoxy molding plastics, 5 inserts, 6 base plate for packaging, the 6c interconnection circuit, the pad of 7 base plate for packaging upper surfaces, the pad of 8 chip B, 9 bonding wires, the pad of 10 base plate for packaging upper surfaces, 11 base plate for packaging lower surface pad, the welded ball array of 12 base plate for packaging lower surfaces, 13 semiconductor chip A lower surface array of solder balls, the pad of 14 base plate for packaging upper surfaces, 15 bonding wires, the pad of 16 chip C, 17 adhesive layers, the 17a wall, 18 semiconductor chip C, 19 adhesive layers, the 19a wall, 20 semiconductor chip D, 21 adhesive layers, the 21a wall, 22 semiconductor chip E, 23 bonding wires, the pad of 24 chip D, 25 bonding wires, the pad of 26 chip E.
Embodiment
Embodiment one
Further specify present embodiment below in conjunction with accompanying drawing:
Pressing up and down, the active surface of the lowermost semiconductor chip A of order is connected to semiconductor chip A on the circuit layer of base plate for packaging 6 by welded ball array-13 down.Described base plate for packaging 6 adopts silicon substrate, ceramic substrate, plastic base.The spacing of welded ball array 13 is 0.050～0.500mm, and the soldered ball diameter is 0.050～0.500mm, and the composition of soldered ball is Pb/Sn, and SnAgCu, SnAg, welded ball array can be distribution fully or part distributes.Semiconductor chip A lower surface filling underfill material 5 is to improve the reliability of soldered ball 13.By adhesive layer 3 semiconductor chip B is bonded in the semiconductor chip A back side, semiconductor chip C, semiconductor chip D and above semiconductor chip are stacked in layers above semiconductor chip B, semiconductor chip A adopts inverted structure, and semiconductor chip B, semiconductor chip C, semiconductor chip D and semiconductor chip E adopt positive assembling structure.By bonding wire pad 7, pad 10 on the circuit layer on the pad 8 on semiconductor chip B, semiconductor chip C, semiconductor chip D and the semiconductor chip E, pad 16, pad 24, pad 26 and the base plate for packaging 6 are linked to each other, the packaged chip of stack package structure is stacked in layers and arranges.Can optionally pile up one deck or multi-lager semiconductor chip more than the semiconductor chip B, present embodiment piles up the three-layer semiconductor chip at semiconductor chip B.Adopt between the semiconductor chip adhesive layer 3,17,19,21 and wall 17a, 19a, 21a fix, adhesive layer 3,17,19,21 can adopt the organic polymer elargol, perhaps the inorganic polymer elargol.Reserve the space of bonding wire by wall 17a, 19a, 21a.Capsulation material is sealed in all semiconductor chips and bonding wire on the base plate for packaging.The pad of all semiconductor chip surface, bonding wire are that gold, copper or aluminum metallic material are made.
The processing step of the three-dimensional stacked encapsulation of present embodiment specific implementation semiconductor chip is as follows:
(1) as shown in Figure 2, the used base plate for packaging 6 of preparation encapsulation, material therefor can be silicon substrate, ceramic substrate, plastic base such as BT, FR4, composite material such as A1SiC, MCPCB, wherein the lower surface 6b of the upper face 6a of base plate for packaging and base plate for packaging has comprised the pad of electrical connection effect, and base plate for packaging inside comprises inner multilayer interconnection circuit 6c.
(2) as shown in Figure 3, salient point 13 under the preparation semiconductor chip A lower surface, adopt modes such as scolder welding, hot pressing welding or hot sonic soldering connect chip lower surface salient point to be welded on the pad 14 of base plate for packaging 6 upper surface 6a then, semiconductor chip A links to each other with pad on the base plate for packaging 6 by array of solder balls 13, and 6 internal circuit 6c link to each other with base plate for packaging lower surface pad 11 via base plate for packaging.
(3) as shown in Figure 4, filling underfill material.At the peripheral injection of semiconductor chip A lower surface inserts 5, inserts 5 is made up of the filler of thermosetting polymer and silicon dioxide.Because the capillarity in slit between semiconductor chip A lower surface and the base plate for packaging 6, filler is inhaled into the space between semiconductor chip A and base plate for packaging 6 upper surfaces.Be heated to then about 130 ℃, keep finishing in 3～4 hours curing.
(4) as shown in Figure 5, by adhesive layer 3 semiconductor chip B is fixed on the surface of semiconductor chip A, adhesive can adopt macromolecule paster material or scolder.
(5) as shown in Figure 6, by adhesive layer 17 and wall 17a semiconductor chip C is fixed on the upper surface of semiconductor chip B, wall 17a is the bonding wire headspace.
(6) as shown in Figure 7, by adhesive layer 19 and wall 19a chip D is fixed on the upper surface of chip C, wall 19a is the bonding wire headspace.
(7) by adhesive layer 21 and wall 21a semiconductor chip E is fixed on the upper surface of semiconductor chip D as Fig. 8, wall 21a is the bonding wire headspace.
(8) as shown in Figure 9, the pad 8,16 of semiconductor chip B, semiconductor chip C, semiconductor chip D and semiconductor chip E upper surface, 24 and 26 and base plate for packaging 6 between the pad 7, pad 10 welding bonding wire 9,15,23,25 realize being electrically connected.The bonding wire material can adopt gold thread, aluminum steel or copper cash, and bonding wire craft can adopt ultrasonic bonding, thermocompression bonding or hot ultrasonic bonding technology.
(9) as shown in figure 10, by plastic package process all semiconductor chips and bonding wire are sealed, encapsulant 4 can be selected epoxy molding plastic (EMC) etc. for use.
(10) as shown in figure 11, at pad 11 preparation welded ball arrays 12, scolder can adopt plumber's solder, golden tin solder or Sn-Ag-Cu lead-free scolder.Salient point preparation technology can adopt silk-screen printing technique, evaporation or plating, and reflux technique forms welded ball array 12 then.
Embodiment two
Embodiment two is identical with embodiment one, and difference is that present embodiment has adopted the two-layer packing forms that piles up, referring to Figure 12.
Embodiment three
Embodiment three is identical with embodiment one, and difference is the packing forms that present embodiment adopts three level stack, referring to Figure 13.
Claims (9)
1. a semiconductor chip piles up encapsulating structure, comprise several semiconductor chips, base plate for packaging, capsulation material, it is characterized in that by the active surface of the lowermost semiconductor chip A of order up and down down, semiconductor chip A is connected on the circuit layer of base plate for packaging through welded ball array, semiconductor chip A lower surface filling underfill material, by adhesive layer semiconductor chip B is bonded in the semiconductor chip A back side, semiconductor chip C, semiconductor chip D and above semiconductor chip are stacked in layers above semiconductor chip B, through bonding wire with semiconductor chip B, semiconductor chip C, pad on semiconductor chip D and the above semiconductor chip links to each other with circuit layer on the base plate for packaging, and the packaged chip of stack package structure is stacked in layers and arranges.
2. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that described semiconductor chip A is inverted structure, and semiconductor chip B, semiconductor chip C, semiconductor chip D and above semiconductor chip are positive assembling structure.
3. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that described semiconductor chip A is connected with base plate for packaging by array of solder balls, the spacing of welded ball array is 0.050～0.500mm, the soldered ball diameter is 0.050～0.500mm, the composition of soldered ball is Pb/Sn, SnAgCu, SnAg, welded ball array can be distribution fully or part distributes.
4. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, one deck or multi-lager semiconductor chip can optionally be piled up in the top that it is characterized in that described semiconductor chip B, fix through adhesive layer and wall between the semiconductor chip, reserve the space of bonding wire by wall.
5. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that described capsulation material is sealed in all semiconductor chips and bonding wire on the base plate for packaging.
6. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that pad, the bonding wire material of described all semiconductor chip surface can adopt metals such as gold, copper or aluminium.
7. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that described adhesive layer adopts organic polymer elargol, perhaps inorganic polymer elargol.
8. a kind of semiconductor chip according to claim 1 piles up encapsulating structure, it is characterized in that described base plate for packaging adopts silicon substrate, ceramic substrate, plastic base.
9. packaging technology that semiconductor chip piles up encapsulating structure is characterized in that comprising successively following steps:
(1) base plate for packaging of preparation encapsulation usefulness;
(2) the salient point soldered ball of preparation semiconductor chip A lower surface, adopt scolder welding, hot pressing welding, perhaps hot sonic soldering connects mode semiconductor chip A lower surface salient point soldered ball is welded on the pad of base plate for packaging upper surface, and semiconductor chip A links to each other with pad on the base plate for packaging through array of solder balls;
(3) at the peripheral injection bottom inserts of semiconductor chip A lower surface and finish curing;
(4) semiconductor chip B is fixed on the upper surface of semiconductor chip A by adhesive layer;
(5) by adhesive layer and wall semiconductor chip C is fixed on the upper surface of semiconductor chip B, and is the bonding wire headspace at wall;
(6) by adhesive layer and wall semiconductor chip D is fixed on the upper surface of semiconductor chip C, and is the bonding wire headspace at wall;
(7) by adhesive layer and wall semiconductor chip E is fixed on the upper surface of semiconductor chip D, and is the bonding wire headspace at wall;
(8) adopting ultrasonic bonding, thermocompression bonding between the pad on the pad of semiconductor chip B, semiconductor chip C, semiconductor chip D and semiconductor chip E upper surface and the base plate for packaging, or hot ultrasonic bonding technology welding bonding wire, realize being electrically connected;
(9) by plastic package process with all semiconductor chips and bonding wire sealed package;
(10) pad at the base plate for packaging lower surface is coated with scolder by silk-screen printing technique, plating or evaporation process, by the preparation soldered ball that refluxes, is connected by the soldered ball of base plate for packaging internal circuit with the base plate for packaging lower surface again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104581912A CN103187404A (en) | 2011-12-31 | 2011-12-31 | Semiconductor chip stacking and packaging structure and process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104581912A CN103187404A (en) | 2011-12-31 | 2011-12-31 | Semiconductor chip stacking and packaging structure and process thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103187404A true CN103187404A (en) | 2013-07-03 |
Family
ID=48678495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104581912A Pending CN103187404A (en) | 2011-12-31 | 2011-12-31 | Semiconductor chip stacking and packaging structure and process thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187404A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538368A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Three-dimensional stacking packaging structure based on secondary plastic packaging technology and preparing method thereof |
| CN105280562A (en) * | 2014-05-27 | 2016-01-27 | 爱思开海力士有限公司 | Flexible stack package having wing portions |
| CN109727913A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN110660891A (en) * | 2018-06-29 | 2020-01-07 | 合肥彩虹蓝光科技有限公司 | Flip-chip device packaging method and structure |
| CN112908945A (en) * | 2021-01-12 | 2021-06-04 | 江苏晶凯半导体技术有限公司 | Packaging assembly, electronic equipment and packaging method |
| CN113629021A (en) * | 2021-08-09 | 2021-11-09 | 长江存储科技有限责任公司 | Semiconductor device package structure and manufacturing method thereof |
| WO2024016505A1 (en) * | 2022-07-22 | 2024-01-25 | 长鑫存储技术有限公司 | Semiconductor stack structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030015803A1 (en) * | 2001-07-20 | 2003-01-23 | Optosys Technologies Gmbh | High-density multichip module and method for manufacturing the same |
| CN1441469A (en) * | 2002-02-25 | 2003-09-10 | 精工爱普生株式会社 | Semiconductor water, semiconductor device and their producing method, circuit board and instrument |
| CN1484308A (en) * | 2002-09-17 | 2004-03-24 | ���˻�˹�����̩�˹ɷ�����˾ | Open type multi-chip stacking package unit |
| US20050009236A1 (en) * | 1996-05-20 | 2005-01-13 | Ball Michael B. | Method of fabrication of stacked semiconductor devices |
| CN102185090A (en) * | 2011-03-29 | 2011-09-14 | 晶科电子（广州）有限公司 | Luminescent device adopting COB (chip on board) packaging and manufacturing method thereof |
| CN202434508U (en) * | 2011-12-31 | 2012-09-12 | 刘胜 | Semiconductor chip stacking and encapsulating structure |
-
2011
- 2011-12-31 CN CN2011104581912A patent/CN103187404A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050009236A1 (en) * | 1996-05-20 | 2005-01-13 | Ball Michael B. | Method of fabrication of stacked semiconductor devices |
| US20030015803A1 (en) * | 2001-07-20 | 2003-01-23 | Optosys Technologies Gmbh | High-density multichip module and method for manufacturing the same |
| CN1441469A (en) * | 2002-02-25 | 2003-09-10 | 精工爱普生株式会社 | Semiconductor water, semiconductor device and their producing method, circuit board and instrument |
| CN1484308A (en) * | 2002-09-17 | 2004-03-24 | ���˻�˹�����̩�˹ɷ�����˾ | Open type multi-chip stacking package unit |
| CN102185090A (en) * | 2011-03-29 | 2011-09-14 | 晶科电子（广州）有限公司 | Luminescent device adopting COB (chip on board) packaging and manufacturing method thereof |
| CN202434508U (en) * | 2011-12-31 | 2012-09-12 | 刘胜 | Semiconductor chip stacking and encapsulating structure |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105280562A (en) * | 2014-05-27 | 2016-01-27 | 爱思开海力士有限公司 | Flexible stack package having wing portions |
| CN105280562B (en) * | 2014-05-27 | 2019-09-13 | 爱思开海力士有限公司 | Flexible stack package with alar part |
| CN104538368A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Three-dimensional stacking packaging structure based on secondary plastic packaging technology and preparing method thereof |
| CN109727913A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN110660891A (en) * | 2018-06-29 | 2020-01-07 | 合肥彩虹蓝光科技有限公司 | Flip-chip device packaging method and structure |
| CN112908945A (en) * | 2021-01-12 | 2021-06-04 | 江苏晶凯半导体技术有限公司 | Packaging assembly, electronic equipment and packaging method |
| CN113629021A (en) * | 2021-08-09 | 2021-11-09 | 长江存储科技有限责任公司 | Semiconductor device package structure and manufacturing method thereof |
| WO2024016505A1 (en) * | 2022-07-22 | 2024-01-25 | 长鑫存储技术有限公司 | Semiconductor stack structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103187404A (en) | Semiconductor chip stacking and packaging structure and process thereof | |
| TWI355061B (en) | Stacked-type chip package structure and fabricatio | |
| US8138023B2 (en) | Method for forming laminated structure and method for manufacturing semiconductor device using the method thereof | |
| KR101190920B1 (en) | Stacked semiconductor package and method of manufacturing thereof | |
| US7649248B2 (en) | Stack package implementing conductive support | |
| US20130099393A1 (en) | Stacked Semiconductor Package | |
| CN102867800A (en) | Connecting function chips to a package to form package-on-package | |
| JP2008166439A (en) | Semiconductor device and manufacturing method thereof | |
| WO2013106973A1 (en) | Package-on-package semiconductor chip packaging structure and technology | |
| KR20110124063A (en) | Stack type semiconductor package | |
| CN101477979B (en) | Multi-chip encapsulation body | |
| CN102176444B (en) | High integration level system in package (SIP) structure | |
| CN202434509U (en) | Stackable semiconductor chip packaging structure | |
| CN101872749B (en) | Recess chip packaging structure and laminated packaging structure using same | |
| CN101930956B (en) | Chip packaging structure and manufacturing method thereof | |
| CN202025746U (en) | High integrated level SiP structure | |
| CN202394859U (en) | Semiconductor encapsulating structure | |
| CN102176450A (en) | High-density system in package (SIP) structure | |
| CN202434508U (en) | Semiconductor chip stacking and encapsulating structure | |
| CN103915423A (en) | Three-dimensional stack-packaging structure and method for chips | |
| CN104681499B (en) | Package stack structure and method for fabricating the same | |
| KR20110138788A (en) | Stack type semiconductor package | |
| CN110634856A (en) | Flip-chip and wire bonding hybrid packaging structure and packaging method thereof | |
| CN201994292U (en) | High-density system-level packaging structure | |
| TWI387068B (en) | Cavity chip package structure and package-on-package using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130703 |