CN103137563A - Flash memory structure achieved on vertical silicon nanometer line and manufacturing method of flash memory structure - Google Patents
Flash memory structure achieved on vertical silicon nanometer line and manufacturing method of flash memory structure Download PDFInfo
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Abstract
The invention relates to a flash memory structure achieved on a vertical silicon nanometer line and a manufacturing method of the flash memory structure. The manufacturing method comprises steps as follows: depositing a bottom oxide layer and a silicon layer on the upper surface of a silicon substrate in sequence; etching the silicon layer to form a vertical silicon nanometer line structure; preparing a first buried oxide layer which is then covered on the bottom of the vertical silicon nanometer line; injecting main foreign ions to an exposed upper portion structure to form at least two main foreign matter silicon layers; preparing ONO layers on the upper surface of the first buried oxide layer and the surface of the exposed upper portion vertical structure; preparing a polycrystalline silicon layer on the surface of each ONO layer; etching the polycrystalline silicon layers and retaining areas, located inside the main foreign matter silicon layers, of the polycrystalline silicon layers; etching the ONO layers; preparing oxide layers to cover all main foreign matter silicon layers; and preparing a metal structure on the surface of the exposed upper portion vertical structure. The flash memory structure achieved on the vertical silicon nanometer line and the manufacturing method of the flash memory structure enable a silicon oxide nitride oxide silicon (SONOS) structure to be achieved on the vertical silicon nanometer line, and can exceed the memory limit of an existing flash memory.
Description
Technical field
The present invention relates to the silicon semiconductor device manufacturing process, relate in particular to the flash memory structure and the manufacture method thereof that realize on vertical silicon nanowire.
Background technology
The memory cell of existing flash memory generally uses polysilicon as the floating boom transistor (floating gate transistor) of information storage medium, and its information storage principle is to inject or the FN tunneling effect makes electronics as the carrier storage of the information polysilicon at floating boom by hot electron.When electronic injection and when being stored in floating boom, representative information " 0 "; When electronics is wiped free of from floating boom, representative information " 1 ".The transistorized flash memory technology of floating boom exists inherent shortcoming, as NOR(and non-) chip below 45 nm technology node, NAND(or non-) chip is below 32 nm technology node, because excessively thin dielectric layer can cause electric leakage, cause the mutual interference of data phase, and the problem of chip failure occurs.Progress along with technology, the material of floating boom changes to some extent, SONOS is that a kind of use silicon nitride (Si3N4) is as the flash memory structure of information storage medium, its various aspects of performance is more more superior as the flash memory structure of floating boom than polysilicon, such as it has lower program voltage, higher erasable durability degree etc.SONOS utilizes the mode of the seizure of silicon nitride dielectric layer interface trap and release electric charge to come access data, and it is very suitable on the high-capacity flash memory chip, has the advantages such as in chip, wafer (cell) is less, operating voltage is lower.
NOR and NAND are two kinds of different Nonvolatile memory unit array structures.General NOR flash memory and the general NOR flash memory that is used for large data storage that is used for code storage has its advantage separately.The challenge that the development of present flash memory technology runs into is the restriction of memory capacity--continues to increase memory capacity and become more and more difficult on prior art and structure.The limit that how to adopt new technology and structure to break through memory capacity is a huge challenge to industry.
Traditional structure is to make single storage organization on silicon substrate, is the structure on plane, and if increase the number of plies, need to constantly repeat this structure and be superimposed upon on original structure, occur so have the ever-increasing problem of process costs.In order to increase the memory capacity of nand flash memory, a kind of is to increase storehouse, and another kind is as far as possible device to be done littlely on technique, increases the density of storage organization.Increasing the storehouse number of plies can make the volume of flash memory increase, technologic device dimensions shrink is so uneasy, so industry can make the density of memory cell increase as much as possible and not need to reach by more difficult technique (size is dwindled) in the new nand flash memory structure of searching now.If the better nand flash memory structure that the energy develop makes new advances can be reduced the shared bulk size of memory cell, add with the increase lamination and come capacity increasing, the memory capacity of flash memory is promoted greatly.
Silicon nano line transistor is a kind of new device structure.The silicon nanowire structure transistor of Preliminary report has excellent Sub-Threshold Characteristic, carrier mobility and closes step response both at home and abroad at present, can be good at suppressing short-channel effect.Than traditional silicon planar device, the nanowire MOS FET of One Dimensional Quasi ballistic transport shows very strong minification advantage, if the problem in its more existing manufacturing technologies is progressively solved, nano-wire transistor will show great potentiality to the set objective that realizes the semiconductor route map.
The technology of preparing of silicon nanowires by its conducting channel be parallel or perpendicular to substrate be divided into the plane with vertical two kinds.A main advantage of vertical-type is that its channel length is not to define by photoetching, but uses can define in the technology that the nanoscale yardstick is well controlled thickness as growth technology or layer deposition techniques (layer deposition).
Chinese patent (application number: CN102086024A) disclose a kind of preparation method of silicon nanowires, comprised the steps: deposition the first silicon dioxide layer on single crystalline silicon substrate; The width of lithographic definition silicon nanowires, etching the first silicon dioxide layer, remaining the first silicon dioxide layer of etching are that the mask etching single crystalline silicon substrate forms the silicon nanowires bar; Deposit the second silicon dioxide layer and silicon nitride layer; The etch silicon nitride layer is the side wall that the remaining silicon nitride layer of etching forms the silicon nanowires bar; Etching the second silicon dioxide layer is until the bottom-exposed of silicon nanowires bar; Remove the silicon nitride side wall of silicon nanowires bar; The silicon of etching silicon nano line bar bottom-exposed makes the bottom of silicon nanowires bar be formed unsettled silicon nanowires by hollow out; Remove remaining first, second silicon dioxide layer of silicon nanowires surrounding.The preparation method of silicon nanowires of the present invention can be on single crystalline silicon substrate top-down preparation silicon nanowires.
If the flash memory of technical advantageous SONOS structure is realized on novel silicon nanowire structure, just both advantages can be combined, obtain having the silicon nanowires SONOS flash memory structure of advantageous characteristic, break through the limited technical bottleneck of memory capacity of above-mentioned floating boom transistor and existing large capacity nand flash memory, greatly surmount the memory limit of existing flash memory.
Summary of the invention
In view of the above problems, the invention provides a kind of flash memory structure of realizing and manufacture method thereof on vertical silicon nanowire.
The technical scheme that technical solution problem of the present invention adopts is:
A kind of method that realizes flash memory structure wherein, comprises the steps:
Upper surface at a silicon substrate deposits bottom oxide layer and silicon layer successively;
Part is removed described silicon layer, forms at least one vertical silicon nanowire structure in the upper surface of described bottom oxide layer;
Prepare the first buried oxide layer and cover described floor structure, and part described top vertical structure is embedded among described the first buried oxide layer;
The described top vertical structure that exposes is carried out main impure ion injection technology, form two-layer at least main impurity silicon layer in the described top vertical structure that exposes;
The preparation oxide-nitride-oxide layer covers the surface of the described top vertical structure of the upper surface of described the first buried oxide layer and exposure;
The preparation polysilicon layer, the surface of the described oxide-nitride-oxide layer of covering;
Part is removed described polysilicon layer and described oxide-nitride-oxide layer, form polysilicon gate on the two side of described main impurity silicon layer, and remaining described oxide-nitride-oxide layer covers the surface of described main impurity silicon layer and the surface of the described top vertical structure between described main impurity silicon layer;
Prepare the second buried oxide layer, cover the upper surface of described the first buried oxide layer, and this second buried oxide layer is also buried described main impurity silicon layer;
Remaining described top vertical structure is carried out the top metal metallization processes.
The described method that realizes flash memory structure, wherein, the material of described silicon substrate is identical with the material type of described main impurity silicon layer, and the material of described silicon layer is different from the material type of described silicon substrate.
The described method that realizes flash memory structure, wherein, each described vertical silicon nanowire structure includes two top vertical structures and a floor structure, described two top vertical structures connect by described floor structure, and are arranged in the logical metal connecting structure connection of two adjacent described top vertical structures of different described vertical silicon nanowire structures.
The described method that realizes flash memory structure wherein, adopts high-density plasma chemical vapor deposition technique to prepare described bottom oxide layer, described the first buried oxide layer and described the second buried oxide layer.
The described method that realizes flash memory structure wherein, adopts low-pressure chemical vapor phase deposition technique to prepare described oxide-nitride-oxide layer.
The described method that realizes flash memory structure wherein, adopts ion implantation technology and photoetching process to form described vertical silicon nanowire structure successively.
A kind of flash memory structure, wherein, described flash memory structure comprises silicon substrate, buried oxide layer, a plurality of metal connecting structure and at least two vertical silicon nanowire structures;
Described buried oxide layer covers the upper surface of described silicon substrate, described metal connecting structure is positioned at the upper surface of described buried oxide layer, and described floor structure is arranged at the inside of described buried oxide layer, and the described top vertical structure that is positioned at described floor structure upper surface partly is exposed to described buried oxide layer;
Be positioned on the described top vertical structure of described buried oxide layer inside and be provided with the multilayered memory cellular construction.
Described flash memory structure, wherein, the equal structure of each described vertical silicon nanowire comprises two top vertical structures and a floor structure, described two top vertical structures connect by described floor structure, and two adjacent described top vertical structures that are arranged in different described vertical silicon nanowire structures connect by described metal connecting structure.
Described flash memory structure, wherein, each described memory cell structure comprises a plurality of main impurity silicon areas, oxide-nitride-oxide layer and polysilicon layer;
Wherein, be provided with described polysilicon layer on the sidewall of each described main impurity range, and also be provided with described oxide-nitride-oxide layer between described polysilicon layer and described main impurity silicon area, this oxide-nitride-oxide layer covers the surface of the described top vertical structure between described main impurity silicon area and adjacent described main impurity silicon area.
Described flash memory structure, wherein, the material of described buried oxide layer is silicon dioxide.
Technique scheme has following advantage or beneficial effect:
The present invention is by being made in existing SONOS flash memory structure on vertical silicon nanowire, the technical advantage of SONOS and silicon nanowires is combined, thereby obtain having the silicon nanowires SONOS flash memory structure of superiority, solve present floating boom transistor and the limited technical bottleneck of existing large capacity nand flash memory memory capacity, greatly surmounted the limit of existing flash memory storage capacity.
Description of drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only is used for explanation and sets forth, and does not consist of limitation of the scope of the invention.
Fig. 1 carries out the structural representation that phosphonium ion injects on silicon layer in the embodiment of the present invention;
Fig. 2 is the structural representation of vertical silicon nanowire in the embodiment of the present invention;
Fig. 3 is the structural representation of main impurity silicon layer in the embodiment of the present invention;
Fig. 4 is the structural representation of deposit ONO layer and polysilicon layer in the embodiment of the present invention;
Fig. 5 is the structural representation of memory cell in the embodiment of the present invention;
Fig. 6 is the schematic diagram of flash memory structure in the embodiment of the present invention;
Fig. 7 is the electrical block diagram of prior art NAND type flash memory;
Fig. 8 is the schematic equivalent circuit of SONOS in the embodiment of the present invention.
Embodiment
The present invention is a kind of flash memory structure of realizing on vertical silicon nanowire and manufacture method thereof, and the embodiment of the inventive method is as follows:
The present invention realizes flash memory structure on vertical silicon nanowire, concrete grammar is:
Carry out on the semiconductor device substrate as Fig. 1 to step shown in Figure 6, wherein this Semiconductor substrate is P type substrate 1, in its surface coverage, bottom oxide layer 2 is arranged, surface coverage in bottom oxide layer 2 has silicon layer, this silicon layer is the silicon layer opposite with substrate type, because the substrate 1 of selecting is P type substrate, therefore, silicon layer herein adopts N-type silicon layer 3 in the present embodiment.
As shown in Figure 1, carry out the injection of phosphonium ion on N-type silicon layer 3, as shown in Figure 2, and by photoetching process, N-type silicon layer 3 is carried out photoetching, thereby formation vertical silicon nanowire, wherein, vertical silicon nanowire comprises floor structure 32 and top vertical structure 31, from left to right it is defined as respectively the first top vertical structure 311, the second top vertical structure 312, the 3rd top vertical structure 313 and the 4th top vertical structure 314; Floor structure 32 is two horizontal nano wires, connects respectively the bottom of the first top vertical structure 311 and the second top vertical structure 312 and the bottom of the 3rd top vertical structure 313 and the 4th top vertical structure 314; Wherein the second top vertical structure 312 is not connected with the 3rd top vertical structure 313 bottoms.Bottom buried oxide layer 1 is carried out high-density plasma (HDP) oxide deposition, form the first buried oxide layer 21 on bottom oxidization layer thing 2, thereby the thickness of bottom buried oxide layer 1 is originally further increased, and the first buried oxide layer 21 is buried the floor structure 32 of the first top vertical structure 311 and the second top vertical structure 312, and part is buried the below part of the first top vertical structure 311 and the below part of the second top vertical structure 312; The first buried oxide layer 21 is also buried the floor structure 32 of the 3rd top vertical structure 313 and the 4th top vertical structure 314 simultaneously, and part is buried the below part of the 3rd top vertical structure 313 and the below part of the 4th top vertical structure 314.
After above-mentioned steps, the injection that P type master impurity is carried out in the pre-position on the vertical silicon nanowire that forms forms main impurity silicon layer 4, and wherein, preposition is to form the position of memory cell in subsequent technique.
As shown in Figure 3, in top vertical structure outside top vertical structure 31 is exposed to the first buried oxide layer 21, choose the precalculated position and carry out the injection of main impurity, zone after carrying out main Impurity injection forms main impurity silicon 4, wherein, the main impurity silicon layer 4 that forms is at least two-layer, and separated by a distance between adjacent main impurity silicon layer 4.In an embodiment of the present invention, memory cell is two-layer, so precalculated position in this step is also two-layer, corresponding formed main impurity silicon layer 4 is also two-layer, wherein first floor master impurity silicon layer 41 and the first buried oxide layer surface 21 join, second layer master impurity silicon layer 42 is positioned at the top of first floor master impurity silicon layer 41, the distance of the F of being separated by between first floor master impurity silicon layer 41 and second layer master impurity silicon layer 42, and F is the critical size of nanometer technology.
As shown in Figure 4, the deposit of nitration case-oxide layer-nitration case dielectric layer (ONO layer) 5 is carried out on top vertical structure 31 surfaces that expose and the first buried oxide layer 21 surfaces of exposing, to form the three-layer composite structure dielectric layer 5 of nitration case-oxide layer-nitration case, wherein the deposit of ONO layer 5 can be adopted low-pressure chemical vapor phase deposition technique (LPCVD).
Deposit one deck polysilicon layer (poly) 6 again on the surface of ONO layer 5, the surface of the ONO layer 5 that forms before this polysilicon layer is covered in.
As shown in Figure 5 and Figure 6, polysilicon layer 6 is carried out etching, keep the second polysilicon layer 62 of its first polysilicon layer 61 that is positioned at first floor master impurity silicon layer 41 and second layer master impurity silicon layer.ONO layer 5 is carried out etching, will be positioned at the ONO layer 5 under first floor master impurity silicon layer 41 bottoms and the ONO layer 5 that is positioned on second layer master impurity silicon layer 42 tops etches away.After above-mentioned steps, continue to adopt the technique of high-density plasma chemical vapor deposition to carry out deposit to the first buried oxide layer 21, form the second buried oxide layer 22, thereby make the second buried oxide layer bury all main impurity silicon layers.At this moment, form a first floor memory cell structure 81 that comprises main impurity silicon area, ONO layer 5, the first polysilicon layer 61 and the second buried oxide layer 22 between first floor master impurity silicon layer 41 bottoms and top; Same, form a second layer memory cell structure 82 that comprises main impurity silicon area, ONO layer 5, the second polysilicon layer 62 and the second buried oxide layer 22 between second layer master impurity silicon layer 42 bottoms and top.
after above-mentioned steps is completed, expose portion surface preparation metal connecting structure 7 in the top of vertical silicon nanowire vertical structure 31, make the top metal of total, wherein, metal connecting structure 7 is divided into Three regions, cover respectively the vertical silicon nanowire end of diverse location, as shown in Figure 6, exposed region surface coverage in the first top vertical structure 311 has the first metal connecting structure 71, the exposed region surface coverage of the exposed region of the second top vertical structure 312 and the 3rd top vertical structure 313 has the second metal connecting structure 72, the exposed region surface coverage of the 4th top vertical structure 314 has the 3rd metal connecting structure 73, the first metal connecting structure 71 wherein, be not connected between the second metal connecting structure 72 and the 3rd metal connecting structure 73.
It needs to be noted, memory cell in an embodiment of the present invention is two-layer, in actual production process, the number of plies of memory cell can be increased accordingly according to actual needs, and corresponding step also changes accordingly with it.
The invention also discloses a kind of flash memory structure, comprise silicon substrate, buried oxide layer, metal connecting structure, at least two vertical silicon nanowire structure independently mutually.
The equal structure of each vertical silicon nanowire comprises two top vertical structures and a floor structure, two top vertical structures connect by floor structure, and two adjacent upper vertical structures that are arranged in different vertical silicon nanowire structures connect by metal connecting structure.
Wherein, buried oxide layer covers silicon substrate, and floor structure is positioned at buried oxide layer, and the top vertical structure partly is positioned at buried oxide layer, and part is positioned at metal connecting structure; There are a plurality of memory cell structures in the top vertical structure that is arranged in buried oxide layer, and memory cell structure comprises a plurality of main impurity silicon areas, oxide-nitride-oxide layer, polysilicon layer.
Set forth below in conjunction with accompanying drawing and instantiation.
The substrate type that adopts in the present embodiment is P type substrate, and corresponding vertical silicon nanowire structure adopts N-type silicon, and main impurity type silicon is P type silicon, and vertical silicon nanowire structure in the present embodiment is two, and memory cell structure is also two-layer.
As shown in Figure 6, this structure comprises P type substrate 1, buried oxide layer 2, metal connecting structure 7, two independently vertical silicon nanowire structure 3 and multilayered memory cellular construction 81(82 mutually), wherein, buried oxide layer 2 is positioned on P type substrate 1, metal connecting structure 7 is positioned on buried oxide layer 2, multilayered memory cellular construction 81(82) be positioned at buried oxide layer 2 inside, the part at the top of vertical nano-wire structure is arranged in metal connecting structure 7, and vertical nano-wire structure remainder is arranged in buried oxide layer 2.
The vertical silicon nanowire structure comprises top vertical structure 31 and floor structure 32, and wherein, the top vertical structure comprises the first top vertical structure 311, the second top vertical structure 312, the 3rd top vertical structure 313 and the 4th top vertical structure 314; Floor structure comprises the first floor structure 321 and the second floor structure 322; The first top vertical structure 311 is connected by the first floor structure 321 with the second top vertical structure 312, and the 3rd top vertical structure 313 connects by the second floor structure 322 with the 4th top vertical structure 314.
Metal connecting structure 7 comprises the first metal connecting structure 71, the second metal connecting structure 72 and the 3rd metal connecting structure 73, wherein, the first metal connecting structure 71, the second metal connecting structure 72 and the 3rd metal connecting structure 73 are not connected each other, the first metal connecting structure 71 covers the top of the first top vertical structure 311, the second metal connecting structure 72 covers the top of the second top vertical structure 312 and the top of the 3rd top vertical structure 313, and the 3rd metal connecting structure 73 covers the top of the 4th top vertical structure 314.
As shown in Figure 6, memory cell structure 81(82) comprise main impurity silicon area 4, ONO layer 5 and poly layer 6, wherein, main impurity silicon area 4 lays respectively in the first top vertical structure 311, the second top vertical structure 312, the 3rd top vertical structure 313 and the 4th top vertical structure 314, and be in the same level position, the both side surface of each main impurity silicon area 4 is coated with ONO layer 5, and the surface coverage of each ONO layer 5 has poly layer 6.
Flash memory with said structure can have larger memory capacity than traditional NAND type flash memory.
Fig. 7 is traditional NAND type flash memory structure circuit diagram, Fig. 8 is the equivalent circuit diagram of the SONOS of vertical-channel, as can be known from Fig. 7, the overall size of traditional NAND type flash memory structure is 2F * 8=16F, as shown in Figure 8, the overall size of the SONOS flash memory of vertical-channel is 3F * 4=12F, wherein, F represents the critical size of nanometer technology, as seen, adopt the SONOS flash memory of the vertical-channel that above-mentioned technological process makes, can form than the larger unit bit density of traditional NAND type flash memory structure, thereby realize the breakthrough of flash memory storage capacity.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents, all should think still to belong in the intent of the present invention and scope in claims scope.
Claims (10)
1. a method that realizes flash memory structure, is characterized in that, comprises the steps:
Upper surface at a silicon substrate deposits bottom oxide layer and silicon layer successively;
Part is removed described silicon layer, forms at least one vertical silicon nanowire structure in the upper surface of described bottom oxide layer;
Prepare the first buried oxide layer and cover described floor structure, and part described top vertical structure is embedded among described the first buried oxide layer;
The described top vertical structure that exposes is carried out main impure ion injection technology, form two-layer at least main impurity silicon layer in the described top vertical structure that exposes;
The preparation oxide-nitride-oxide layer covers the surface of the described top vertical structure of the upper surface of described the first buried oxide layer and exposure;
The preparation polysilicon layer, the surface of the described oxide-nitride-oxide layer of covering;
Part is removed described polysilicon layer and described oxide-nitride-oxide layer, form polysilicon gate on the two side of described main impurity silicon layer, and remaining described oxide-nitride-oxide layer covers the surface of described main impurity silicon layer and the surface of the described top vertical structure between described main impurity silicon layer;
Prepare the second buried oxide layer, cover the upper surface of described the first buried oxide layer, and this second buried oxide layer is also buried described main impurity silicon layer;
Remaining described top vertical structure is carried out the top metal metallization processes.
2. the method that realizes flash memory structure as claimed in claim 1, is characterized in that, the material of described silicon substrate is identical with the material type of described main impurity silicon layer, and the material of described silicon layer is different from the material type of described silicon substrate.
3. the method that realizes flash memory structure as claimed in claim 1, it is characterized in that, each described vertical silicon nanowire structure includes two top vertical structures and a floor structure, described two top vertical structures connect by described floor structure, and are arranged in the logical metal connecting structure connection of two adjacent described top vertical structures of different described vertical silicon nanowire structures.
4. the method that realizes flash memory structure as claimed in claim 1, is characterized in that, adopts high-density plasma chemical vapor deposition technique to prepare described bottom oxide layer, described the first buried oxide layer and described the second buried oxide layer.
5. the method that realizes flash memory structure as claimed in claim 1, is characterized in that, adopts low-pressure chemical vapor phase deposition technique to prepare described oxide-nitride-oxide layer.
6. the method that realizes flash memory structure as claimed in claim 1, is characterized in that, adopts successively ion implantation technology and photoetching process to form described vertical silicon nanowire structure.
7. a flash memory structure, is characterized in that, described flash memory structure comprises silicon substrate, buried oxide layer, a plurality of metal connecting structure and at least two vertical silicon nanowire structures;
Described buried oxide layer covers the upper surface of described silicon substrate, described metal connecting structure is positioned at the upper surface of described buried oxide layer, and described floor structure is arranged at the inside of described buried oxide layer, and the described top vertical structure that is positioned at described floor structure upper surface partly is exposed to described buried oxide layer;
Be positioned on the described top vertical structure of described buried oxide layer inside and be provided with the multilayered memory cellular construction.
8. flash memory structure as claimed in claim 7, it is characterized in that, the equal structure of each described vertical silicon nanowire comprises two top vertical structures and a floor structure, described two top vertical structures connect by described floor structure, and two adjacent described top vertical structures that are arranged in different described vertical silicon nanowire structures connect by described metal connecting structure.
9. flash memory structure as claimed in claim 7, is characterized in that, each described memory cell structure comprises a plurality of main impurity silicon areas, oxide-nitride-oxide layer and polysilicon layer;
Wherein, be provided with described polysilicon layer on the sidewall of each described main impurity range, and also be provided with described oxide-nitride-oxide layer between described polysilicon layer and described main impurity silicon area, this oxide-nitride-oxide layer covers the surface of the described top vertical structure between described main impurity silicon area and adjacent described main impurity silicon area.
10. flash memory structure as claimed in claim 7, is characterized in that, the material of described buried oxide layer is silicon dioxide.
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| CN107230679A (en) * | 2016-03-23 | 2017-10-03 | 格罗方德半导体公司 | High density memory cells structure |
| CN108428634A (en) * | 2018-02-09 | 2018-08-21 | 中国科学院微电子研究所 | Vertical nanowire transistor and manufacturing method thereof |
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