CN102931182A - Packaging device of compact single-phase integrated drive circuit and single-phase integrated drive circuit - Google Patents

Packaging device of compact single-phase integrated drive circuit and single-phase integrated drive circuit Download PDF

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Publication number
CN102931182A
CN102931182A CN2012104523165A CN201210452316A CN102931182A CN 102931182 A CN102931182 A CN 102931182A CN 2012104523165 A CN2012104523165 A CN 2012104523165A CN 201210452316 A CN201210452316 A CN 201210452316A CN 102931182 A CN102931182 A CN 102931182A
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pin
upper arm
bias voltage
gate driver
gate
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CN102931182B (en
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吴美飞
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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Abstract

The invention provides a packaging device of a compact single-phase integrated drive circuit. The packaging device comprises wire-leading frame, a plurality of first chip paddles formed on the wire-leading frame, first grid electrode drive devices, second grid electrode drive devices, first upper arm transistors, first lower arm transistors, second upper arm transistors, second lower arm transistors, signal pins, and power pins, wherein each first grid electrode drive device, each second grid electrode drive device, each first upper arm transistor, each first lower arm transistor, each second upper arm transistor, and each second lower arm transistor are arranged on each first chip paddle, and each signal pin and each power pin are led from each first chip paddle and arranged oppositely on tow sides of the wire-leading frame. The invention further provides the single-phase integrated drive circuit, aims at solving the problems that drive circuit devices formed by discrete components are difficult in installation and poor in reliability due to large amount, and is particularly suitable for solving the problems that center distances of the pins are reduced due to the fact that packaging size is limited in integrated drive circuits, and thereof the pins are damaged with one another due to the fact that the center distances are not enough.

Description

Packaging device of compact single-phase integrated drive circuit and single-phase integrated drive circuit
Technical Field
The invention belongs to the technical field of integrated semiconductors, and particularly relates to a packaging device of a compact single-phase integrated drive circuit and the single-phase integrated drive circuit.
Background
Compared with an alternating current motor, the brushless direct current motor can effectively improve the working efficiency, can flexibly set the starting and closing parameters of the motor through the adjustment of a control program, meets the use requirements of users more, and becomes a first choice of household and industrial control motors increasingly.
Three-phase brushless direct current motors and single-phase brushless direct current motors in the brushless direct current motors. The current integrated drive circuit of the three-phase brushless direct current motor has a large volume, is difficult to be arranged on an annular PCB (printed circuit board) inside a plurality of motors (such as motors with the outer diameter of 80mm and the shaft diameter of 34mm or less), and the high-voltage pins and the low-voltage pins of the integrated drive circuit are close to each other, so that the problem that the pins are damaged by each other due to insufficient center distance is easily caused. The single-phase brushless direct current motor is one of brushless direct current motors, and the single-phase brushless direct current motor is a motor with extremely high cost performance due to the fact that a winding method is simple, requirements on magnetic materials of the motor are not high, and the effect of the three-phase brushless direct current motor can be achieved on the basis of a lot of power applications. The single-phase brushless direct current motor can be applied to various energy-saving fans and water pumps.
The single-phase brushless direct current motor consists of a motor and a driving circuit, wherein the driving circuit consists of a power driver and a controller, and the driving circuit processes a control signal sent by a program through the controller so as to drive the power driver to be switched on or switched off, and further control the starting or stopping of the motor and the operation of various modes. At present, the driving method of a general single-phase brushless dc motor includes the following several methods:
the first method is as follows: as shown in fig. 1, a high voltage gate driver S1 in the form of Totem Pole (Totem Pole) formed by discrete devices such as bipolar junction transistors (such as NPN and PNP), diodes, resistors and capacitors is used to drive a power driver G1 formed by power devices (such as MOSFET tubes), but the high voltage gate driver of this circuit structure requires dozens of discrete devices, and has the disadvantages of complicated design, high production difficulty, poor reliability, high repair rate, and difficult integration into the motor due to its large occupied volume.
The second method comprises the following steps: as shown in fig. 2, a high voltage gate driver (HVIC) S1 'manufactured by an integrated process based on fig. 1 is modified to drive a power driver G1' having a single-phase upper leg and a single-phase lower leg composed of four power devices (e.g., MOSFET transistors) by using two gate drivers S2 instead of the high voltage gate driver S1 in the form of a totem pole built up of discrete devices. Although the high voltage gate driver S1 'may also be integrated with under-voltage protection, the high voltage gate driver S1' has a relatively high integration level and a reliability that is greatly enhanced compared to the high voltage gate driver S1 with totem-pole type formed by bjts. However, the high voltage gate driver S1 'and the power driver G1' are also discrete devices, and there are also many problems, for example, it is difficult to integrate the high voltage gate driver and the power driver on a single chip by an integration process in the prior art, and the existing lead frame for packaging the device does not have multiple base islands, and is generally provided with a single chip; for example, the control circuit has the disadvantages of complex design, large volume, poor insulation, large parasitic capacitance and inductance and the like, and is difficult to be applied to occasions requiring compact installation and uniform heat dissipation of end covers, and the system reliability is also poor due to the difficulty in ensuring the parameter consistency of four power devices. Further, since the line between the high voltage gate driver S1 'and the power driver G1' is long and the line inductance and the line resistance are large, the gate filter capacitance Cgate for preventing the miller effect needs to be increased.
Fig. 3 illustrates two power devices corresponding to one of the gate drivers S2 in fig. 2. It is common practice to use two identical gate drivers S2, each of which S2 adjusts the driving resistance R at the gate of the power device to adjust the rising and falling edge times of the output signal of the power device. Therefore, the existence of four driving resistors R will occupy more space of the integrated circuit, and if the driving resistors are set too small, the output signal will have larger ringing, and the EMI (electromagnetic interference) will also be larger; if the driving resistor is set to be too large, the switching time of the power device is slow, and the single-phase upper bridge arm and the single-phase lower bridge arm can be communicated to cause unrecoverable damage, so that the margin for adjustment of a customer is small.
Therefore, the control circuit and the power driving circuit in the traditional single-phase brushless direct current motor driving circuit are still discrete devices, the positions on the PCB are scattered, the single-phase brushless direct current motor driving circuit is difficult to be uniformly attached to the radiating fins, and even if the radiating fins can be attached, the radiating fins have larger area and higher cost, and cannot have higher insulativity while ensuring small volume, so that the single-phase brushless direct current motor driving circuit is difficult to be reliably used for a long time.
Meanwhile, when the motor is applied to some motors with severe vibration, the radiating fins and the modules forming the driving circuit are easy to separate, which may cause the temperature of the power module to rise sharply, or in other motor applications, when the input and output power of the motor needs to be dynamically adjusted according to the temperature of the power module, an output pin for sensing the temperature needs to be arranged in the power module, and an analog voltage corresponding to the temperature is output to the control circuit to control the PWM duty ratio in real time. In addition, in other motor applications, it is necessary to actively output an alarm signal to the control circuit according to a fault, or actively add an overcurrent protection signal to the control circuit according to the magnitude of current. The addition of these discrete devices also undoubtedly increases the difficulty of integration, with a consequent increase in cost.
Along with being used for single-phase brushless DC motor's discrete component more and more, the volume is constantly increased, and the pin number increases, and pin center distance is reducing, how can guarantee to drive single-phase motor's integrated module can be applicable to that power module size is little, the installation is small, in order to guarantee simultaneously to have sufficient center distance between the high-low pressure pin and between the high-voltage pin, and the occasion of the requirement compact installation that goes to guarantee withstand voltage is a problem that awaits the solution urgently.
Disclosure of Invention
The invention aims to provide a packaging device of a compact single-phase integrated drive circuit and the single-phase integrated drive circuit, which are used for solving the problems of difficult installation and poor reliability caused by the large number of devices of the drive circuit formed by connecting discrete components, in particular the problem that the pins are damaged mutually due to insufficient center distance caused by the reduction of the center distance of the pins due to the limited packaging volume in the integrated drive circuit.
In order to solve the above problems, the present invention provides a packaging device for a compact single-phase integrated driving circuit, comprising:
a lead frame;
forming a plurality of first chip base islands on the lead frame;
the signal pins and the power pins are respectively formed on two opposite sides of the lead frame and are led out through the bending of the plurality of first chip base islands;
a first gate driver, a second gate driver, a first upper arm transistor, a first lower arm transistor, a second upper arm transistor and a second lower arm transistor respectively mounted on each first chip base island, wherein the first gate driver, the second gate driver, the first upper arm transistor, the first lower arm transistor, the second upper arm transistor and the second lower arm transistor are respectively electrically connected; and
the packaging structure comprises a packaging body, a packaging body and a packaging body, wherein the length of the packaging body is 17.8-25.8 mm, and the width of the packaging body is 11-13 mm; wherein,
the signal pins corresponding to the first gate driver comprise a first upper arm bias voltage pin, a first gate driving bias voltage pin, a first upper arm input signal pin, a first lower arm input signal pin and a common-ground voltage pin, and the signal pins corresponding to the second gate driver comprise a second upper arm bias voltage pin, a second gate driving bias voltage pin, a second upper arm input signal pin, a second lower arm input signal pin and the common-ground voltage pin;
the power pin corresponding to the first upper arm transistor comprises an upper arm positive phase voltage pin and a first drive output signal pin, the power pin corresponding to the first lower arm transistor comprises the first drive output signal pin and a first detection signal pin, the power pin corresponding to the second upper arm transistor comprises the upper arm positive phase voltage pin and a second detection signal pin, and the power pin corresponding to the second lower arm transistor comprises the second detection signal pin and a second drive output signal pin;
the center distance between the first gate drive bias voltage pin and the first upper arm bias voltage pin, the center distance between the second gate drive bias voltage pin and the second upper arm bias voltage pin, and the center distance between the first lower arm input signal pin and the second upper arm bias voltage pin are more than twice of the center distance of the low-voltage pins.
Preferably, a center distance between the upper arm positive phase voltage pin and the first driving output signal pin, a center distance between the first driving output signal pin and the first detection signal pin, and a center distance between the second driving output signal pin and the second detection signal pin are more than twice of a center distance of the low voltage pin.
Further, a first functional pin is arranged between the first gate driving bias voltage pin and the first upper arm bias voltage pin, and a second functional pin is arranged between the second gate driving bias voltage pin and the second upper arm bias voltage pin.
Furthermore, a temperature sensor or a fault signal generator or an overcurrent signal comparator is loaded on the first functional pin and the second functional pin.
Preferably, the packaging device further comprises a first bootstrap diode pad formed on the first gate driver and a second bootstrap diode pad formed on the second gate driver; forming a first bootstrap diode chip base island and a second bootstrap diode chip base island on the lead frame; the first bootstrap diode chip is installed on the first bootstrap diode chip base island and electrically connected with the first functional pin and the first bootstrap diode pressure welding point; and the second bootstrap diode chip is installed on the second bootstrap diode chip base island and is electrically connected with the second functional pin and the second bootstrap diode pressure welding point.
Preferably, the packaging device further comprises a plurality of second chip base islands formed on the lead frame; and the switch units are respectively arranged on each second chip base island, and each switch unit comprises an upper arm switch unit and a lower arm switch unit.
According to another aspect of the present invention, there is provided a single-phase integrated driving circuit, comprising:
a high voltage gate driver, a power driver, a signal pin and a power pin integrated on the same package, wherein the high voltage gate driver is composed of a first gate driver and a second gate driver, and the power driver is composed of a first upper arm transistor, a first lower arm transistor, a second upper arm transistor and a second lower arm transistor;
the high-voltage gate driver receives a driving signal generated by an input signal through the signal pin, and the power driver responds to the driving signal and outputs a driving output signal for controlling the work of a load through the power pin; wherein,
the signal pins corresponding to the first gate driver are a first upper arm bias voltage pin, a first gate driving bias voltage pin, a first upper arm input signal pin, a first lower arm input signal pin and a common-ground voltage pin, and the signal pins corresponding to the second gate driver are a second gate driving bias voltage pin, a second upper arm input signal pin, a second lower arm input signal pin and the common-ground voltage pin;
the power pins corresponding to the first upper arm transistor are an upper arm positive phase voltage pin and a first drive output signal pin, the power pins corresponding to the first lower arm transistor are the first drive output signal pin and a first detection signal pin, the power pins corresponding to the second upper arm transistor are the upper arm positive phase voltage pin and a second detection signal pin, and the power pins corresponding to the second lower arm transistor are the second detection signal pin and a second drive output signal pin;
the center distance between the first gate driving bias voltage pin and the first upper arm bias voltage pin, the center distance between the second gate driving bias voltage pin and the second upper arm bias voltage pin, and the center distance between the first lower arm input signal pin and the second upper arm bias voltage pin are twice of the center distance of the low-voltage pins.
Preferably, a center distance between the upper arm positive phase voltage pin and the first driving output signal pin, a center distance between the first driving output signal pin and the first detection signal pin, and a center distance between the second driving output signal pin and the second detection signal pin are more than twice of a center distance of the low voltage pin.
Further, a first functional pin is arranged between the first gate driving bias voltage pin and the first upper arm bias voltage pin; and a second functional pin is arranged between the second gate driving bias voltage pin and the second upper arm bias voltage pin.
Furthermore, a temperature sensor or a fault signal generator or an overcurrent signal comparator is loaded on the first functional pin and the second functional pin.
Preferably, the single-phase integrated driving circuit further includes that the first gate driver has a first bootstrap diode bonding pad, the first bootstrap diode bonding pad is electrically connected to a first functional pin, and the first functional pin and the first upper arm bias voltage pin are respectively electrically connected to an anode and a cathode of the first bootstrap diode;
the second gate driver is provided with a second bootstrap diode bonding pad, the second bootstrap diode bonding pad is electrically connected with a second functional pin, and the second functional pin and a second upper arm bias voltage pin are respectively electrically connected with the anode and the cathode of the second bootstrap diode.
Further, a plurality of switching units for power driving are integrated, each of the switching units including an upper arm switching unit and a lower arm switching unit.
According to the technical scheme, the grid driver and the power driver are integrated on the same packaging body, the grid driver generates the driving signal according to the input signal received by the signal pin, and the driving power driver responds to the driving signal and generates the driving output signal for driving the load to work at the power pin. Compared with the prior art, the invention realizes the integration of the gate driver and the power driver through the packaging process, and solves the problem that two gate drivers and four power drivers cannot be placed in the traditional lead frame because the traditional lead frame only has a single base island. Therefore, the discrete components originally forming the gate driver and the power driver are not dispersed but effectively integrated, so that the size is reduced, the design of controlling the power driver by the gate driver is simple, and the system reliability is improved.
Because the gate driver and the power driver are integrated on the same package, the problems of difficult installation and poor reliability caused by the large number of devices due to the connection of discrete components can be reduced through the circuit layout in the package, and the overall cost is reduced.
In addition, because the gate driver and the power driver are integrated on the same packaging body, the problem that the pins are damaged mutually due to insufficient center distance in an integrated driving circuit because the center distance of the pins is reduced due to limited packaging volume in the integrated driving circuit can be solved by adjusting the circuit layout inside the packaging body and the pin arrangement outside the packaging body.
In addition, because the gate driver and the power driver are integrated on the same package, the gate driver and the power driver can be conveniently integrated in the same package, the mutual wiring between the gate driver and the power driver is laid out differently, so that, in the case where the total number of signal pins and power pins is unchanged, the signal pin can be reasonably utilized to receive the input signal according to different application requirements so as to generate the driving output signal at the power pin to drive the load to work, therefore, the drive circuit can be used for not only single-phase electrode drive but also High Intensity Discharge (HID) drive, and a temperature sensor or a fault signal generator or an over-current signal comparator can be loaded at the functional pin arranged on the signal pin according to different application requirements, so as to effectively detect the single-phase integrated drive circuit and reduce the fault occurrence rate and the maintenance problem.
In addition, because the gate driver and the power driver are integrated on the same package, the internal wiring of the integrated circuit is short, and the wiring inductance and wiring resistance are extremely low, so that the gate filter capacitor Cgate originally placed for preventing the miller effect can be omitted. In addition, the gate driving resistor for controlling the power driver to be turned on and off in the prior art is also conveniently integrated into the same package, so that the integrated driving circuit can have smaller switching loss on the basis of keeping smaller EMI.
Drawings
Fig. 1 is a schematic diagram of a motor driving circuit in a totem-pole form formed by discrete devices according to a first embodiment of the prior art;
fig. 2 is a schematic diagram of a motor driving circuit formed by a high voltage gate driver and a power driving circuit separately according to a second embodiment of the prior art;
FIG. 3 is a schematic diagram of a motor driving circuit with a gate driving resistance discrete device according to a third embodiment of the prior art; packaging device of compact single-phase integrated drive circuit and single-phase integrated drive circuit
FIG. 4 is a schematic diagram of a packaging apparatus of a compact single-phase integrated driving circuit according to a first embodiment of the present invention;
FIG. 5 is a schematic view of a pressure point disposed on the first gate driver in FIG. 4;
FIG. 6 is a schematic diagram of a pressure point disposed on the second gate driver in FIG. 4;
FIG. 7 is a schematic diagram of a single-phase integrated driving circuit according to a first embodiment of the present invention;
FIG. 8 is a schematic diagram of an application of a single-phase integrated driving circuit according to a first embodiment of the present invention;
FIG. 9 is a schematic diagram of a packaging apparatus of a compact single-phase integrated driving circuit according to a second embodiment of the present invention;
fig. 10 is a schematic view of a pressure point provided on the first gate driver in fig. 13;
FIG. 11 is a schematic view of a pressure point disposed on the second gate driver in FIG. 13;
FIG. 12 is a schematic diagram of a single-phase integrated driving circuit according to a second embodiment of the present invention;
FIG. 13 is a schematic diagram of an application of a single-phase integrated driving circuit according to a second embodiment of the present invention;
FIG. 14 is a schematic diagram of a single-phase integrated driving circuit according to a third embodiment of the present invention;
FIG. 15 is a side view of the outer leads of the package of the compact single phase integrated driver circuit according to an embodiment of the present invention;
fig. 16 is a top view of the outer leads of the package device of the compact single-phase integrated driving circuit according to the embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather construed as limited to the embodiments set forth herein.
[ EXAMPLES one ]
The invention provides a packaging device of a compact single-phase integrated drive circuit, as shown in fig. 4, the packaging device 100 of the compact single-phase integrated drive circuit comprises a lead frame 102, and a plurality of first chip base islands formed on the lead frame. The plurality of first chip base islands include a first gate-driven chip base island 104, a second gate-driven chip base island 106, a first upper arm chip base island 108, a first lower arm chip base island 110, a second upper arm chip base island 112, and a second lower arm chip base island 114. The first gate driving chip base island 104 and the second gate driving chip base island 106 are formed on one inner side of the lead frame, the first upper arm chip base island 108 and the first lower arm chip base island 110, and the second upper arm chip base island 112 and the second lower arm chip base island 114 are formed on the other inner side of the lead frame opposite to each other, the first upper arm chip base island 108 and the first lower arm chip base island 110 are close to the first gate driving chip base island, and the second upper arm chip base island 112 and the second lower arm chip base island 114 are close to the second gate driving chip base island.
The packaging apparatus 100 of the compact single-phase integrated drive circuit further includes a first gate driver 60, a second gate driver 50, a first upper arm transistor 40, a first lower arm transistor 30, a second upper arm transistor 20, and a second lower arm transistor 10. The first upper arm transistor 40, the first lower arm transistor 30, the second upper arm transistor 20, and the second lower arm transistor 10 are all MOSFET transistors. Wherein the first gate driver 60 is formed on the first gate driving chip base island, the second gate driver 50 is formed on the second gate driving chip base island, the first upper arm transistor 40 is formed on the first upper arm chip base island, the first lower arm transistor 30 is formed on the first lower arm chip base island, the second upper arm transistor 20 is formed on the second upper arm chip base island and the second lower arm transistor 10 is formed on the second lower arm chip base island.
The packaging device 100 of the compact single-phase integrated driving circuit also comprises a signal pin. Each signal pin is led out after being bent through the corresponding base island. The signal pin is formed on one side of the lead frame 102. Therefore, the signal pins corresponding to the first gate driver comprise a first upper arm bias voltage pin (1), a first gate driving bias voltage pin (3), a first upper arm input signal pin (4), a first lower arm input signal pin (5) and a common ground voltage pin (11), and the signal pins corresponding to the second gate driver comprise a second upper arm bias voltage pin (6), a second gate driving bias voltage pin (8), a second upper arm input signal pin (9), a second lower arm input signal pin (10) and the common ground voltage pin (11). Then, the signal pins (1), (3), (4), (5), (6), (8), (9), (10) and (11) receive the corresponding first upper arm bias voltage VB1, first gate driving bias voltage VCC1, first upper arm input signal INH1, first lower arm input signal INL1, second upper arm bias voltage VB2, second gate driving bias voltage VCC2, second upper arm input signal INH2, second lower arm input signal INL2 and common ground voltage COM, respectively, see fig. 15 and 16. The first gate drive bias voltage pin (3), the first upper arm input signal pin (4), the first lower arm input signal pin (5), the second gate drive bias voltage pin (8), the second upper arm input signal pin (9), the second lower arm input signal pin (10) and the common ground voltage pin (11) are all low-voltage pins, and the center distance between the low-voltage pins is the low-voltage pin interval.
The packaging device 100 of the compact single-phase integrated drive circuit also comprises a power pin. Each power pin is also led out after being bent through the corresponding base island. The power pin is formed on the other side of the lead frame, and the other side of the lead frame is opposite to one side of the lead frame. Therefore, the power pin corresponding to the first upper arm transistor comprises an upper arm positive phase voltage pin (12) and a first drive output signal pin (13), the power pin corresponding to the first lower arm transistor comprises the first drive output signal pin (13) and a first detection signal pin (14), the power pin corresponding to the second upper arm transistor comprises the upper arm positive phase voltage pin (12) and a second detection signal pin (15), and the power pin corresponding to the second lower arm transistor comprises the second detection signal pin (15) and a second drive output signal pin (16). Then, the power pin (12) receives the upper arm positive phase voltage VP, and the power pins (13), (14), (15), and (16) output the corresponding first drive output signal OUT1, first detection signal N1, second detection signal N2, and second drive output signal OUT2, respectively, see fig. 15 and 16.
Referring to fig. 5 and 6, a first common ground voltage pad 61 and a second common ground voltage pad 51 are respectively disposed on the first gate driver 60 and the second gate driver 50, the first and second common ground voltage pads 61 and 51 are electrically connected to the first and second gate driving chip base islands 104 and 106, the first gate driver chip base island 104 and the second gate driver chip base island 106 integrated on the same lead frame 102 may be electrically connected to a common ground voltage pin (11), and the first gate driver 60 and the second gate driver 50 are connected to form a high voltage gate driver, therefore, the first gate driver 60 and the second gate driver 50 simultaneously receive the common ground voltage COM through the common ground voltage pin (11). Since the two gate drivers constituting the high voltage gate driver are discrete devices in the prior art, in order to drive the two discrete gate drivers respectively, each discrete gate driver must receive a corresponding gate driving bias voltage, an upper arm input signal, a lower arm input signal, an upper arm bias voltage and a common ground voltage, even though each gate driver can share one common ground voltage, each discrete gate driver must provide a common ground voltage pin, and perform circuit layout on the corresponding common ground voltage pin outside each discrete gate driver to commonly receive the same common ground voltage. The invention can omit a common-ground voltage pin, thereby adopting the least pins, realizing the function of the high-voltage gate driver and reducing the size of the integrated circuit as much as possible. In addition, the first gate driver 60 further has a first gate driving bias voltage pad 66 receiving the first gate driving bias voltage VCC1, respectively, a first upper arm input signal pad 67 receiving the first upper arm input signal INH1, and a first lower arm input signal pad 68 receiving the first lower arm input signal INL1, and the second gate driver 50 further has a second gate driving bias voltage pad 56 receiving the second gate driving bias voltage VCC2, a second upper arm input signal pad 57 receiving the second upper arm input signal INHL2, and a second lower arm ihi input signal pad 58 receiving the second lower arm input signal INHL2, respectively.
In the prior art, four power devices forming the power driver are discrete devices, two of the four power devices form a single-phase upper bridge arm, each power device forming the single-phase upper bridge arm must receive a corresponding upper arm positive phase voltage in order to drive the single-phase upper bridge arm, even if each power device forming the single-phase upper bridge arm can share one upper arm positive phase voltage, each power device forming the single-phase upper bridge arm must be provided with an upper arm positive phase voltage pin, and the same upper arm positive phase voltage can be received together only by performing circuit layout on the corresponding upper arm positive phase voltage pin outside each power device forming the single-phase upper bridge arm. Since the drain D11 of the first upper arm transistor 40 and the drain D21 of the second upper arm transistor 20 are electrically connected to the upper arm positive phase voltage pin (12), then, a power driver is formed by the electrical connection of the drain D12 of the first lower arm transistor 30 and the source S11 of the first upper arm transistor 40 and the electrical connection of the drain D22 of the second lower arm transistor 10 and the source S21 of the second upper arm transistor 20, and the first upper arm chip base island 108, the first lower arm chip base island 110, the second upper arm chip base island 112 and the second lower arm chip base island 114 integrated on the same lead frame 102 are integrated together by electrical connection of transistors mounted thereon, therefore, the first upper arm transistor 40 and the second upper arm transistor 20 receive the upper arm positive phase voltage VP simultaneously through the upper arm positive phase voltage pin (12). Therefore, the invention can omit an upper arm positive phase voltage pin, thereby realizing the function of the power driver by using the least pins and reducing the size of the integrated circuit as much as possible.
Referring to fig. 5 and 6, the first gate driver may further include a first upper arm bias voltage pad 65, a first upper arm driving signal pad 64, a first upper arm bias voltage pad 63, and a first lower arm driving signal pad 62, the first upper arm driving signal pad 64, the first upper arm bias voltage pad 63, and the first lower arm driving signal pad 62 are electrically connected to the gate G11 of the first upper arm transistor, the drain D12 of the first lower arm transistor, and the gate G12, respectively, the second gate driver may further include a second upper arm bias voltage pad 55, a second upper arm driving signal pad 54, a second upper arm bias voltage pad 53, and a second lower arm driving signal pad 52, the second upper arm driving signal pad 54, the second upper arm bias voltage pad 53, and the second lower arm driving signal pad 52 are electrically connected to the gate G21, the gate G of the second upper arm transistor, and the gate G of the second lower arm transistor, respectively, The drain D22 and the gate G22 of the second lower arm transistor are electrically connected, thereby forming a single-phase integrated drive circuit. And the first gate-driving chip base island 104 and the second gate-driving chip base island 106 integrated on the same lead frame 102 are integrated with the first upper arm chip base island 108, the first lower arm chip base island 110, the second upper arm chip base island 112 and the second lower arm chip base island 114 through drivers mounted on the respective to form the same chip through electrical connections between transistors mounted on the respective. Wherein the first upper arm bias voltage pad 65, the first upper arm driving signal pad 64, the first upper arm bias voltage pad 63 and the first lower arm driving signal pad 62 receive the first upper arm bias voltage VB1, the first upper arm driving signal HO1, the first upper arm bias voltage ground VS1 and the first lower arm driving signal LO1, respectively. The second upper arm bias voltage pad 55, the second upper arm drive signal pad 54, the second upper arm bias voltage pad 53, and the second lower arm drive signal pad 52 receive the second upper arm bias voltage VB2, the second upper arm drive signal HO2, the second upper arm bias voltage ground VS2, and the second lower arm drive signal LO2, respectively.
The packaging device 100 of the compact single-phase integrated driving circuit further comprises a packaging body. The packaging body is used for plastically packaging the single-phase integrated drive circuit, the lead frame, the signal pin, the power pin and each electric connection. The size of the package can be adjusted according to the size of the power driver used: when the power of the power driver is reduced, the size of the package body can be 17.8mm in length and 11mm in width, and when the power of the power driver is increased, the size of the package body can be 25.8mm in length and 13mm in width; the size of the packaging body can be adjusted according to the size of the first gate driver and the second gate driver: when the power of the first gate driver and the second gate driver is reduced, the size of the package may be 17.8mm in length and 11mm in width, and when the power of the first gate driver and the second gate driver is increased, the size of the package may be 25.8mm in length and 13mm in width.
Because the high-voltage gate driver and the power driver are integrated on the same packaging body, discrete elements originally forming the gate driver and the power driver are not dispersed any more but are effectively integrated together, the size of the high-voltage gate driver and the power driver is reduced compared with that of a single-phase integrated driving circuit formed by discrete devices in the prior art, the design of controlling the power driver by the high-voltage gate driver is simple, and the system reliability is improved.
In addition, since the gate driver and the power driver are integrated on the same package, the problems of difficult installation and poor reliability caused by the large number of devices due to the connection of discrete components can be reduced through the circuit layout in the package, and the overall cost is reduced.
With continued reference to fig. 4, in the packaging apparatus 100 of the compact single-phase integrated drive circuit, the voltage of the first upper arm bias voltage VB1 can be as high as above 600V, and the voltage of the first gate drive bias voltage VCC1 can be as low as below 20V; the second upper arm bias voltage VB2 can be as high as 600V or more, and the second gate drive bias voltage VCC2 can be as low as 20V or less.
In addition, the voltage of the second upper arm bias voltage VB2 may be as high as 600V or more, and the voltage of the first lower arm input signal INL1 may be as low as 20V or less.
In order to prevent the problem that the center distance between the high-voltage pin and the low-voltage pin is short and the low-voltage pin and the circuit thereof are failed due to the arc discharge effect between the high-voltage pin and the low-voltage pin caused by the fact that the two pins are close to each other on the bonding pad on the PCB in a wet environment or a dust environment, the center distance between the high-voltage pin and the low-voltage pin needs to be enlarged. Since the first gate driver 60 and the second gate driver 50 are integrated on the same chip, one common ground voltage pin is omitted, and there is no package pin between the second upper arm bias voltage pin (6) and the first lower arm input signal pin (5) (see fig. 15 and 16). Therefore, the packaging device 100 of the compact single-phase integrated driving circuit has a sufficient pin center distance at the signal pin.
Although the first gate drive bias voltage pin (3) and the first upper arm bias voltage pin (1) have a first functional pin in between, a second functional pin is arranged between the second gate driving bias voltage pin (8) and the second upper arm bias voltage pin (6), the first and second functional pins are formed at the signal pins of the lead frame by bending the first and second gate driver chip base islands 104 and 106, respectively, but are not connected to the chips by metal wire bonding, and thus, no pad is required to be designed when laying out the wiring, no pin is required to be designed at the signal pin of the lead frame, therefore, sufficient pin center distances are provided between the first gate drive bias voltage pin (3) and the first upper arm bias voltage pin (1), and between the second gate drive bias voltage pin (8) and the second upper arm bias voltage pin (6).
At this time, the pin center distance between the first gate driving bias voltage pin (3) and the first upper arm bias voltage pin (1), the pin center distance between the second gate driving bias voltage pin (8) and the second upper arm bias voltage pin (6), and the pin center distance D1 between the first lower arm input signal pin (5) and the second upper arm bias voltage pin (6) are all more than twice the low voltage pin center distance, and the low voltage pin center distance is 1.778mm, as shown in fig. 15 and 16.
And the first upper arm transistor and the second upper arm transistor are also electrically connected inside the same chip, and one upper arm positive phase voltage pin is omitted. Therefore, the packaging device 100 of the compact single-phase integrated driving circuit also has a sufficient pin center distance at the power pin.
At this time, the pin center distance between the upper arm positive phase voltage pin (12) and the first drive output signal pin (13), the pin center distance between the first drive output signal pin (13) and the first detection signal pin (14), and the pin center distance D2 between the second drive output signal pin (16) and the second detection signal pin (15) are more than twice the low voltage pin center distance, see fig. 15 and 16.
As can be seen, since the high voltage gate driver and the power driver in the related art are discrete devices, the number of pins generated by external circuit connection for realizing the function of the integrated driving circuit is increased, and thus it is difficult to increase the pin center distance. In the invention, the high-voltage gate driver and the power driver are integrated on the same packaging body, so that the problem that the pins are damaged mutually due to insufficient center distance caused by the reduction of the center distance of the pins due to the limited packaging volume in the integrated driving circuit can be solved by adjusting the circuit layout inside the packaging body and the external pin arrangement, thereby reducing the cost and enhancing the reliability.
With reference to fig. 4, after the first upper arm bias voltage pin (1), the first gate driving bias voltage pin (3), the second upper arm bias voltage pin (6) and the first gate driving bias voltage pin (8) are subjected to insulation protection, when there is a requirement for practical application, the first functional pin (2) and the second functional pin (7) may be manufactured with pins to receive different signals NC1 and NC2, respectively, if the first functional pin (2) and the second functional pin (7) are set as temperature-sensing output pin output signals NC1 and NC2, the first functional pin and the second functional pin are loaded with temperature sensors and cooperate with an external resistor to output a voltage signal indicating an in-package temperature value, and after the voltage signal is processed by an external controller of the package, the voltage signal is transmitted to the corresponding first upper arm input signal pin HIN1 or first lower arm input signal pin LIN1 and second upper arm input signal pin HIN2 or second lower arm input signal pin after the voltage signal is processed by the external controller of the package LIN2 to control PWM duty cycle in real time and dynamically adjust input and output power of load. Similarly, the first functional pin (2) and the second functional pin (7) are set as output pin output signals NC1 and NC2 for detecting faults, and the first functional pin (2) and the second functional pin (7) are loaded with fault signal generators to detect the working state of a load so as to output a fault signal alarm. The first functional pin (2) and the second functional pin (7) can also be loaded with an overcurrent signal comparator to increase the overcurrent protection function.
Based on the first embodiment of the packaging apparatus of the compact single-phase integrated driving circuit, the invention provides a corresponding single-phase integrated driving circuit, as shown in fig. 7, the single-phase integrated driving circuit includes:
a high voltage gate driver 107, a power driver 115, a signal pin and a power pin integrated on the same package, wherein the high voltage gate driver 107 is composed of a first gate driver 104 and a second gate driver 106, and the power driver 115 is composed of a first upper arm transistor 108, a first lower arm transistor 110, a second upper arm transistor 112 and a second lower arm transistor 114.
The high voltage gate driver 107 receives a corresponding input signal through the signal pin to generate a driving signal, and the power driver 115 responds to the driving signal and receives and outputs a driving output signal through the power pin to control the operation of the load as follows:
the first gate driver 104 starts up after receiving input signals from a first upper arm bias voltage pin (1), a first gate drive bias voltage pin (3) and a common ground voltage pin (11), the second gate driver 106 starts up and starts up after receiving input signals from a second upper arm bias voltage pin (6), a second gate drive bias voltage pin (8) and the common ground voltage pin (11), and the first upper arm transistor and the second upper arm transistor receive power signals from an upper arm positive phase voltage pin (12).
The first condition is as follows: when the first gate driver 104 receives the first upper arm input signal INH1 from the first upper arm input signal pin (4), the second gate driver 106 receives the second lower arm input signal INL2 from the second lower arm input signal pin (10) as the driving signal, and at this time, the first gate driver 104 outputs the first upper arm driving signal HO1 to the gate G11 of the first upper arm transistor, and the second gate driver 106 outputs the second lower arm driving signal LO1 to the gate G12 of the second lower arm transistor.
Thus, the first upper arm transistor is turned on, the first lower arm transistor is turned off, and outputs the first drive output signal OUT1 at the first drive output signal pin (13) and the first detection signal N1 at the first detection signal pin (14), while the second upper arm transistor is turned off, the second lower arm transistor is turned on, and outputs the second drive output signal OUT2 at the second drive output signal pin (16) and the second detection signal N2 at the second detection signal pin (15).
Case two: when the first gate driver 104 receives the first lower arm input signal INL1 from the first lower arm input signal pin (5) as the driving signal, the second gate driver 106 receives the second upper arm input signal INH2 from the second upper arm input signal pin (9) as the driving signal, and at this time, the first gate driver 104 outputs the first lower arm driving signal LO1 to the gate G12 of the first lower arm transistor, and the second gate driver 106 outputs the second upper arm driving signal HO2 to the gate of the second upper arm transistor.
Thus, the first upper arm transistor is turned off, the first lower arm transistor is turned on, and outputs the first drive output signal OUT1 at the first drive output signal pin (13) and the first detection signal N1 at the first detection signal pin (14), while the second upper arm transistor is turned on, the second lower arm transistor is turned off, and outputs the second drive output signal OUT2 at the second drive output signal pin (16) and the second detection signal N2 at the second detection signal pin (15).
Finally, the power driver 115 drives the load to work according to the first driving output signal OUT1 and the second driving output signal OUT 2. Meanwhile, the first detection signal N1 and the second detection signal N2 detect the flowing current in real time, so that the overcurrent phenomenon is prevented.
The single-phase integrated driving circuit provided by the present invention may also correspond to the packaging device of the compact single-phase integrated driving circuit, and have the same pin structure and pin center distance, which is not described herein any more, and refer to the detailed description of each signal pin and power pin in the first embodiment.
As shown in fig. 8, the single-phase integrated drive circuit shown in fig. 7 may further include a bias voltage pin unit composed of the first upper arm bias voltage pin (1) and the second upper arm bias voltage pin (6) for driving the first upper arm transistor and the second upper arm transistor, respectively. The first upper arm bias voltage pin (1) generates the first upper arm bias voltage VB1 through an external bootstrap network (resistor R1, diode D1, capacitor C1 in fig. 8) to drive the first upper arm transistor 40; the second upper arm bias voltage pin (6) generates the second upper arm bias voltage VB2 through another external bootstrap network (resistor R2, diode D2, capacitor C2 in fig. 8) to drive the second upper arm transistor 20.
[ example two ]
On the basis of the first embodiment, referring to fig. 9 in combination with fig. 10 and 11, the packaging apparatus of the compact single-phase integrated driving circuit further includes: a first bootstrap diode pad 69 and a second bootstrap diode pad 59, the first bootstrap diode pad 69 being formed on the first gate driver 104, the second bootstrap diode pad 59 being formed on the second gate driver 106.
The packaging device of the compact single-phase integrated driving circuit further comprises a first bootstrap diode chip base island and a second bootstrap diode chip base island, wherein the first bootstrap diode chip base island is formed on the lead frame and close to the first gate driving chip base island, and the second bootstrap diode chip base island is formed on the lead frame and close to the second gate driving chip base island.
The packaging device of the compact single-phase integrated driving circuit further includes a first bootstrap diode chip 80 and a second bootstrap diode chip 70, the first bootstrap diode chip 80 is mounted on the first bootstrap diode chip base island and electrically connected to the first functional pin and the first bootstrap diode pad, and the second bootstrap diode chip 70 is formed on the second bootstrap diode chip base island and electrically connected to the second functional pin and the second bootstrap diode pad. Therefore, the first bootstrap diode chip 80 and the second bootstrap diode chip 70 are integrated with the high voltage gate driver and the power driver on the same package, so that reliability between devices is improved, and additional mounting cost is reduced.
Therefore, as the high-voltage gate driver and the power driver are integrated on the same package body, different effective layouts can be conveniently carried out on the mutual circuits between the high-voltage gate driver and the power driver, so that under the condition that the total number of the signal pins and the power pins is not changed, the signal pins can be reasonably utilized to receive input signals according to different application requirements, and the power pins generate driving output signals to drive a load to work; different devices can be loaded at the first functional pin and the second functional pin of the signal pin according to different application requirements, so that the single-phase integrated drive circuit can be effectively detected, and the fault occurrence rate and the maintenance problem are reduced.
Based on the packaging device of the compact single-phase integrated drive circuit in the second embodiment, the invention provides a corresponding single-phase integrated drive circuit. Compared with the single-phase integrated drive circuit shown in fig. 7, the single-phase integrated drive circuit shown in fig. 12 is different in that:
referring to fig. 10 and 11, the first gate driver has a first bootstrap diode pad 69, and in the first gate driver, the first bootstrap diode pad 69 is connected to a first gate driving bias voltage pad 66, and after the first bootstrap diode pad 69 is connected to the anode of the first bootstrap diode 80 through the first functional pin (2), the cathode of the first bootstrap diode 80 is led out of the first upper arm bias voltage pin (1) through the first bootstrap diode chip base island; the second gate driver is provided with a second bootstrap diode pressure welding point 59, in the second gate driver, the second bootstrap diode pressure welding point 59 is connected with a second gate driving bias voltage pressure welding point 56, and after the second bootstrap diode pressure welding point 59 is connected with the anode of the second bootstrap diode 70 through the second functional pin (7), the cathode of the second bootstrap diode 70 is led out of the second upper arm bias voltage pin (6) through the second bootstrap diode chip base island.
As shown in fig. 13, the single-phase integrated drive circuit shown in fig. 12 may further include a bias voltage pin unit composed of the first upper arm bias voltage pin (1) and the second upper arm bias voltage pin (6) for driving the first upper arm transistor and the second upper arm transistor, respectively. The first upper arm bias voltage pin (1) generates the first upper arm bias voltage VB1 through an external bootstrap capacitor C1 to drive the first upper arm transistor 40; the second upper arm bias voltage pin (6) generates the second upper arm bias voltage VB2 through another external bootstrap capacitor C2, and drives the second upper arm transistor 20.
[ EXAMPLE III ]
In addition to the first embodiment or the second embodiment, the packaging apparatus 100 of the compact single-phase integrated driving circuit further includes: a plurality of second chip base islands formed on the lead frame 102, and switch units respectively mounted on each of the second chip base islands, each of the switch units being formed by connecting an upper arm switch unit and a lower arm switch unit in series end to end.
Preferably, each of the upper arm switching units includes an ON resistance RG _ ON, and each of the lower arm switching units includes an OFF resistance RG _ OFF.
Respectively receiving a start end, a middle end and a tail end of one of the switch units connected end to end in series to the first upper arm bias voltage VB1, the first upper arm driving signal HO1 and the first upper arm bias voltage VS 1; respectively receiving the first gate driving bias voltage VCC1, the first lower arm driving signal LO1 and the common ground voltage COM from the start end, the middle end and the end of another switch unit connected end to end in series; the start end, the middle end and the tail end of one more switch units connected end to end in series receive the second upper arm bias voltage VB2, a second upper arm driving signal HO2 and a second upper arm bias voltage VS2 respectively; the start terminal, the middle terminal and the end terminal of still another one of the switching units connected end to end in series receive the second gate driving bias voltage VCC2, the second lower arm driving signal LO2 and the common ground voltage COM, respectively.
Because the high-voltage gate driver and the power driver are integrated on the same packaging body, the internal wiring of the integrated circuit is short, and the wiring inductance and the wiring resistance are extremely small, the gate filter capacitor Cgate originally placed for preventing the Miller effect can be omitted. In addition, each driving resistor R originally used for adjusting the rising and falling edge time of the output signal of the power device is divided into the ON resistor RG _ ON and the OFF resistor RG _ OFF and integrated into the first gate driver and the second gate driver, the resistance values of the ON resistor RG _ ON and the OFF resistor RG _ OFF are properly adjusted according to the requirements of system design and the parameters of the power device, and the ON and OFF of the power devices respectively connected with the first upper arm driving signal HO1, the first lower arm driving signal LO1, the second upper arm driving signal HO2 and the second lower arm driving signal LO2 can be adjusted, so that the single-phase integrated driving circuit can have smaller switching loss ON the basis of keeping smaller EMI.
Based on the packaging apparatus of the compact single-phase integrated driving circuit according to the third embodiment, the present invention provides a corresponding single-phase integrated driving circuit, the single-phase integrated driving circuit according to the third embodiment has a first gate driver and a second gate driver, and since the first gate driver and the second gate driver have the same structure, the single-phase integrated driving circuit shown in fig. 14, taking the first gate driver as an example, is different from the single-phase integrated driving circuit shown in fig. 3 in that:
the first gate driver integrates two switching units, each of the switching units includes an upper arm switching unit and a lower arm switching unit, and a power device connected with the switching unit is turned ON by adjusting the size of an ON-resistance RG _ ON arranged in each of the upper arm switching units; the power device connected thereto is turned OFF by adjusting the magnitude of the OFF resistance RG _ OFF provided in each of the lower arm switch units.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (12)

1. An apparatus for packaging a compact single-phase integrated drive circuit, comprising:
a lead frame;
forming a plurality of first chip base islands on the lead frame;
the signal pins and the power pins are respectively formed on two opposite sides of the lead frame and are led out through the bending of the plurality of first chip base islands;
a first gate driver, a second gate driver, a first upper arm transistor, a first lower arm transistor, a second upper arm transistor and a second lower arm transistor respectively mounted on each of the first chip base islands, wherein the first gate driver, the second gate driver, the first upper arm transistor, the first lower arm transistor, the second upper arm transistor and the second lower arm transistor are respectively electrically connected; and
the packaging structure comprises a packaging body, a packaging body and a packaging body, wherein the length of the packaging body is 17.8-25.8 mm, and the width of the packaging body is 11-13 mm; wherein,
the signal pins corresponding to the first gate driver comprise a first upper arm bias voltage pin, a first gate driving bias voltage pin, a first upper arm input signal pin, a first lower arm input signal pin and a common-ground voltage pin, and the signal pins corresponding to the second gate driver comprise a second upper arm bias voltage pin, a second gate driving bias voltage pin, a second upper arm input signal pin, a second lower arm input signal pin and the common-ground voltage pin;
the power pin corresponding to the first upper arm transistor comprises an upper arm positive phase voltage pin and a first drive output signal pin, the power pin corresponding to the first lower arm transistor comprises the first drive output signal pin and a first detection signal pin, the power pin corresponding to the second upper arm transistor comprises the upper arm positive phase voltage pin and a second detection signal pin, and the power pin corresponding to the second lower arm transistor comprises the second detection signal pin and a second drive output signal pin;
the center distance between the first gate drive bias voltage pin and the first upper arm bias voltage pin, the center distance between the second gate drive bias voltage pin and the second upper arm bias voltage pin, and the center distance between the first lower arm input signal pin and the second upper arm bias voltage pin are more than twice of the center distance of the low-voltage pins.
2. The packaging apparatus of compact single-phase integrated driving circuit according to claim 1,
the center distance between the upper arm positive phase voltage pin and the first drive output signal pin, the center distance between the first drive output signal pin and the first detection signal pin, and the center distance between the second drive output signal pin and the second detection signal pin are more than twice of the center distance of the low voltage pin.
3. The packaging apparatus of compact single-phase integrated driving circuit according to claim 2,
a first functional pin is arranged between the first gate driving bias voltage pin and the first upper arm bias voltage pin, and a second functional pin is arranged between the second gate driving bias voltage pin and the second upper arm bias voltage pin.
4. The packaging apparatus of compact single-phase integrated driving circuit according to claim 3,
and loading a temperature sensor or loading a fault signal generator or loading an over-current signal comparator on the first functional pin and the second functional pin.
5. The apparatus for packaging a compact single-phase integrated driver circuit as recited in claim 3, further comprising:
forming a first bootstrap diode pad on the first gate driver and forming a second bootstrap diode pad on the second gate driver;
forming a first bootstrap diode chip base island and a second bootstrap diode chip base island on the lead frame;
the first bootstrap diode chip is installed on the first bootstrap diode chip base island and electrically connected with the first functional pin and the first bootstrap diode pressure welding point;
and the second bootstrap diode chip is installed on the second bootstrap diode chip base island and is electrically connected with the second functional pin and the second bootstrap diode pressure welding point.
6. The packaging apparatus of a compact single-phase integrated driving circuit according to claim 4 or 5, further comprising:
forming a plurality of second chip base islands on the lead frame;
and the switch units are respectively arranged on each second chip base island, and each switch unit comprises an upper arm switch unit and a lower arm switch unit.
7. A single-phase integrated drive circuit, comprising:
a high voltage gate driver, a power driver, a signal pin and a power pin integrated on the same package, wherein the high voltage gate driver is composed of a first gate driver and a second gate driver, and the power driver is composed of a first upper arm transistor, a first lower arm transistor, a second upper arm transistor and a second lower arm transistor;
the high-voltage gate driver receives a driving signal generated by an input signal through the signal pin, and the power driver responds to the driving signal and outputs a driving output signal for controlling the work of a load through the power pin; wherein,
the signal pins corresponding to the first gate driver are a first upper arm bias voltage pin, a first gate driving bias voltage pin, a first upper arm input signal pin, a first lower arm input signal pin and a common-ground voltage pin, and the signal pins corresponding to the second gate driver are a second gate driving bias voltage pin, a second upper arm input signal pin, a second lower arm input signal pin and the common-ground voltage pin;
the power pins corresponding to the first upper arm transistor are an upper arm positive phase voltage pin and a first drive output signal pin, the power pins corresponding to the first lower arm transistor are the first drive output signal pin and a first detection signal pin, the power pins corresponding to the second upper arm transistor are the upper arm positive phase voltage pin and a second detection signal pin, and the power pins corresponding to the second lower arm transistor are the second detection signal pin and a second drive output signal pin;
the center distance between the first gate driving bias voltage pin and the first upper arm bias voltage pin, the center distance between the second gate driving bias voltage pin and the second upper arm bias voltage pin, and the center distance between the first lower arm input signal pin and the second upper arm bias voltage pin are twice of the center distance of the low-voltage pins.
8. The single-phase integrated drive circuit of claim 7, wherein,
the center distance between the upper arm positive phase voltage pin and the first drive output signal pin, the center distance between the first drive output signal pin and the first detection signal pin, and the center distance between the second drive output signal pin and the second detection signal pin are more than twice of the center distance of the low voltage pin.
9. The single-phase integrated drive circuit of claim 8, wherein,
a first functional pin is arranged between the first gate driving bias voltage pin and the first upper arm bias voltage pin; and a second functional pin is arranged between the second gate driving bias voltage pin and the second upper arm bias voltage pin.
10. The single-phase integrated drive circuit of claim 9, wherein,
and loading a temperature sensor or loading a fault signal generator or loading an over-current signal comparator on the first functional pin and the second functional pin.
11. The single-phase integrated drive circuit of claim 9, wherein,
the first gate driver is provided with a first bootstrap diode bonding pad, the first bootstrap diode bonding pad is electrically connected with a first functional pin, and the first functional pin and a first upper arm bias voltage pin are respectively electrically connected with the anode and the cathode of the first bootstrap diode;
the second gate driver is provided with a second bootstrap diode bonding pad, the second bootstrap diode bonding pad is electrically connected with a second functional pin, and the second functional pin and a second upper arm bias voltage pin are respectively electrically connected with the anode and the cathode of the second bootstrap diode.
12. The single-phase integrated drive circuit according to claim 10 or 11, further comprising a plurality of switching units integrated for power driving, each of the switching units including an upper arm switching unit and a lower arm switching unit.
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