CN102903323A - Shifting register unit, gate drive circuit and display device - Google Patents
Shifting register unit, gate drive circuit and display device Download PDFInfo
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- CN102903323A CN102903323A CN2012103830626A CN201210383062A CN102903323A CN 102903323 A CN102903323 A CN 102903323A CN 2012103830626 A CN2012103830626 A CN 2012103830626A CN 201210383062 A CN201210383062 A CN 201210383062A CN 102903323 A CN102903323 A CN 102903323A
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Abstract
The invention provides a shifting register unit, a gate drive circuit and a display device, and relates to the field of production of displays, so that number of signal lines and film field effect transistors, which are integrated in the shifting register unit, can be reduced, and a space is saved, so that the product cost is reduced. The shifting register unit comprises a pre-charging module, a signal output module, an output level pull-down module, a first knot voltage control module and a second knot voltage control module.
Description
Technical field
The present invention relates to liquid crystal display and make the field, relate in particular to shift register cell, gate driver circuit and display device.
Background technology
The in the last few years development of display has presented high integration, cheaply development trend.Wherein realization that very important technology is exactly the technology mass production of the capable driving of array base palte (Gate Driver on Array is called for short GOA).Utilize the GOA technology gate switch circuit to be integrated on the array base palte of display panel to form the turntable driving to display panel, thereby can save the grid-driving integrated circuit part, it not only can reduce cost of products from material cost and manufacture craft two aspects, and display panel can be accomplished the design for aesthetic of both sides symmetry and narrow frame.Owing to the technique that can save Gate direction Bonding (binding), also more favourable to production capacity and Yield lmproved simultaneously.The gate switch circuit that this GOA of utilization technology is integrated on the array base palte is also referred to as GOA circuit or shift-register circuit.
Shift-register circuit comprises several shift register cells, the corresponding grid line of each shift register cell, and except first shift register cell and last shift register cell, the output terminal of all the other each shift register cells connects the signal input part of the next shift register cell that is adjacent; Existing shift register cell structure assembly a large amount of signal wire and Thin Film Transistor (TFT) (Thin Film Transistor is called for short TFT) greatly increased cost of products so that circuit takes up space.
Summary of the invention
Embodiments of the invention provide a kind of shift register cell, gate driver circuit and display device, can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
For achieving the above object, embodiments of the invention adopt following technical scheme:
First aspect, the embodiment of the invention provides a kind of shift register cell, comprise: pre-charge module, signal output module, the drop-down module of output level, the first node voltage control module and the second node voltage control module, the first node is the tie point of described pre-charge module and signal output module, and the second node is the tie point of described the first node voltage control module and the second node voltage control module;
Wherein, described pre-charge module connects first signal input end and the first node, is used under the control of described first signal input end described signal output module precharge;
Described signal output module connects signal output part, described the first node and the first clock signal, is used for connecting under the control of described the first node voltage described the first clock signal and described signal output part;
The drop-down module of described output level connects described signal output part, second clock signal and the first voltage end, is used for connecting under the control of described second clock signal described signal output part and described the first voltage end;
Described the first node voltage control module connects second clock signal, described the first voltage end, described the first node and the second node, is used for connecting under the control of described second clock signal described the first node and described the first voltage end;
Described the second node voltage control module connects described first signal input end, described signal output part, described the first voltage end and described the second node, is used for control and connects described the second node and described the first voltage end.
In the possible implementation of the first, according to first aspect,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor are connected described first signal input end with source electrode, the drain electrode of described the first transistor connects described the first node;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connect described the first node, and the source electrode of described transistor seconds connects described the first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
The first electric capacity, a utmost point of described the first electric capacity connects the grid of described transistor seconds, and another utmost point of described the first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of described output level comprises:
The 3rd transistor, the described the 3rd transistorized grid connects described second clock signal, and the described the 3rd transistorized source electrode connects described signal output part, and the described the 3rd transistorized drain electrode connects described the first voltage end;
Described the first node voltage control module comprises:
The 4th transistor, the described the 4th transistorized grid is connected described second clock signal with source electrode, and the described the 4th transistorized drain electrode connects described the second node;
The 5th transistor, the described the 5th transistorized grid connects described the second node, and the described the 5th transistorized source electrode connects described the first node, and the described the 5th transistorized drain electrode connects described the first voltage end;
The second node voltage control module comprises:
The 6th transistor, the described the 6th transistorized grid connects described first signal input end, and the described the 6th transistorized source electrode connects described the second node, and the described the 6th transistorized drain electrode connects described the first voltage end;
The 7th transistor, the described the 7th transistorized grid connects described signal output part, and the described the 7th transistorized source electrode connects described the second node, and the described the 7th transistorized drain electrode connects described the first voltage end.
In the possible implementation of the second, according to first aspect,
Described pre-charge module also connects secondary signal input end, second voltage end and tertiary voltage end, being used at described second voltage end is that high level tertiary voltage end is when being low level, under the control of described first signal input end, to described signal output module precharge, under the control of described secondary signal input end, connect described the first node and described tertiary voltage end;
Perhaps described second voltage end is that low level tertiary voltage end is when being high level, under the control of described secondary signal input end, to described signal output module precharge, under the control of described first signal input end, connect described the first node and described second voltage end;
The drop-down module of described output level also connects the 3rd signal input part and the 4th signal input part, is used for connecting under the control of the 3rd signal input part or the 4th signal input part described signal output part and described the first voltage end;
Described the second node voltage control module also connects described secondary signal input end, is used for connecting under the control of described secondary signal input end described the second node and described the first voltage end.
In the third possible implementation, the implementation possible according to the second,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor connect described first signal input end, and the source electrode of described the first transistor connects described second voltage end, and the drain electrode of described the first transistor connects described the first node;
The 8th transistor, the described the 8th transistorized grid connects described secondary signal input end, and the described the 8th transistorized source electrode connects described the first node, and the described the 8th transistorized drain electrode connects described tertiary voltage end;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connect described the first node, and the source electrode of described transistor seconds connects described the first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
The first electric capacity, a utmost point of described the first electric capacity connects the grid of described transistor seconds, and another utmost point of described the first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of output level comprises:
The 3rd transistor, the described the 3rd transistorized grid connects described second clock signal, and the described the 3rd transistorized source electrode connects described signal output part, and the described the 3rd transistorized drain electrode connects described the first voltage end;
The 9th transistor, the described the 9th transistorized grid connects described the 3rd signal input part, and the described the 9th transistorized source electrode connects described signal output part, and the described the 9th transistorized drain electrode connects described the first voltage end;
The tenth transistor, the described the tenth transistorized grid connects described the 4th signal input part, and the described the tenth transistorized source electrode connects described signal output part, and the described the tenth transistorized drain electrode connects described the first voltage end;
The first node voltage control module comprises:
The 4th transistor, the described the 4th transistorized grid is connected described second clock signal with source electrode, and the described the 4th transistorized drain electrode connects described the second node;
The 5th transistor, the described the 5th transistorized grid connects described the second node, and the described the 5th transistorized source electrode connects described the first node, and the described the 5th transistorized drain electrode connects described the first voltage end;
The second node voltage control module comprises:
The 6th transistor, the described the 6th transistorized grid connects described first signal input end, and the described the 6th transistorized source electrode connects described the second node, and the described the 6th transistorized drain electrode connects described the first voltage end;
The 7th transistor, the described the 7th transistorized grid connects described output signal end, and the described the 7th transistorized source electrode connects described the second node, and the described the 7th transistorized drain electrode connects described the first voltage end.
The 11 transistor, the described the 11 transistorized grid connects described secondary signal input end, and the described the 11 transistorized source electrode connects described the second node, and the described the 11 transistorized drain electrode connects described the first voltage end.
Wherein, above-mentioned the first voltage end is earth terminal.
Second aspect, a kind of gate driver circuit is provided, comprise that series connection is a plurality of such as the described shift register cell of the possible implementation of the first of first aspect or first aspect, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input end of the next shift register cell that is adjacent.
The third aspect, a kind of gate driver circuit is provided, comprise series connection a plurality of implementation or the second possible implementation described shift register cells possible such as the first of first aspect, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input end of the next shift register cell that is adjacent, the signal output part of each shift register cell also connects the secondary signal input end of a upper shift register cell that is adjacent, except the first two shift register cell with latter two shift register cell, the signal output part of all the other each shift register cells also connect with its on the 3rd signal input part of adjacent second shift register cell and the lower neighbour's that is adjacent the 4th signal input part of second shift register cell.
Fourth aspect, the embodiment of the invention provide a kind of display device, comprising:
The viewing area has for a plurality of pixels that show image;
Gate driver circuit is used for sweep signal is delivered to described viewing area;
Data drive circuit is used for data-signal is delivered to described viewing area;
It is characterized in that described gate driver circuit is above-mentioned arbitrary gate driver circuit.
The shift register cell that the embodiment of the invention provides, gate driver circuit and display device can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The simple scanning shift register cell structural representation that Fig. 1 provides for the embodiment of the invention;
The simple scanning shift register cell electrical block diagram that Fig. 2 provides for the embodiment of the invention;
The bilateral scanning shift register cell structural representation that Fig. 3 provides for the embodiment of the invention;
The bilateral scanning shift register cell electrical block diagram that Fig. 4 provides for the embodiment of the invention;
Simple scanning shift register cell the first clock signal that Fig. 5 provides for the embodiment of the invention, second clock signal, PU voltage node and signal output waveform synoptic diagram;
Bilateral scanning shift register cell the first clock signal that Fig. 6 provides for the embodiment of the invention, second clock signal, PU voltage node and signal output waveform synoptic diagram;
The grid electrode drive circuit structure formula synoptic diagram of the simple scanning that Fig. 7 provides for the embodiment of the invention;
The grid electrode drive circuit structure formula synoptic diagram of the bilateral scanning that Fig. 8 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The transistor that adopts among all embodiment of the present invention all can be thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the transistorized source electrode that adopts here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein a utmost point is called source electrode, and another utmost point is called drain electrode.Stipulate that by the form in the accompanying drawing transistorized upside is that source electrode, intermediate ends are that grid, lower side are drain electrode.In addition; transistor can be divided into N-type and P type according to transistorized characteristic differentiation; following examples all describe as inner take the N transistor; what can expect is that those skilled in the art can expect easily not making under the creative work prerequisite when adopting the P transistor npn npn to realize, therefore also in the embodiments of the invention protection domain.
The structural representation of the individual event scan shift deposit unit that Fig. 1 provides for the embodiment of the invention, comprise: pre-charge module 11, signal output module 12, the drop-down module 13 of output level, the first node voltage control module 14 and the second node voltage control module 15, the first node PU is the tie point of pre-charge module 11 and signal output module 12, and the second node PD is the tie point of the first node voltage control module 14 and the second node voltage control module 15; And the first signal input end of the shift register among Fig. 1 is INPUT1, and signal output part is OUTPUT, and the first clock signal is CLK, and the second clock signal is CLKB, and the first node is the PU point, and the second node is the PD point, and the first voltage end is V1;
The below specifically describes the relation between its each parts:
The drop-down module 13 of output level connects signal output part OUTPUT, second clock signal CLKB and the first voltage end V1, is used for connection signal output terminal OUTPUT and the first voltage end V1 under the control of second clock signal CLKB;
The first node voltage control module 14 connects second clock signal CLKB, the first voltage end V1, described the first node PU point and the second node PD point, is used for connecting under the control of second clock signal first node PU and the first voltage end V1;
The second node voltage control module 15 connects first signal input end INPUT1, signal output part OUTPUT, the first voltage end V1 and the second node PD point, is used for control and connects the second node PD and the first voltage end V1.
The shift register cell that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
Optionally, the electrical block diagram of a kind of shifting deposit unit that Fig. 2 provides for the embodiment of the invention, be applied to individual event scanning, comprise: pre-charge module 11, signal output module 12, the drop-down module 13 of output level, the first node voltage control module 14, the second node voltage control module 15, following examples all are to describe as an example of the N-type transistor example, be that each transistorized characteristic is conducting when the grid input high level among the following embodiment, when the grid input low level, end, because the characteristic first voltage end V1 of N-type pipe is for adopting low level, the first voltage end V1 directly describes as an example of connection earth terminal VSS example among Fig. 2, and the annexation of the electricity device that comprises in each concrete module is as follows:
When first signal input end INPUT1 had the high level input, the first transistor T1 was conducting state, and precharge is carried out in the signal output module precharge that is connected with the first node PU point, so that the voltage of the first node PU raises;
The first capacitor C 1, a utmost point of this first capacitor C 1 connects the grid of transistor seconds T2, and another utmost point of this first capacitor C 1 connects the drain electrode of transistor seconds T2;
Wherein, after pre-charge module 11, when the first clock signal clk was high level, the first capacitor C 1 discharge conducting transistor seconds T2 was communicated with the first clock signal clk and signal output part OUTPUT, so that the output signal of shift register cell is high level;
The drop-down module 13 of output level comprises: the grid of the 3rd transistor T 3, the three transistor Ts 3 connects second clock signal CLKB, and the source electrode of the 3rd transistor T 3 connects signal output part OUTPUT, and the drain electrode of the 3rd transistor T 3 connects earth terminal VSS;
Wherein, after the shift register cell output high level signal, the first clock signal clk becomes low level, second clock signal CLKB becomes high level, by second clock signal CLKB control T3 conducting, connection signal output terminal OUTPUT and earth terminal VSS, the output signal of drop-down shift register cell at the corresponding levels;
The first node voltage control module 14 comprises: the grid of the 4th transistor T 4, the four transistor Ts 4 is connected second clock signal CLKB with source electrode, and the drain electrode of the 4th transistor T 4 connects the second node PD point;
The grid of the 5th transistor T 5, the five transistor Ts 5 connects the second node PD point, and the source electrode of the 5th transistor T 5 connects the first node PU point, and the drain electrode of the 5th transistor T 5 connects earth terminal VSS;
Wherein, after the shift register cell output high level signal, the first clock signal clk becomes low level, when second clock signal CLKB becomes high level, by second clock signal CLKB control T4 and T5 conducting, connect the first node PU and earth terminal VSS, drop-down PU voltage node voltage;
The second node voltage control module 15 comprises: the grid of the 6th transistor T 6, the six transistor Ts 6 connects first signal input end INPUT1, and the source electrode of the 6th transistor T 6 connects the second node PD point, and the drain electrode of the 6th transistor T 6 connects earth terminal VSS;
The grid of the 7th transistor T 7, the seven transistor Ts 7 connects output signal end OUTPUT, and the source electrode of the 7th transistor T 7 connects the second node PD point, and the drain electrode of the 7th transistor T 7 connects earth terminal VSS;
Wherein, for keep PU voltage node voltage at high level not by drop-down, should so that PU voltage node voltage when being high level PD voltage node voltage be low level, and the voltage that PU is ordered must keep high level at the output stage of pre-charging stage and shift register cell at the corresponding levels, therefore T6 conducting when first signal input end input high level, the second node PD and earth terminal VSS are connected in control, and holding PD voltage node voltage is low level; T7 conducting when shift register cell signal output part output high level at the corresponding levels, the second node PD and earth terminal VSS are connected in control, and keeping PD voltage node voltage is low level.
To describe as an example of the N-type transistor example in the accompanying drawings among the above embodiment, because the transistorized characteristic of N-type is the conducting of grid high level, the cut-off of grid low level, need the first clock signal clk and second clock signal CLKB to provide corresponding level with this and could realize above-mentioned circuit function, in addition because the characteristic of N-type transistor high level conducting so the first voltage end V1 are the employing low level, among the figure directly to connect earth terminal VSS as example, need the shape of corresponding adjustment the first clock signal and second clock signal when certainly just adopting the P transistor npn npn and the first voltage end V1 is connected to a high level, to guarantee the normal operation of circuit, concrete principle repeats no more for those skilled in the art are understandable herein.
The shift register cell that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
In conjunction with Fig. 2 and Fig. 5, wherein Fig. 2 provides time-state method (wherein Fig. 5 is the time-state method of CLK, CLKB, PU point and each signal end signal of OUTPUT) the individual event scan shift register unit that the embodiment of the invention provides and the function of shift-register circuit specific implementation of the circuit diagram of individual event scan shift register unit, individual event scan shift register unit that Fig. 5 provides as follows:
In the t1 time period, first signal input end INPUT1 is high level, the first clock signal clk is low level, second clock signal CLKB is high level, the T1 conducting is charged to C1, and conducting T2 is so that the T2 grid is high level, and to keep T5 be cut-off state thereby the T6 conducting drags down the PD point voltage, and the PU point is in high level in the cycle t1 thereby remain on; The t2 time period behind t1, the first clock signal clk is high level, second clock signal CLKB is low level, it is conducting state that the C1 discharge keeps T2, then signal output part OUTPUT is high level, T5 is cut-off state thereby the T7 conducting drags down the maintenance of PD point voltage, and the PU point is in high level in the cycle t2 thereby remain on; The t3 time period behind t2, the first clock signal clk is low level, and second clock signal CLKB is high level, conducting T3, T4 and T5, and the PD point is noble potential, so that signal output part OUTPUT is low level, the PU point also is low level; In non-working time, the first clock signal clk is high level at shift register, and second clock signal CLKB is low level, and without turn-on transistor, signal output part OUTPUT is low level.
The shift register cell that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
Optionally, be illustrated in figure 3 as the structural representation of a kind of bilateral scanning shift register cell that embodiments of the invention provide, comprise: pre-charge module 31, signal output module 32, the drop-down module 33 of output level, the first node voltage control module 34, the first signal input end of the shift register among the second node voltage control module 35 and Fig. 3 is INPUT1, secondary signal input end INPUT2, the 3rd signal input part INPUT3, the 4th signal input part INPUT4, signal output part is OUTPUT, the first clock signal is CLK, the second clock signal is CLKB, the first node is the PU point, the second node is the PD point, the first voltage end is V1, second voltage end V2, tertiary voltage end V3, wherein second voltage end V2 is input high level during forward scan, tertiary voltage end V3 input low level, perhaps second voltage end V2 is input low level during reverse scan, tertiary voltage end V3 input high level, here the first voltage end V1 is a low level, in addition concrete restriction is not done in forward scanning or reverse scan, just for the direction of distinguishing scanning is different, the annexation between each parts of concrete its is:
The drop-down module 33 of output level, connect signal output part OUTPUT, second clock signal CLKB, the first voltage end V1, the 3rd signal input part INPUT3 and the 4th signal input part INPUT4, the drop-down module 33 of output level is used for connection signal output terminal OUTPUT and the first voltage end V1 under the control of second clock signal CLKB, the level of degrade signal output terminal OUTPUT; The drop-down module 33 of output level is used for connection signal output terminal OUTPUT and the first voltage end V1, the i.e. level of degrade signal output terminal OUTPUT when the voltage of the 3rd signal input part INPUT3 is high level under the 3rd signal input part INPUT3 control during this external forward scan; When reverse scan, be used for connection signal output terminal OUTPUT and the first voltage end V1 under the 4th signal input part INPUT4 control, namely at the 3rd signal input part INPUT3, the level of degrade signal output terminal OUTPUT when namely the voltage of the 4th signal input part INPUT4 is high level.
The first node voltage control module 34 connects second clock signal CLKB, earth terminal VSS, the first node PU point and the second node PD point.The first node voltage control module 34 is used for connecting the first node PU and the first voltage end V1 under the control of described second clock signal CLKB, be that shift register cell is exported after the high level signal, the first clock signal clk becomes low level, when second clock signal CLKB becomes high level, the voltage that drop-down the first node PU is ordered.
The second node voltage control module 35 connects first signal input end INPUT1, signal output part OUTPUT, the first voltage end V1, the second node PD point and secondary signal input end INPUT2.The second node voltage control module 35 is used for connecting described the second node PD and described the first voltage end V1 in first signal input end INPUT1 control, be that first signal input end INPUT1 drags down the voltage that the second node PD is ordered when being high level, be used for connecting described the second node PD and described the first voltage end V1 in secondary signal input end INPUT2 control, drag down the voltage that the second node PD is ordered when namely secondary signal input end INPUT2 is high level.
The shift register cell that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
Optionally, the electrical block diagram of bilateral scanning shift register cell as shown in Figure 4, comprise: pre-charge module 31, signal output module 32, the drop-down module 33 of output level, the first node voltage control module 34, the second node voltage control module 35, the first signal input end of the shift register cell among Fig. 4 is INPUT1, secondary signal input end INPUT2, the 3rd signal input part INPUT3, the 4th signal input part INPUT4, signal output part is OUTPUT, the first clock signal is CLK, the second clock signal is CLKB, the first node is the PU point, the PU point is the node of the grid of the source electrode of first crystal T1 pipe drain electrode and the 5th transistor T 5 and transistor seconds T2, the second node is the PD point, and the PD point is the node of the source electrode of the source electrode of the grid of the 5th transistor T 5 and the 6th transistor T 6 and the 7th transistor T 7, second voltage end V2, tertiary voltage end V3, the first voltage end V1, the first voltage end V1 is take earth terminal VSS as example among the figure, and the annexation of each concrete electricity device is as follows:
The grid of the 8th transistor T 8, the eight transistor Ts 8 connects secondary signal input end N+1_OUTPUT, and the source electrode of the 8th transistor T 8 connects the first node PU point, and the drain electrode of the 8th transistor T 8 connects tertiary voltage end V3;
Wherein, the forward surface sweeping stage, second voltage end V2 is that high level tertiary voltage end V3 is low level, when the first signal input end INPUT1 in the pre-charge module 31 is high level, the first transistor T1 is conducting state, and the first node PU point is carried out precharge, when secondary signal input end INPUT2 is high level (during next stage shift register cell output high level), the 8th transistor T 8 is conducting state, and carries out drop-down to the first node PU point voltage; The reverse scan stage, second voltage end V2 is that low level tertiary voltage end V3 is high level, when the secondary signal input end INPUT2 in the pre-charge module 31 is high level, the 8th transistor T 8 is conducting state, and the first node PU point carried out precharge, when first signal input end INPUT1 is high level (during upper level shift register cell output high level), the first transistor T1 is conducting state, and carries out drop-down to the first node PU point voltage.
The first capacitor C 1, a utmost point of this first capacitor C 1 connects the grid of transistor seconds T2, and another utmost point of this first capacitor C 1 connects the drain electrode of transistor seconds T2;
Wherein, when the first clock signal clk was high level, transistor seconds T2 was conducting state, so that the output signal of shift register cell is high level.
The drop-down module 33 of output level comprises: the grid of the 3rd transistor T 3, the three transistor Ts 3 connects second clock signal CLKB, and the source electrode of the 3rd transistor T 3 connects signal output part OUTPUT, and the drain electrode of the 3rd transistor T 3 connects earth terminal VSS;
The grid of the 9th transistor T 9, the nine transistor Ts 9 connects the 3rd signal input part INPUT3, and the source electrode of the 9th transistor T 9 connects signal output part OUTPUT, and the drain electrode of the 9th transistor T 9 connects earth terminal VSS;
The grid of the tenth transistor T 10, the ten transistor Ts 10 connects the 4th signal input part INPUT4, and the source electrode of the tenth transistor T 10 connects signal output part OUTPUT, and the drain electrode of the tenth transistor T 10 connects earth terminal VSS;
Wherein, after the shift register cell output high level signal, the first clock signal clk becomes low level, second clock signal CLKB becomes high level, this moment, second clock signal CLKB controlled 3 conductings of the 3rd transistor T, and shift register cell output signal at the corresponding levels is played drop-down, reset response; In addition, in the forward scan stage, become high level at next stage the first clock signal clk, when second clock signal CLKB is low level, by the 3rd signal input part INPUT3 control, 9 pairs of shift register cell output signals at the corresponding levels of the 9th transistor T play drop-down, reset response; In the reverse scan stage, 10 pairs of shift register cell output signals at the corresponding levels of the tenth transistor T play drop-down, reset response.
The first node voltage control module 34 comprises: the grid of the 4th transistor T 4, the four transistor Ts 4 is connected second clock signal CLKB with source electrode, and the drain electrode of the 4th transistor T 4 connects the second node PD point;
The grid of the 5th transistor T 5, the five transistor Ts 5 connects the second node PD point, and the source electrode of the 5th transistor T 5 connects the first node PU point, and the drain electrode of the 5th transistor T 5 connects earth terminal VSS;
Wherein, after the output high level signal of shift register cell, the first clock signal clk becomes low level, when second clock signal CLKB becomes high level, by second clock signal CLKB control, the 4th transistor T 4 and 5 pairs of PU voltage node of the 5th transistor T voltage play drop-down, reset response;
The second node voltage control module 35 comprises: the grid of the 6th transistor T 6, the six transistor Ts 6 connects first signal input end INPUT1, and the source electrode of the 6th transistor T 6 connects the second node PD point, and the drain electrode of the 6th transistor T 6 connects earth terminal VSS;
The grid of the 7th transistor T 7, the seven transistor Ts 7 connects output signal end OUTPUT, and the source electrode of the 7th transistor T 7 connects the second node PD point, and the drain electrode of the 7th transistor T 7 connects earth terminal VSS.
The grid of the 11 transistor T 11, the 11 transistor Ts 11 connects secondary signal input end INPUT2, and the source electrode of the 11 transistor T 11 connects the second node PD point, and the drain electrode of the 11 transistor T 11 connects earth terminal VSS.
Wherein, be that high level is not by drop-down in order to keep PU voltage node voltage, should make PU voltage node voltage when being high PD voltage node voltage be low level, and the voltage that PU is ordered must keep high level at the output stage of pre-charging stage and shift register cell at the corresponding levels, with this in the forward scan stage, T6 conducting when first signal input end INPUT1 input high level, keeping PD voltage node voltage is low level; T7 conducting when shift register cell signal output part output high level at the corresponding levels, keeping PD voltage node voltage is low level; The reverse scan stage, T11 conducting when secondary signal input end INPUT2 input high level, keeping PD voltage node voltage is low level; T7 conducting when shift register cell signal output part output high level at the corresponding levels, keeping PD voltage node voltage is low level.
The shift register cell that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
In conjunction with Fig. 4 and Fig. 6, wherein Fig. 4 provides the function of two item scan shift register unit that time-state method (time-state method of CLK, CLKB, PU point and each signal end signal of OUTPUT when wherein Fig. 6 the is bilateral scanning) embodiment of the invention of the circuit diagram of two scan shift register circuit and two the scan shift registers unit that Fig. 6 provides provides and shift-register circuit specific implementation as follows:
During forward scan, in the t1 ' time period, second voltage end V2 input high level, tertiary voltage end V3 input low level, by first signal input end INPUT1 input high level, conducting T1 carries out precharge to C1, the T5 remain off and then so that PU point maintenance high level thereby the T6 conducting keeps PD point to be in low level; The t2 ' time period behind t1 ', the first clock signal clk is high level, second clock signal CLKB is low level, then C1 conducting T2 is so that signal output part OUTPUT signal is high level, the T5 remain off and then so that PU point maintenance high level thereby T7 conducting this moment keeps PD point to be in low level; The t3 ' time period behind t2 ', the first clock signal clk is low level, second clock signal CLKB is high level, conducting T3, T4 and T5, the PD point is high level, so that signal output part OUTPUT is low level, the PU point also is low level, and in time period t 3 ', by the 3rd signal input part INPUT3 input high level, by conducting T9 degrade signal output terminal OUTPUT signal; In non-working time, the first clock signal clk is high level at shift register cell, and second clock signal CLKB is low level, and without turn-on transistor, signal output part OUTPUT is low level.
During reverse scan, the input voltage of second voltage end V2 and tertiary voltage end V3 exchanges, the t1 ' time period by tertiary voltage end V3 input high level, second voltage end V2 input low level, by secondary signal input end INPUT2 input high level, conducting T8 carries out precharge to C1, the T5 remain off and then so that PU point maintenance high level thereby the T11 conducting keeps PD point to be in low level; The t2 ' time period behind t1 ', the first clock signal clk is high level, second clock signal CLKB is low level, then C1 conducting T2 is so that signal output part OUTPUT signal is high level, the T5 remain off and then so that PU point maintenance high level thereby T7 conducting this moment keeps PD point to be in low level; The t3 ' time period behind t2 ', the first clock signal clk is low level, second clock signal CLKB is high level, the signal of conducting T3 degrade signal output terminal OUTPUT, so that signal output part OUTPUT signal is low level, conducting T4 and T5 drag down PU voltage node voltage, and in time period t 3 ', by the 4th signal input part INPUT4 input high level, by conducting T10 degrade signal output terminal OUTPUT signal; In non-working time, the first clock signal clk is high level at shift register, and second clock signal CLKB is low level, and without turn-on transistor, signal output part OUTPUT is low level.Time-state method when wherein not providing reverse scan specifically can be with reference to the time-state method of forward scan.
The shift register cell that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
The invention provides a kind of gate driver circuit, comprise that series connection is a plurality of such as Fig. 1 or shift register cell shown in Figure 2, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input end of the next shift register cell that is adjacent.
Concrete, gate driver circuit is swept in individual event as shown in Figure 7, comprises several shift register cells, and wherein the output terminal OUTPUT of shift register cell SR0 connects the first signal input end INPUT1 of shift register cell SR1 and connects a grid line GL0; The output terminal OUTPUT of shift register cell SR1 connects the first signal input end INPUT1 of shift register cell SR2 and connects a grid line GL1; The output terminal OUTPUT of shift register cell SR2 connects the first signal input end INPUT1 of shift register cell SR3 and connects a grid line GL2, except first shift register cell and last shift register cell, other shift register cell links according to the method.The first signal input end INPUT1 of first shift register cell is at frame start signal STV of initial time input, and each shift register cell has the first clock signal terminal CLK input and a second clock signal end CLKB input; The clock signal of second clock signal end CLKB and the first clock signal terminal CLK has 180 degree phase differential, and the clock signal of the first clock signal terminal CLK and second clock signal end CLKB is half the time output high level within the work period separately all, second half time output low level; The clock signal of the first clock signal terminal CLK of two adjacent shift register cells has 180 degree phase differential in addition, and the clock signal of the second clock signal end CLKB of two adjacent shift register cells has 180 degree phase differential.
The gate driver circuit that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
Another kind of gate driver circuit provided by the invention, comprise series connection a plurality of such as Fig. 3 or the described shift register cell of Fig. 4 except first shift register cell and last shift register cell, all the other each shift register cell signal output parts also connect the secondary signal input end of a upper shift register cell that is adjacent, the signal output part of each shift register cell also connects the secondary signal input end of a upper shift register cell that is adjacent, except the first two shift register cell with latter two shift register cell, the signal output part of all the other each shift register cells also connect with its on the 3rd signal input part of adjacent second shift register cell and the lower neighbour's that is adjacent the 4th signal input part of second shift register cell.
Concrete, bilateral scanning gate driver circuit as shown in Figure 8, comprise several shift register cells, wherein, the signal output part OUTPUT of shift register cell SR0_1 connects the first signal input end INPUT1 of next shift register cell SR0_2 and the 4th signal input part INPUT4 and grid line G0_1 of lower two shift register cells; The signal output part OUTPUT of shift register cell SR0_2 connects the secondary signal input end INPUT2 of the first signal input end INPUT1 of next shift register cell SR1, a upper shift register cell and the 4th signal input part INPUT4 and grid line G0_2 of lower two shift register cells; The signal output part OUTPUT of shift register cell SR1 connects the secondary signal input end INPUT2 of the first signal input end INPUT1 of next shift register cell, a upper shift register cell SR0_2 and the 3rd signal input part INPUT3 and grid line G1 of the 4th signal input part INPUT4 of lower two shift register cells, upper two shift register cell SR0_1; Except the first two shift register cell with latter two shift register cell, other shift register cell connects according to shift register cell SR1, the signal input part of first shift register cell is at frame start signal STV of initial time input when forward scan, and the signal input part of last shift register cell is at frame start signal STV ' of initial time input when reverse scan; Each shift register cell has the first clock signal terminal CLK input and a second clock signal end CLKB input; The clock signal of second clock signal end CLKB and the first clock signal terminal CLK has 180 degree phase differential, and the clock signal of the first clock signal terminal CLK and second clock signal end CLKB is half the time output high level within the work period separately all, second half time output low level; The clock signal of the first clock signal terminal CLK of two adjacent shift register cells has 180 degree phase differential in addition, and the clock signal of the second clock signal end CLKB of two adjacent shift register cells has 180 degree phase differential.
The gate driver circuit that the embodiment of the invention provides can reduce signal wire integrated in the shifting deposit unit and the quantity of Thin Film Transistor (TFT), conserve space, and then reduce cost of products.
The embodiment of the invention also provides a kind of display device, such as being display panel, comprising:
The viewing area has for a plurality of pixels that show image; Gate driver circuit is used for sweep signal is delivered to the viewing area; And data drive circuit is used for data-signal is delivered to the viewing area.Wherein gate driver circuit is above-mentioned gate driver circuit.In addition, display device can also be Electronic Paper, mobile phone, TV, digital album (digital photo frame) etc. display device.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (8)
1. shift register cell, it is characterized in that, comprise: pre-charge module, signal output module, the drop-down module of output level, the first node voltage control module and the second node voltage control module, the first node is the tie point of described pre-charge module and signal output module, and the second node is the tie point of described the first node voltage control module and the second node voltage control module;
Wherein, described pre-charge module connects first signal input end and the first node, is used under the control of described first signal input end described signal output module precharge;
Described signal output module connects signal output part, described the first node and the first clock signal, is used for connecting under the control of described the first node voltage described the first clock signal and described signal output part;
The drop-down module of described output level connects described signal output part, second clock signal and the first voltage end, is used for connecting under the control of described second clock signal described signal output part and described the first voltage end;
Described the first node voltage control module connects second clock signal, described the first voltage end, described the first node and the second node, is used for connecting under the control of described second clock signal described the first node and described the first voltage end;
Described the second node voltage control module connects described first signal input end, described signal output part, described the first voltage end and described the second node, is used for control and connects described the second node and described the first voltage end.
2. shift register cell according to claim 1 is characterized in that,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor are connected described first signal input end with source electrode, the drain electrode of described the first transistor connects described the first node;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connect described the first node, and the source electrode of described transistor seconds connects described the first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
The first electric capacity, a utmost point of described the first electric capacity connects the grid of described transistor seconds, and another utmost point of described the first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of described output level comprises:
The 3rd transistor, the described the 3rd transistorized grid connects described second clock signal, and the described the 3rd transistorized source electrode connects described signal output part, and the described the 3rd transistorized drain electrode connects described the first voltage end;
Described the first node voltage control module comprises:
The 4th transistor, the described the 4th transistorized grid is connected described second clock signal with source electrode, and the described the 4th transistorized drain electrode connects described the second node;
The 5th transistor, the described the 5th transistorized grid connects described the second node, and the described the 5th transistorized source electrode connects described the first node, and the described the 5th transistorized drain electrode connects described the first voltage end;
The second node voltage control module comprises:
The 6th transistor, the described the 6th transistorized grid connects described first signal input end, and the described the 6th transistorized source electrode connects described the second node, and the described the 6th transistorized drain electrode connects described the first voltage end;
The 7th transistor, the described the 7th transistorized grid connects described signal output part, and the described the 7th transistorized source electrode connects described the second node, and the described the 7th transistorized drain electrode connects described the first voltage end.
3. shift register cell according to claim 1 is characterized in that,
Described pre-charge module also connects secondary signal input end, second voltage end and tertiary voltage end, being used at described second voltage end is that high level tertiary voltage end is when being low level, under the control of described first signal input end, to described signal output module precharge, under the control of described secondary signal input end, connect described the first node and described tertiary voltage end;
Perhaps described second voltage end is that low level tertiary voltage end is when being high level, under the control of described secondary signal input end, to described signal output module precharge, under the control of described first signal input end, connect described the first node and described second voltage end;
The drop-down module of described output level also connects the 3rd signal input part and the 4th signal input part, is used for connecting under the control of the 3rd signal input part or the 4th signal input part described signal output part and described the first voltage end;
Described the second node voltage control module also connects described secondary signal input end, is used for connecting under the control of described secondary signal input end described the second node and described the first voltage end.
4. shift register cell according to claim 3 is characterized in that,
Described pre-charge module comprises:
The first transistor, the grid of described the first transistor connect described first signal input end, and the source electrode of described the first transistor connects described second voltage end, and the drain electrode of described the first transistor connects described the first node;
The 8th transistor, the described the 8th transistorized grid connects described secondary signal input end, and the described the 8th transistorized source electrode connects described the first node, and the described the 8th transistorized drain electrode connects described tertiary voltage end;
Described signal output module comprises:
Transistor seconds, the grid of described transistor seconds connect described the first node, and the source electrode of described transistor seconds connects described the first clock signal, and the drain electrode of described transistor seconds connects described signal output part;
The first electric capacity, a utmost point of described the first electric capacity connects the grid of described transistor seconds, and another utmost point of described the first electric capacity connects the drain electrode of described transistor seconds;
The drop-down module of output level comprises:
The 3rd transistor, the described the 3rd transistorized grid connects described second clock signal, and the described the 3rd transistorized source electrode connects described signal output part, and the described the 3rd transistorized drain electrode connects described the first voltage end;
The 9th transistor, the described the 9th transistorized grid connects described the 3rd signal input part, and the described the 9th transistorized source electrode connects described signal output part, and the described the 9th transistorized drain electrode connects described the first voltage end;
The tenth transistor, the described the tenth transistorized grid connects described the 4th signal input part, and the described the tenth transistorized source electrode connects described signal output part, and the described the tenth transistorized drain electrode connects described the first voltage end;
The first node voltage control module comprises:
The 4th transistor, the described the 4th transistorized grid is connected described second clock signal with source electrode, and the described the 4th transistorized drain electrode connects described the second node;
The 5th transistor, the described the 5th transistorized grid connects described the second node, and the described the 5th transistorized source electrode connects described the first node, and the described the 5th transistorized drain electrode connects described the first voltage end;
The second node voltage control module comprises:
The 6th transistor, the described the 6th transistorized grid connects described first signal input end, and the described the 6th transistorized source electrode connects described the second node, and the described the 6th transistorized drain electrode connects described the first voltage end;
The 7th transistor, the described the 7th transistorized grid connects described output signal end, and the described the 7th transistorized source electrode connects described the second node, and the described the 7th transistorized drain electrode connects described the first voltage end.
The 11 transistor, the described the 11 transistorized grid connects described secondary signal input end, and the described the 11 transistorized source electrode connects described the second node, and the described the 11 transistorized drain electrode connects described the first voltage end.
5. according to claim 1 to 4 arbitrary described shift register cells, it is characterized in that described the first voltage end is earth terminal.
6. gate driver circuit, it is characterized in that, comprise a plurality of shift register cells as claimed in claim 1 or 2 of series connection, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input end of the next shift register cell that is adjacent.
7. gate driver circuit, it is characterized in that, comprise that series connection is a plurality of such as claim 3 or 4 described shift register cells, except first shift register cell and last shift register cell, the signal output part of all the other each shift register cells connects the first signal input end of the next shift register cell that is adjacent, the signal output part of each shift register cell also connects the secondary signal input end of a upper shift register cell that is adjacent, except the first two shift register cell with latter two shift register cell, the signal output part of all the other each shift register cells also connect with its on the 3rd signal input part of adjacent second shift register cell and the lower neighbour's that is adjacent the 4th signal input part of second shift register cell.
8. display device comprises:
The viewing area has for a plurality of pixels that show image;
Gate driver circuit is used for sweep signal is delivered to described viewing area;
Data drive circuit is used for data-signal is delivered to described viewing area;
It is characterized in that described gate driver circuit is claim 6 or 7 described arbitrary gate driver circuits.
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| CN108022560B (en) * | 2016-11-01 | 2023-10-10 | 合肥鑫晟光电科技有限公司 | Gate driving circuit and driving method thereof, display substrate and display device |
| WO2022089067A1 (en) * | 2020-10-26 | 2022-05-05 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method, gate driving circuit and display apparatus |
| US11830410B2 (en) | 2020-10-26 | 2023-11-28 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Gate driving unit, gate driving method, gate driving circuit and display device |
| CN114005398A (en) * | 2021-09-17 | 2022-02-01 | 友达光电股份有限公司 | Gate drive circuit |
| CN114005398B (en) * | 2021-09-17 | 2023-12-12 | 友达光电股份有限公司 | Gate driving circuit |
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| CN102903323B (en) | 2015-05-13 |
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