CN102683289B - Method for improving writing redundancy of static random access memory - Google Patents
Method for improving writing redundancy of static random access memory Download PDFInfo
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- CN102683289B CN102683289B CN201210136000.5A CN201210136000A CN102683289B CN 102683289 B CN102683289 B CN 102683289B CN 201210136000 A CN201210136000 A CN 201210136000A CN 102683289 B CN102683289 B CN 102683289B
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- 238000005516 engineering process Methods 0.000 claims abstract description 15
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
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Abstract
The invention discloses a method for improving writing redundancy of a static random access memory. The method includes that the static random access memory lining is provided. The lining comprises an N-channel metal oxide semiconductor (NMOS) area, a first P-channel metal oxide semiconductor area and a second PMOS area. The first NMOS area is used for preparing a common NMOS device, a control tube and a downward pull tube. The first PMOS area is used for preparing a common PMOS device. The second PMOS area is used for preparing an upward pull tube. A shallow-groove isolation area is formed among the NMOS area, the first PMOS area and the second PMOS area. Simultaneously, the local strain silicon technology is adopted on the NMOS area and the second PMOS area to enable the NMOS area and the second PMOS area to be located in an epitaxial silicon thin film on a germanium silicon virtual lining. The method reduces hole mobility ratio of the upward pull tube, increases equivalent resistance of the upward pull tube and improves writing redundancy of the random access memory.
Description
Technical field
The present invention relates to semiconductor preparing technical field, relate in particular to a kind of method that static random access memory writes redundancy that improves.
Background technology
Static random access memory (SRAM), as the class staple product in semiconductor memory, is widely used in the high speed data exchange systems such as computer, communication, multimedia.Shown in Fig. 1 is the domain structure of a common sram cell below 90 nanometers, include these three levels of source region, polysilicon gate and contact hole, what in figure, region 1 marked is control valve (Pass Gate), this device is a nmos device, what region 2 marked is lower trombone slide (Pull Down MOS), this device is similarly a nmos device, and what region 3 marked is upper trombone slide (Pull Up MOS), and this device is a PMOS device.
Writing redundancy (Write Margin) is an important parameter weighing sram cell write performance, Fig. 2 is that a SRAM device is being write fashionable work schematic diagram, in figure, 4 is control valve, 5 is lower trombone slide, 6 is upper trombone slide, suppose that node 7 storage data are electronegative potential (storing data for " 0 "), and it is corresponding, node 8 storage data are high potential (storing data for " 1 "), take now and write high potential and node 8 writes electronegative potential as example to node 7, before write activity, bit line 9 can be charged to high potential in advance, bit line 10 can be precharged to electronegative potential, when write activity starts, word line 11 is opened, because the data of node 7 initial storage are electronegative potential, so during initial condition, upper trombone slide 6 is opened and lower trombone slide 5 cuts out.Due to upper trombone slide 6 and control valve 4, all open, so the current potential of node 8 is no longer " 1 ", but be positioned at a certain intermediate potential.This intermediate potential is determined by the equivalent resistance of upper trombone slide 6 and control valve 4.In order to complete write activity, the intermediate potential of node 8 must be less than certain numerical value, control valve and 4 and the ratio of the equivalent resistance of upper trombone slide 6 must be less than certain numerical value, intermediate potential value is lower, sram cell to write redundancy just larger.If the equivalent resistance of trombone slide in increase, just can reduce the intermediate potential of node 8, thereby increase the redundancy that writes of sram cell.
Along with the progress of technology generations, particularly, in the following technology generations of 65 nanometer, can adopt local train silicon technology to prepare cmos device.Local train silicon technology refers to when preparing cmos device, for nmos device, its raceway groove can be positioned on SiGe virtual substrate among epitaxially grown silicon thin film, because the lattice constant of silicon is less than germanium silicon, therefore, on SiGe virtual substrate, among epitaxially grown silicon thin film, can have tensile stress, this tensile stress is useful to the electron mobility of raising nmos device.And for PMOS device, because the tensile stress in raceway groove can reduce the mobility in hole, so the raceway groove of PMOS device is still positioned among common body silicon, and can not adopt the method for SiGe virtual substrate ESF epitaxial silicon film.Owing to just adopting the method for ESF epitaxial silicon film on SiGe virtual substrate at the regional area of nmos device, be therefore called as local train silicon technology.Especially, for the upper trombone slide of SRAM, because it is also a PMOS device, so in common technique, as shown in Figure 3, the raceway groove of common PMOS device 6, upper trombone slide 6 ' is to be positioned among common body silicon 0.
Summary of the invention
Problem for above-mentioned existence, the object of this invention is to provide a kind of method that static random access memory writes redundancy that improves, tensile stress in trombone slide raceway groove is increased, thereby reduced upper trombone slide hole mobility, increased the equivalent resistance of upper trombone slide, improved random asccess memory and write redundancy.
The object of the invention is to be achieved through the following technical solutions:
Improve static random access memory and read a method for redundancy, wherein, comprise the following steps:
Static random access memory substrate is provided, on described substrate, comprise successively adjacent territory, nmos area, a PMOS region and the 2nd PMOS region, described the first territory, nmos area is for the preparation of common nmos device, control valve and lower trombone slide, a described PMOS region is for the preparation of common PMOS device, and described the 2nd PMOS region is for the preparation of upper trombone slide;
Between territory, described nmos area, a described PMOS region and described the 2nd PMOS region, form shallow trench isolation region;
Local train silicon technology is taked in territory, described nmos area and described the 2nd PMOS region simultaneously, territory, described nmos area and described the 2nd PMOS region are all positioned among the ESF epitaxial silicon film on SiGe virtual substrate.
Above-mentioned raising static random access memory is read the method for redundancy, wherein, in the manufacturing process that completes territory, described nmos area or a described PMOS region or described the 2nd PMOS region, be included in deposition of gate material on silicon thin film, etching forms grid and makes side wall.
Above-mentioned raising static random access memory is read the method for redundancy, and wherein, described deposition process adopts chemical gas-phase method.
Above-mentioned raising static random access memory is read the method for redundancy, and wherein, described etching adopts dry etching.
Above-mentioned raising static random access memory is read the method for redundancy, and wherein, described silicon thin film is silicon nitride or silica.
Above-mentioned raising static random access memory is read the method for redundancy, and wherein, described substrate is silicon substrate.
Compared with the prior art, beneficial effect of the present invention is:
1, do not increase existing processing step;
2, by logical operation (Logic Operation), when taking local train silicon technology with raising nmos device electron mobility, in the technical process of the local SiGe virtual substrate of preparation, trombone slide region is opened equally, final upper trombone slide is also positioned among the ESF epitaxial silicon film on SiGe virtual substrate, rather than as common PMOS device, be positioned among common aspect silicon, thereby increased the tensile stress among upper trombone slide raceway groove, reduce the carrier mobility of upper trombone slide device, increased the equivalent resistance of upper trombone slide;
3,, in ablation process, reduced the current potential of node 8, thereby improved the redundancy that writes of random asccess memory.
Accompanying drawing explanation
Fig. 1 is SRAM domain schematic diagram in prior art;
Fig. 2 is SRAM electrical block diagram in prior art.
Fig. 3 is the schematic cross-section of nmos device, PMOS device and upper trombone slide after local train silicon technology in prior art;
Fig. 4 is a kind of schematic cross-section that improves NMOS, PMOS and upper trombone slide in the method that static random access memory writes redundancy of the present invention.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment, the invention will be further described.
As shown in Figure 4, the present invention improves the method that static random access memory is read redundancy, and it comprises the following steps:
Static random access memory substrate 0 is provided, on substrate 0, comprise successively adjacent territory, nmos area 5, a PMOS region 6 and the 2nd PMOS region 6 ', the first territory, nmos area 5 is for the preparation of common nmos device, control valve and lower trombone slide, the one PMOS region 6 is for the preparation of common PMOS device, and described the 2nd PMOS region 6 ' is for the preparation of upper trombone slide;
Between territory, nmos area 5, a PMOS region 6 and the 2nd PMOS region 6 ', form respectively shallow trench isolation region (STI);
Local train silicon technology is taked in territory, nmos area 5 and the 2nd PMOS region 6 ' simultaneously, by logical operation (Logic Operation), when taking local train silicon technology with raising nmos device electron mobility, in the technical process of the local SiGe virtual substrate of preparation, trombone slide region is opened equally, finally make territory, nmos area 5 and the 2nd PMOS region 6 ' all be positioned at SiGe virtual substrate 00, ESF epitaxial silicon film 000 on 00 ', among 000 ', and a PMOS region 6 is still among body silicon 0, thereby increased the tensile stress among upper trombone slide raceway groove, reduced the carrier mobility of upper trombone slide device, increased the equivalent resistance of upper trombone slide, in ablation process, reduced the current potential of node 8, thereby improved the redundancy that writes of random asccess memory.Strained silicon is formed by epitaxial growth Si on the larger substrate of the atomic distances such as SiGe, the basic principle of its formation is to utilize a kind of cost method relatively low, can large-scale application to strengthen silicon atom spacing, thereby reduce the current suffered obstruction of electronics, also be just equivalent to reduce resistance, therefore caloric value and energy consumption all can reduce, and the speed of service is promoted.
Preferably, in the manufacturing process that completes territory, nmos area 5 or a PMOS region 6 or the 2nd PMOS region 6 ', be included in deposition of gate material on silicon thin film, etching forms grid and makes side wall.
Preferably, deposition process adopts chemical gas-phase method, and etching adopts dry etching.
Further, silicon thin film is silicon nitride or silica, and substrate is silicon substrate.
The present invention can be applicable in 45nm static random access memory preparation technology, to improve it, writes redundancy.
To sum up, the present invention is by logical operation (Logic Operation), when taking local train silicon technology with raising nmos device electron mobility, in the technical process of the local SiGe virtual substrate of preparation, trombone slide region is opened equally, final upper trombone slide is also positioned among the ESF epitaxial silicon film on SiGe virtual substrate, rather than as common PMOS device, be positioned among common aspect silicon, thereby increased the tensile stress among upper trombone slide raceway groove, reduce the carrier mobility of upper trombone slide device, increased the equivalent resistance of upper trombone slide.
Above specific embodiments of the invention be have been described in detail, but the present invention is not restricted to specific embodiment described above, it is just as example.To those skilled in the art, any equivalent modifications and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (6)
1. improve the method that static random access memory writes redundancy, it is characterized in that, comprise the following steps:
Static random access memory substrate is provided, on described substrate, comprise successively adjacent territory, nmos area, a PMOS region and the 2nd PMOS region, territory, described nmos area is for the preparation of common nmos device, control valve and lower trombone slide, a described PMOS region is for the preparation of common PMOS device, and described the 2nd PMOS region is for the preparation of upper trombone slide;
Between territory, described nmos area, a described PMOS region and described the 2nd PMOS region, form shallow trench isolation region;
Local train silicon technology is taked in territory, described nmos area and described the 2nd PMOS region simultaneously, territory, described nmos area and described the 2nd PMOS region are all positioned among the ESF epitaxial silicon film on SiGe virtual substrate.
2. raising static random access memory as claimed in claim 1 writes the method for redundancy, it is characterized in that, in the manufacturing process that completes territory, described nmos area or a described PMOS region or described the 2nd PMOS region, be included in deposition of gate material on silicon thin film, etching forms grid and makes side wall.
3. raising static random access memory as claimed in claim 2 writes the method for redundancy, it is characterized in that, described deposition process adopts chemical gas-phase method.
4. raising static random access memory as claimed in claim 2 writes the method for redundancy, it is characterized in that, described etching adopts dry etching.
5. raising static random access memory as claimed in claim 2 writes the method for redundancy, it is characterized in that, described silicon thin film is silicon nitride or silica.
6. raising static random access memory as claimed in claim 1 writes the method for redundancy, it is characterized in that, described substrate is silicon substrate.
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