CN102364687A - Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground - Google Patents
Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground Download PDFInfo
- Publication number
- CN102364687A CN102364687A CN2011103435849A CN201110343584A CN102364687A CN 102364687 A CN102364687 A CN 102364687A CN 2011103435849 A CN2011103435849 A CN 2011103435849A CN 201110343584 A CN201110343584 A CN 201110343584A CN 102364687 A CN102364687 A CN 102364687A
- Authority
- CN
- China
- Prior art keywords
- soi
- ground
- type diffusion
- diffusion region
- protection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to an electrostatic discharge (ESD) protection structure between a silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground. The ESD protection structure comprises a SOI base plate. The SOI substrate comprises a silicon film. An active region is arranged on the silicon film. An isolation region is arranged on an outer ring of the active region. The active region comprises a first conductive type diffusion area. The outer ring of the first conductive type diffusion area is provided with a first conductive type substrate. The outer ring of the first conductive type substrate is provided with a second conductive type diffusion area. A gate oxide is arranged above the first conductive type substrate. A polysilicon gate is arranged on the gate oxide. The polysilicon gate is in an annular shape. A structure is simple. Technology steps are compatible with a traditional SOI technology and are easy to be realized. A N-type gate control diode structure which is optimized on the technology and a layout is used so as to improve a tolerance level of the ESD between the SOI/CMOS integrated circuit power supply and the ground.
Description
Technical field
The present invention relates to a kind of esd protection structure, the esd protection structure between especially a kind of SOI/CMOS ic power and the ground belongs to the technical field of esd protection on the integrated circuit.
Background technology
The full dielectric isolation of element has thoroughly been eliminated the latch-up of body silicon circuit in the SOI/CMOS integrated circuit; Have advantages such as parasitic capacitance is little, speed is high, integrated level is high, operating temperature range is wide, anti-irradiation ability is strong simultaneously, make it in the large scale integrated circuit of space radiation environment electronic system, intense radiation environment strategy weapon, obtain emphasis and use.But static discharge (ESD, Electrostatic discharge) is a principal element that influences the SOI/CMOS IC reliability.Because material, the technology of preparation SOI/CMOS integrated circuit are different with the body silicon circuit; The silicon fiml of SOI (Silicon-on-Insulator) material is very thin; The lower thermal conductivity of SOI device oxygen buried layer (than little two one magnitude of silicon) has influenced the heat radiation of protection device; Make its ESD dissipation of energy ability very low, be merely 1% of body silicon circuit savings.Therefore, comparing the body silicon circuit based on the ESD Circuits Design for High of the integrated circuit of SOI/CMOS technology processing more is difficult to realize that this is the major reason that SOI/CMOS circuit ESD level is difficult to improve.
In prior art; Between power supply and ground, adopt the SOI diode to be connected; Utilize the reverse bias conducting of SOI diode under the ESD stress condition that the path of releasing of electrostatic induced current is provided, thereby the source end and the drain terminal that play metal-oxide-semiconductor among the SOI are tied not by the effect of ESD stress damage.But in real world applications, the reverse breakdown voltage (V of SOI diode
B) near in addition be higher than the junction breakdown voltage of SOI device; Junction breakdown has taken place in SOI device that tend to take place inside circuit under the stress condition of ESD; The SOI diode finally causes circuit to increase sharply to tens mA magnitudes from μ A magnitude according to the chip quiescent current because reverse breakdown voltage is crossed nobleness and do not started working, and inside is damaged by ESD; Disabler, but the normal failure mode of port lost efficacy.So need adjust to prior art.
Summary of the invention
The objective of the invention is to overcome the deficiency that exists in the prior art, the esd protection structure between a kind of SOI/CMOS ic power and the ground is provided, its compact conformation, prepared is simple, has improved the esd protection ability, and applicability is wide, and is safe and reliable.
According to technical scheme provided by the invention, the esd protection structure between said SOI/CMOS ic power and the ground comprises the SOI substrate, and said SOI substrate comprises silicon fiml; Said silicon fiml is provided with the source region, and the outer ring of said active area is provided with isolated area; Said active area comprises the first conduction type diffusion region, and the outer ring of the said first conduction type diffusion region is provided with first conductivity type substrate, and the outer ring of said first conductivity type substrate is provided with the second conduction type diffusion region; The top of said first conductivity type substrate is provided with gate oxide, and said gate oxide is provided with polysilicon gate, and said polysilicon gate ringwise.
The isolated area of outer ring, the said second conduction type diffusion region is a silicon dioxide.The girth of said polysilicon gate is greater than 2500 microns.
Said SOI substrate also comprises the oxygen buried layer that is positioned at the silicon fiml below and is positioned at the substrate of said oxygen buried layer below.Said polysilicon gate is connected with the first conduction type diffusion region equipotential.
Be provided with the first active area contact hole in the said first conduction type diffusion region, be provided with first metal connecting line that is used for the electrical connection of the first conduction type diffusion region in the said first active area contact hole.
Be provided with the second active area contact hole in the said second conduction type diffusion region, be provided with second metal connecting line that is used for the electrical connection of the second conduction type diffusion region in the said second active area contact hole.
Advantage of the present invention: simple in structure, processing step and traditional SOI process compatible; Realize easily; Used N-type gate control diode structure through technology and diagram optimizing; Can improve the ESD tolerance level between SOI/CMOS ic power and the ground; Can the ESD tolerance level between SOI/CMOS ic power and the ground be increased to 2000 volts on HBM model or above level after the use, and the SOI/CMOS ic power and the ESD tolerance level between the ground that do not use this esd protection structure are only on about 500 volts on HBM model.
Description of drawings
Fig. 1 is the structural representation of plane of the present invention domain.
Fig. 2 is a vertical structure sketch map of the present invention.
Fig. 3 is the electrology characteristic sketch map during for diode reverse breakdown of the present invention.
Electrology characteristic sketch map during diode reverse breakdown when Fig. 4 protects structure for not using the present invention.
Fig. 5 is the schematic diagram of the present invention's user mode in the SOI/CMOS circuit.
Description of reference numerals: 1-polysilicon gate, the 2-first conduction type diffusion region, the 3-second conduction type diffusion region, 4-isolated area, the 5-second active area contact hole, 6-adjustment window, the 7-first active area contact hole, 8-substrate, 9-oxygen buried layer and 10-first conductivity type substrate.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the present invention is described further.
As depicted in figs. 1 and 2: said esd protection structure comprises the SOI substrate, and said SOI substrate comprises substrate 8, and said substrate 8 is provided with oxygen buried layer 9, and said oxygen buried layer 9 is provided with silicon fiml.Be used to form the active area of ESD structure on the said silicon fiml, the outer ring of said active area is provided with isolated area 4, and said isolated area 4 is a silicon dioxide.Said active area comprises the first conduction type diffusion region 2; The outer ring of the said first conduction type diffusion region 2 is provided with first conductivity type substrate 10; The outer ring of said first conductivity type substrate 10 is provided with the second conduction type diffusion region 3, and 10 of the said second conduction type diffusion region 3 and first conductivity type substrate form the PN junction structure.Among Fig. 1 of the present invention and Fig. 2, first conduction type is the N type, and second conduction type is the P type, and therefore, the first conduction type diffusion region 2 is the N+ diffusion region, and first conductivity type substrate 10 is the N-substrate, and the second conduction type diffusion region 3 is the P+ diffusion region; Certainly, first conduction type also can be the P type, and second conduction type is the N type.Above first conductivity type substrate 10, be provided with polysilicon gate 1, between said polysilicon gate 1 below and silicon fiml gate oxide be set.Said polysilicon gate 1 ringwise; Thereby the first conduction type diffusion region 2 is positioned at the zone that polysilicon gate 1 annular comprises; The second conduction type diffusion region 3 is positioned at outside the zone that polysilicon gate 1 annular comprises, the first conduction type diffusion region 2 and the second conduction type diffusion region 3 are all through injecting corresponding conductive type ion.Be provided with the first active area contact hole 7 in the first conduction type diffusion region 2, be provided with first metal connecting line that is used for 2 electrical connections of the first conduction type diffusion region in the said first active area contact hole 7.Be provided with the second active area contact hole 5 in the second conduction type diffusion region 3, be provided with second metal connecting line that is used for 3 electrical connections of the second conduction type diffusion region in the said second active area contact hole 5.Adjustment window 6 is used for before forming polysilicon gate 1, first conductivity type substrate 10 of polysilicon gate 1 below being carried out concentration adjustment, to improve the esd protection ability between circuit power and the ground.Polysilicon gate 1 is structure ringwise, and the girth of polysilicon gate 1 is greater than 2500 microns.
The second conduction type diffusion region 3 is electrically connected, and links to each other, polysilicon gate 1 is connected with the first conduction type diffusion region, 2 equipotentials, connect high level VDD, finally form the esd protection structure N-type gate control diode between power supply and the ground with ground level VSS.
Forming process of the present invention is following: at first, on substrate 8, forming oxygen buried layer 9, is SOI nmosfet formation region, i.e. active area on the oxygen buried layer 9.In the middle of on the oxygen buried layer 9 is N+ diffusion region 2.Zone 10 is a device N-substrate, and 10 of P+ diffusion region 3 and N-substrates have formed PN junction.In order to reduce the puncture voltage of diode, before forming zone 7, through a process means and a newly-increased processing step N-substrate 10 is carried out substrate concentration and regulate.Zone 8 is linked to each other, connect ground level VSS, zone 7, zone 9 are linked to each other, connect power supply high level VDD, finally form the esd protection structure N-type gate control diode between power supply and the ground.
The electrology characteristic of Fig. 3 during for the gate control diode reverse breakdown that uses the present invention and form, after optimizing through process means, its puncture voltage (V
B) be about 9 volts, thermal breakdown electric current (I
T2) be about 3.2 amperes, device leakage electric current (I
Leakage) for receiving the peace magnitude, internal resistance (R during reverse breakdown work
On) be about 4.5 ohm.Because its reverse breakdown voltage is lower; Internal resistance is very little; Super large static discharge current between power supply and the ground is released very soon, thereby improve the ESD tolerance level between SOI/CMOS ic power and the ground, make it reach 2000 volts on HBM model or above level.
The electrology characteristic of Fig. 4 when not using the gate control diode reverse breakdown that the present invention forms, its puncture voltage (V
B) be about 13 volts, thermal breakdown electric current (I
T2) be about 2.2 amperes, device leakage electric current (I
Leakage) for receiving the peace magnitude, internal resistance (R during reverse breakdown work
On) be about 50 ohm.Compare with the diode characteristic after the optimization of process process means, its reverse breakdown voltage point is too high, and internal resistance is excessive; May cause the SOI device of circuit that junction breakdown has taken place under the stress condition of ESD; And SOI protection device is a diode because reverse breakdown voltage is crossed nobleness and do not started working, finally cause circuit according to quiescent current from the surge of microampere magnitude to tens milliamperes of magnitudes, innerly damaged by the super large static discharge current; Disabler, but the still normal failure mode of port lost efficacy.Adopt the gate control diode of this specific character, the ESD tolerance level between SOI/CMOS ic power and the ground is easily in about 500 volts on HBM model even following level.
Fig. 5 is the application sketch map of the present invention's invention in the SOI/CMOS circuit.At input port, the input pressure welding point links to each other with the input of driver, and the input of driver links to each other through esd protection structure territory VDD pressure welding point, VSS pressure welding point respectively corresponding to an end that links to each other with the input pressure welding point, forms input protection structure.Output end of driver links to each other with power supply-ground esd protection structure; Said power supply-ground esd protection structure has internal circuit; Said internal circuit is parallel with the gate control diode that some the present invention form; The second conduction type diffusion region 3 of said gate control diode links to each other with the VSS pressure welding point, and the polysilicon gate 1 of gate control diode and the first conduction type diffusion region 2 link to each other with the VDD pressure welding point.The output of internal circuit links to each other with the prime driver of output port, and the power end of said prime driver links to each other with VDD pressure welding point, VSS pressure welding point respectively.The prime output end of driver links to each other with the gate terminal of PMOS pipe, the gate terminal of NMOS pipe; The source terminal of PMOS pipe links to each other with the VDD pressure welding point; The source terminal of NMOS pipe links to each other with the VSS pressure welding point, and the drain electrode end of PMOS pipe links to each other with the drain electrode end of NMOS pipe, and links to each other with the output pressure welding point; The drain electrode end of the drain electrode end of PMOS pipe and NMOS pipe links to each other with VDD pressure welding point, VSS pressure welding point respectively through corresponding esd protection structure.Input signal through the input port esd protection structure, is connected to enter drive by the input pressure welding point.The electric power network that between the internal electric source of chip and ground, forms is inner, puts the protection structures that the present invention of many group parallel connections form in the internal circuit spare bits, further reduces internal resistance, and increase diode girth plays the effect of effective protection internal circuit.At output port, internal signal exports the output pressure welding point through the prime driver to through export structure.Between this export structure and output pressure welding point, also be provided with the output port esd protection structure.
Like Fig. 1～shown in Figure 5: during work; When polysilicon gate 1 and the first conduction type diffusion region 2 that the present invention forms esd protection structure add on the VDD pin; Utilize the reverse breakdown voltage that obtains after optimizing to be lower than the N-type gate control diode of junction breakdown voltage; Make it get into rapidly the reverse breakdown service area, moment super large static discharge current self is flow through from it, from the VSS pin chip of releasing out.Because structure provides polysilicon gate 1 girth and very low conducting resistance greater than 2500 microns; Avoided of the impact of ESD stress to inner small size device drain terminal knot; Thereby avoided of the damage of ESD stress, improved the ESD tolerance level between circuit power and the ground inside chip.
The present invention's advantage compared with prior art: simple in structure, processing step and traditional SOI process compatible; Realize easily; Used N-type gate control diode structure through technology and diagram optimizing; Can improve the ESD tolerance level between SOI/CMOS ic power and the ground; Can the ESD tolerance level between SOI/CMOS ic power and the ground be increased to 2000 volts on HBM model or above level after the use, and the SOI/CMOS ic power and the ESD tolerance level between the ground that do not use this esd protection structure are only on about 500 volts on HBM model.
Claims (7)
1. the esd protection structure between SOI/CMOS ic power and the ground comprises the SOI substrate, and said SOI substrate comprises silicon fiml; Said silicon fiml is provided with the source region, and the outer ring of said active area is provided with isolated area (4); It is characterized in that: said active area comprises the first conduction type diffusion region (2); The outer ring of the said first conduction type diffusion region (2) is provided with first conductivity type substrate (10), and the outer ring of said first conductivity type substrate (10) is provided with the second conduction type diffusion region (3); The top of said first conductivity type substrate (10) is provided with gate oxide, and said gate oxide is provided with polysilicon gate (1), and said polysilicon gate (1) ringwise.
2. the esd protection structure between SOI/CMOS ic power according to claim 1 and the ground is characterized in that: the isolated area (4) of outer ring, the said second conduction type diffusion region (3) is a silicon dioxide.
3. the esd protection structure between SOI/CMOS ic power according to claim 1 and the ground is characterized in that: the girth of said polysilicon gate (1) is greater than 2500 microns.
4. the esd protection structure between SOI/CMOS ic power according to claim 1 and the ground is characterized in that: said SOI substrate also comprises oxygen buried layer (9) that is positioned at the silicon fiml below and the substrate (8) that is positioned at said oxygen buried layer (9) below.
5. the esd protection structure between SOI/CMOS ic power according to claim 1 and the ground is characterized in that: said polysilicon gate (1) is connected with first conduction type diffusion region (9) equipotential.
6. the esd protection structure between SOI/CMOS ic power according to claim 1 and the ground; It is characterized in that: be provided with the first active area contact hole (7) in the said first conduction type diffusion region (2), be provided with first metal connecting line that is used for the electrical connection of the first conduction type diffusion region (2) in the said first active area contact hole (7).
7. the esd protection structure between SOI/CMOS ic power according to claim 1 and the ground; It is characterized in that: be provided with the second active area contact hole (5) in the said second conduction type diffusion region (3), be provided with second metal connecting line that is used for the electrical connection of the second conduction type diffusion region (3) in the said second active area contact hole (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103435849A CN102364687A (en) | 2011-11-03 | 2011-11-03 | Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103435849A CN102364687A (en) | 2011-11-03 | 2011-11-03 | Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102364687A true CN102364687A (en) | 2012-02-29 |
Family
ID=45691245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103435849A Pending CN102364687A (en) | 2011-11-03 | 2011-11-03 | Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102364687A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779819A (en) * | 2012-08-17 | 2012-11-14 | 中国电子科技集团公司第五十八研究所 | ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process |
| CN111900158A (en) * | 2020-08-07 | 2020-11-06 | 深圳市中明科技股份有限公司 | Method for ESD protection of integrated circuit |
| CN113611744A (en) * | 2021-07-07 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection MOS structure suitable for SOI type |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
| US20050007216A1 (en) * | 2003-06-30 | 2005-01-13 | Baldwin David John | MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication |
| CN101355357A (en) * | 2008-09-04 | 2009-01-28 | 中国电子科技集团公司第五十八研究所 | ESD protection structure for output buffer of SOI/CMOS integrated circuit |
| CN102082144A (en) * | 2010-11-04 | 2011-06-01 | 中国科学院上海微系统与信息技术研究所 | Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof |
| CN202394973U (en) * | 2011-11-03 | 2012-08-22 | 中国电子科技集团公司第五十八研究所 | ESD protective structure between SOI/CMOS integrated circuit power and ground |
-
2011
- 2011-11-03 CN CN2011103435849A patent/CN102364687A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5714784A (en) * | 1995-10-19 | 1998-02-03 | Winbond Electronics Corporation | Electrostatic discharge protection device |
| US20050007216A1 (en) * | 2003-06-30 | 2005-01-13 | Baldwin David John | MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication |
| CN101355357A (en) * | 2008-09-04 | 2009-01-28 | 中国电子科技集团公司第五十八研究所 | ESD protection structure for output buffer of SOI/CMOS integrated circuit |
| CN102082144A (en) * | 2010-11-04 | 2011-06-01 | 中国科学院上海微系统与信息技术研究所 | Electro-static discharge (ESD) protection structure in silicon-on-insulator (SOI) circuit and manufacturing method thereof |
| CN202394973U (en) * | 2011-11-03 | 2012-08-22 | 中国电子科技集团公司第五十八研究所 | ESD protective structure between SOI/CMOS integrated circuit power and ground |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779819A (en) * | 2012-08-17 | 2012-11-14 | 中国电子科技集团公司第五十八研究所 | ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process |
| CN102779819B (en) * | 2012-08-17 | 2014-12-03 | 中国电子科技集团公司第五十八研究所 | ESD (Electronic Static Discharge) protection structure based on partial depletion mode SOI (Silicon on Insulator) process |
| CN111900158A (en) * | 2020-08-07 | 2020-11-06 | 深圳市中明科技股份有限公司 | Method for ESD protection of integrated circuit |
| CN111900158B (en) * | 2020-08-07 | 2024-02-20 | 深圳市中明科技股份有限公司 | Method for ESD protection of integrated circuit |
| CN113611744A (en) * | 2021-07-07 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection MOS structure suitable for SOI type |
| CN113611744B (en) * | 2021-07-07 | 2024-01-19 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection MOS structure suitable for SOI |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102714205B (en) | There is the bond pad of integrated transient overvoltage protection | |
| US10510744B2 (en) | Vertical nanowire transistor for input/output structure | |
| TW504828B (en) | Bi-directional electrical overstress and electrostatic discharge protection apparatus | |
| CN101283452B (en) | Electrostatic discharge protection device | |
| CN102738782B (en) | The esd protection circuit of semiconductor integrated circuit | |
| CN103633087B (en) | A kind of strong anti-breech lock controlled LIGBT device with ESD defencive function | |
| CN101630673B (en) | Esd protection structures on soi substrates | |
| CN101290933A (en) | Electrostatic discharge protection device | |
| CN102544115B (en) | ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier) | |
| CN102254912B (en) | Controlled silicon device under auxiliary trigger of embedded P-type MOS (Metal Oxide Semiconductor) transistor | |
| CN202394973U (en) | ESD protective structure between SOI/CMOS integrated circuit power and ground | |
| CN102142440A (en) | Thyristor device | |
| KR20080076403A (en) | Electrostatic discharge protection element | |
| CN100364093C (en) | High-voltage electrostatic discharging protector with gap structure | |
| CN104409454A (en) | NLDMOS anti-static protection tube | |
| CN112599522A (en) | Quick-opening uniform-conduction bidirectional electrostatic surge protection IC | |
| CN102364687A (en) | Electrostatic discharge (ESD) protection structure between silicon-on-insulator (SOI)/CMOS integrated circuit power supply and ground | |
| CN101355357A (en) | ESD protection structure for output buffer of SOI/CMOS integrated circuit | |
| CN104979805A (en) | Bidirectional static protection circuit and battery protection circuit thereof | |
| CN102544068B (en) | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes | |
| US8941959B2 (en) | ESD protection apparatus | |
| CN103872039B (en) | The manufacture method of ESD protection circuit | |
| TWI482259B (en) | Integrated circuit having a charged-device model electrostatic discharge protection mechanism | |
| CN105405843B (en) | Electrostatic discharge protective circuit | |
| CN110047828A (en) | A kind of RC coupling triggering bidirectional transient voltage suppressor based on SOI technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120229 |