CN102360564B

CN102360564B - Twin transistor memory

Info

Publication number: CN102360564B
Application number: CN 201110285756
Authority: CN
Inventors: 陈静; 余涛; 罗杰馨; 伍青青; 柴展
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2011-09-23
Filing date: 2011-09-23
Publication date: 2013-04-10
Anticipated expiration: 2031-09-23
Also published as: CN102360564A

Abstract

The invention provides a twin transistor memory which comprises an I-MOS (Impact-Ionization Metal Oxide Semiconductor) transistor and an MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), wherein the grid electrode of the I-MOS transistor is connected with a word line, the drain electrode of the I-MOS transistor is connected with a first bit line, the grid electrode of the MOSFET is connected with the source electrode of the I-MOS transistor, the drain electrode of the MOSFET is connected with a second bit line, and the source electrode of the MOSFET is grounded. In the invention, the twin transistor memory composed of the I-MOS transistor and the MOSFET not only has very high switching speed but also can effectively avoid the influence of the GIDL (Gate Induced Drain Leakage) current in a '0' state, thereby prolonging the '0' state retention time.

Description

Twin transistor memory

Technical field

The present invention relates to microelectronics and solid state electronics technical field, particularly relate to a kind of novel high-density without electric capacity TTRAM twin transistor memory.

Background technology

Tradition DRAM storage unit comprises a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and a mos capacitance (being 1T1C).Wherein, MOSFET is equivalent to a switch, is used for the operation that the control store unit writes, upgrades and read, and the mos capacitance device is then as the usefulness of charge storage.In actual applications, the electric charge that is stored on the capacitor can run off gradually, so the work of DRAM is " dynamically ", need do periodically and refresh.According to the mole theorem, as long as DIY hardware is updating, memory standards also will constantly substitute, and the size of capacitor and coupling will seriously hinder the further reduction of memory cell area among traditional DRAM.Therefore, people propose to utilize the intrinsic floater effect of SOI MOSFET to realize the concept of dynamic storage cell.

In the storer family based on float structure (FBC), two large typical structure types are arranged.A kind ofly be: the Z-RAM that was created out by Switzerland Innovative Silicon company in 2002 (Zero capacitor RAM) technology, it is not to adopt the electric charge that is stored in the capacitor to come expression information, stores data but catch electric charge by the DRAM unit that adopts this technology under the raceway groove of a traditional Silicon-On-Insulator (SOI) MOSFET.This Z-RAM technology based on float structure (FBC) is to adopt single-transistor (1T) structure.Therefore, it can have the access speed of nearly SRAM and the memory density that surpasses traditional DRAM.Another type is: 2005, Japanese Renesas company proposed the concept of TTRAM, and it is in series by two identical PD-SOI N-shaped MOSFET.Last transistor plays read/write function, and a rear transistor is storage unit.Its advantage is: (1) fully with CMOS process compatible, though cellar area than Z-RAM (1T) structure greatly, but less than the storage unit of traditional 1T1C.(2) operating voltage is fully compatible mutually with the voltage of CMOS logical circuit, and different from the Z-RAM single-transistor is (at least 3 kinds of operating voltages), and TTRAM only needs VDD, VDD/2 and 0 three kinds of voltages, has reduced the requirement to peripheral circuit.(3) retention time (retention time) of TTRAM storage unit differentiation " 0 " and one state will be longer than the Z-RAM unit.

Wherein, the retention time is important index of DRAM storage unit.Retention time can be distinguished " 0 " and the longest time of one writing state exactly, also can think the refresh time that storage unit is the longest.Since different in the biasing that keeps the attitude bit line, can cause the retention time of " 0 " and " 1 " to have a strong impact on.For example " 0 " has write the floater effect unit, then enter hold mode, if again to carry out the one writing operation with array storage unit, bit line will certainly be biased to higher positive voltage, because the public bit line of same column, so be in the bit line of storage unit of maintenance " 0 " state also for just, like this can anti-partially tagma to the P-N knot of drain electrode, produce reverse leakage.Can produce the GIDL effect in addition, described GIDL effect refers to: grid adds negative bias, forms accumulation layer in channel surface, simultaneously drain electrode adds positive voltage, can occur exhausting in the overlapping region of grid and drain electrode, finally form inversion layer, the result causes band to band tunneling tunnelling.Like this, the electrons in tagma is tunneling to drain electrode, stays the hole in the tagma, finally causes keeping " 0 " attitude to have a strong impact on.In other words because the existence of GIDL electric current, meeting so that the tagma constantly charge, thereby changed " 0 " state, the retention time of state is in worst case that Here it is " 0 ".

Summary of the invention

The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of twin transistor memory, so that it not only has very fast switching speed, and GIDL the influence of peak current can effectively avoid " 0 " state the time, thereby improve " 0 " attitude retention time.

Reach for achieving the above object other relevant purposes, the invention provides a kind of twin transistor memory, it is characterized in that, comprise: the I-MOS pipe, has buried insulator layer, be positioned at the semiconductor layer on the described buried insulator layer, described semiconductor layer comprises the first source region, the first drain region and the intrinsic region between described the first source region and the first drain region, and the first source electrode that is positioned at corresponding described the first source region on the described semiconductor layer, first drain electrode in corresponding described the first drain region, and between described the first source electrode and the first drain electrode and the first grid insulation course of corresponding described intrinsic region, one side of described first grid insulation course upper surface is stacking first grid, described first grid is connected with the word line, and described the first drain electrode is connected with the first bit line; And MOSFET pipe, have substrate, be formed with the second source region in described substrate one side, be formed with the second drain region at the opposite side of described substrate, at the second drain electrode and the second gate insulation course between described the second source electrode drains with second in second source electrode in corresponding described the second source region on the described substrate, corresponding described the second drain region, stacking on the described second gate insulation course have a second grid, described second grid connects described the first source electrode, described the second drain electrode is connected with the second bit line, described the second source ground.

Twin transistor memory of the present invention wherein, comprises effective channel region in the intrinsic region of described I-MOS pipe, the width of described effective channel region changes with the grid voltage size that applies on the described first grid.Described I-MOS pipe is P type raceway groove I-MOS pipe.

Twin transistor memory of the present invention, wherein, described MOSFET pipe is enhancement mode MOSFET pipe, perhaps is depletion type MOS FET pipe.

As mentioned above, twin transistor memory of the present invention and the structural difference of traditional TTRAM are: the T1 pipe adopts I-MOS structure (Impact-Ionization MOS), and the T2 pipe is normal MOSFET.Its advantage is: not only have very fast switching speed, this can implement quick conversion to the writing of " 0 " and one state, maintenance, read states.And GIDL the influence of peak current can effectively avoid " 0 " state the time, thereby improve " 0 " attitude retention time.

Description of drawings

Fig. 1 is shown as twin transistor memory of the present invention and forms structural representation.

Fig. 2 is shown as the I-MOS tubular construction synoptic diagram in the twin transistor memory of the present invention.

When being shown as I-MOS of the present invention pipe OFF state, Fig. 3 a can be with synoptic diagram.

When being shown as I-MOS of the present invention pipe ON state, Fig. 3 b can be with synoptic diagram.

Fig. 4 is shown as the P-N knot synoptic diagram in the avalanche multiplication mechanism.

Embodiment

Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.

See also Fig. 1 to Fig. 4, need to prove, the diagram that provides in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and size drafting when implementing according to reality, kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also may be more complicated.

See also Fig. 1, Fig. 1 is shown as twin transistor memory of the present invention and forms structural representation, as shown in the figure, the invention provides a kind of twin transistor memory 1, comprise I-MOS pipe 11 and MOSFET pipe 12, wherein, the grid connective word line WL of described I-MOS pipe 11, the drain electrode of described I-MOS pipe 11 is connected with the first bit line BL1, the grid of described MOSFET pipe 12 connects the source electrode of described I-MOS pipe 11, the drain electrode of described MOSFET pipe 12 is connected with the second bit line BL2, the source ground of described MOSFET pipe 12.In present embodiment, described I-MOS pipe 11 is P type raceway groove I-MOS pipe.So be not limited to this, described I-MOS pipe 11 also can be N-type raceway groove I-MOS pipe.Described MOSFET pipe 12 is enhancement mode MOSFET pipe, perhaps is depletion type MOS FET pipe.

See also Fig. 2, be shown as the I-MOS tubular construction synoptic diagram in the twin transistor memory of the present invention, as shown in the figure, described I-MOS pipe 11 has buried insulator layer 111, be positioned at the semiconductor layer (not indicating) on the described buried insulator layer 111, described semiconductor layer comprises the first source region 112, the first drain region 113 and the intrinsic region 114 between described the first source region 112 and the first drain region 113, and the first source electrode 115 that is positioned at corresponding described the first source region 112 on the described semiconductor layer, first drain electrode 116 in corresponding described the first drain region 113, and drain between 116 and the first grid insulation course 117 of corresponding described intrinsic region 114 at described the first source electrode 115 and first, one side of described first grid insulation course 117 upper surfaces is stacking first grid 118, particularly, the area that described first grid 118 is laid is less than the area of described first grid insulation course 117, so that described first grid 118 is overlapping with the channel part of below, in other words, reserve Overlap at described first grid insulation course 117.Wherein, comprise effective channel region in the intrinsic region 114 of described I-MOS pipe 11, the width of described effective channel region changes with the grid voltage size that applies on the described first grid 118.

Described I-MOS pipe 11 is by the adjusting of utilization to length of effective channel, and then the transverse electric field of control intrinsic region 114 is controlled a kind of gate control diode of open and close attitude.Adopting the P-I-N knot is in order to obtain lower avalanche breakdown field intensity, and this is that electric field required during puncture is larger because the depletion widths of P-N knot is very narrow.In addition, when electronics obtains atomic time of enough kinetic collision intrinsic regions 114 from electric field, intrinsic region 114 can obtain more electron-hole pair.The unique texture of described I-MOS pipe 11, namely first grid 118 not all with the ditch trace overlap, can effectively avoid GIDL the influence of peak current when maintenance " 0 " attitude.

Described MOSFET pipe 12 has substrate 121, is formed with the second source region 122 in described substrate 121 1 sides, is formed with the second drain region 123 at the opposite side of described substrate 121, in second drain electrode 125 in second source electrode 124 in corresponding described the second source region 122 on the described substrate 121, corresponding described the second drain region 123 and at described the second source electrode 124 and the second second gate insulation course 126 that drains between 125, stacking on the described second gate insulation course 126 have a second grid 127.

Especially need to prove, in twin transistor memory 1 of the present invention, described first grid 118 is connected with word line WL, described the first drain electrode 116 is connected with the first bit line BL1, described second grid 127 connects described the first source electrode 115, described the second drain electrode 125 is connected with the second bit line BL2, described the second source electrode 124 ground connection.

For further illustrating principle of the present invention and effect, see also Fig. 3 a to Fig. 4, at first see also Fig. 3 a, can be with synoptic diagram when being shown as I-MOS pipe OFF state.As shown in the figure, described I-MOS pipe 11 is under OFF state, and first grid 118 adds less positive bias, and can not form transoid and can not accumulate again this moment, and length of effective channel is whole intrinsic region 114.At this moment, transverse electric field is not enough to reach breakdown field strength, and the electronics of source can't obtain enough energy generation ionizing collisions.

See also again Fig. 3 b, can be with synoptic diagram when being shown as I-MOS pipe ON state.As shown in the figure, described I-MOS pipe 11 is under ON state, and first grid 118 adds larger negative bias, and accumulation P-district (Lgate as shown in Figure 1) appears in the raceway groove of described first grid 118 belows, thereby has shortened the length of effective channel of device.At this moment along with V _DSIncrease, a part of incremental voltage drop can drop on the LI zone (as shown in Figure 1), and the transverse electric field that namely is added on the described intrinsic region 114 increases, and transverse electric field can increase along with the increase of grid voltage simultaneously.At this moment the electronics of the first source electrode 115 can obtain enough kinetic energy, to such an extent as to when and intrinsic region 114 atoms when producing bump, can destroy key and produce electron-hole pair, these process life and growth in nature successively produce new electron-hole pair.Because this multiplier effect so that produce a large amount of charge carriers in the potential barrier I district unit, increases rapidly inverse current, thereby the P-N junction breakdown occurs.

See also Fig. 4, be shown as the P-N knot synoptic diagram in the avalanche multiplication mechanism.Described I-MOS pipe 11 is under larger reverse biased, electric field in the potential barrier intrinsic region 114 is very strong, electronics in intrinsic region 114 and hole are owing to be subject to the drift action of highfield, has very large kinetic energy, when the character atom in they and the intrinsic region 114 bumps, can the electron collision on the valence link out become conduction electrons, produce simultaneously a hole.Electronics e collides out an electronics e and a hole h in the P-I-N junction barrier, and these three charge carriers are under the highfield effect, and motion also can continue to bump the mechanism of avalanche breakdown that Here it is in the opposite direction.Avalanche breakdown except with the barrier region in electric field intensity closely related, also relevant with the barrier region width, because the increase of charge carrier kinetic energy, also need to have an accelerator, if the barrier region is very thin, even electric field is very strong avalanche breakdown can not occur, this also is one of our reason of adopting wider intrinsic region 114.

As from the foregoing, the principle of work of twin transistor memory 1 of the present invention is:

(a) one writing state, described first grid 118 adds negative bias, can occur accumulating the p district in the overlapping region of first grid 118 with raceway groove, and length of effective channel shortens to LI.Be biased to the first drain electrode 116 just this moment, avalanche breakdown enough greatly consequently occurs in the transverse electric field that is added on the LI zone, the electronics that produces flows out through drain electrode, the hole, tagma is managed 11 first source electrodes 115 by described I-MOS and is discharged, second grid 127 current potentials of described MOSFET pipe 12 are raised by the hole of described I-MOS pipe 11, described MOSFET pipe 12 will be opened this moment, by measuring one writing, the distinguishable different conditions of the current value of two serial transistors when " 0 ".

(b) finish when one writing, enter the maintenance attitude.Only need the first bit line BL1 zero offset this moment, and the hole is pumped to the P district storage that described 1-MOS manages 11 raceway grooves below.

When (c) reading " 1 ", word line WL is added positive potential, the hole is again by the second grid 127 discharged to described MOSFET pipe 12, and this moment, described MOSFET pipe 12 was unlocked, can the reading current value by the second bit line BL2.

(d) write " 0 " state, described first grid 118 still adds negative bias, the p district can occur accumulating in the overlapping region of first grid 118 and raceway groove, and be biased to the first drain electrode 116 negative this moment, and the first drain electrode 116 discharges of 11 are managed in the hole thereupon by described I-MOS.

(e) finish when writing " 0 ", enter the maintenance attitude.Only need this moment the first bit line BL1 is biased to zero, at this moment described I-MOS manages in 11 without unnecessary hole.

When (d) reading " 0 ", word line WL is added positive potential, the still cut-off of described MOSFET pipe 12 this moment, the current value that is read by the second bit line BL2 is zero.

By distinguishing the current value of described the second bit line BL2 under the state of " 1 " " 0 ", can finish storage.

In sum, twin transistor memory of the present invention and the structural difference of traditional TTRAM are: the T1 pipe adopts I-MOS structure (Impact-Ionization MOS), and the T2 pipe is normal MOSFET.Its advantage is: not only have very fast switching speed, this can implement quick conversion to the writing of " 0 " and one state, maintenance, read states.And GIDL the influence of peak current can effectively avoid " 0 " state the time, thereby improve " 0 " attitude retention time.

Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not is used for restriction the present invention.Any person skilled in the art scholar all can be under spirit of the present invention and category, and above-described embodiment is modified or changed.Therefore, have in the technical field under such as and know that usually the knowledgeable modifies or changes not breaking away from all equivalences of finishing under disclosed spirit and the technological thought, must be contained by claim of the present invention.

Claims

1. a twin transistor memory is characterized in that, comprising:

The I-MOS pipe, has buried insulator layer, be positioned at the semiconductor layer on the described buried insulator layer, described semiconductor layer comprises the first source region, the first drain region and the intrinsic region between described the first source region and the first drain region, and the first source electrode that is positioned at corresponding described the first source region on the described semiconductor layer, first drain electrode in corresponding described the first drain region, and between described the first source electrode and the first drain electrode and the first grid insulation course of corresponding described intrinsic region, one side of described first grid insulation course upper surface is stacking first grid, described first grid is connected with the word line, and described the first drain electrode is connected with the first bit line; Comprise effective channel region in the intrinsic region of described I-MOS pipe, the width of described effective channel region changes with the grid voltage size that applies on the described first grid, and the channel part of described first grid and below is overlapping; And

The MOSFET pipe, have substrate, be formed with the second source region in described substrate one side, be formed with the second drain region at the opposite side of described substrate, at the second drain electrode and the second gate insulation course between described the second source electrode drains with second in second source electrode in corresponding described the second source region on the described substrate, corresponding described the second drain region, stacking on the described second gate insulation course have a second grid, described second grid connects described the first source electrode, described the second drain electrode is connected with the second bit line, described the second source ground.

2. twin transistor memory according to claim 1 is characterized in that: described I-MOS pipe is P type raceway groove I-MOS pipe.

3. twin transistor memory according to claim 1 is characterized in that: described MOSFET pipe is managed for enhancement mode MOSFET.

4. twin transistor memory according to claim 1 is characterized in that: described MOSFET pipe is managed for depletion type MOS FET.