CN102193871B - Nonvolatile memory access method, system and nonvolatile memory controller - Google Patents
Nonvolatile memory access method, system and nonvolatile memory controller Download PDFInfo
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- CN102193871B CN102193871B CN201010136470.2A CN201010136470A CN102193871B CN 102193871 B CN102193871 B CN 102193871B CN 201010136470 A CN201010136470 A CN 201010136470A CN 102193871 B CN102193871 B CN 102193871B
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Abstract
The invention discloses a nonvolatile memory access method, a nonvolatile memory access system and a nonvolatile memory controller. The method and the system are used for accessing a plurality of entity blocks in a nonvolatile memory chip, and each entity block is provided with a plurality of entity pages. The method comprises the following steps of: when the data stored in one of the plurality of specific entity pages in the first entity block are updated, judging whether the first entity block has enough space for writing in the specific entity pages, if so, writing the valid data of the specific entity pages and the data to be updated into the first entity block.
Description
Technical field
The present invention relates to nonvolatile memory controller and the non-volatility memorizer access system of a kind of non-volatility memorizer access method and use the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, and consumer is also increased rapidly to the demand of storage medium.Because non-volatility memorizer (Flash Memory) has that data are non-volatile, the little characteristic with machinery-free structure etc. of power saving, volume, be applicable to portable applications, the most applicable being used on the battery-powered product of this class Portable.Solid state hard disc (Solid State Drive, SSD) is exactly a kind of memory storage using NAND non-volatility memorizer as storage medium.Because non-volatility memorizer volume low capacity is large, so be widely used in the storage of individual significant data.Therefore, non-volatility memorizer industry becomes a ring quite popular in electronic industry in recent years.
In the design of non-volatility memorizer access device, non-volatile memory chip has multiple physical blocks (block), and each physical blocks has multiple physical page (page).Wherein, physical blocks is that the minimum of non-volatility memorizer is wiped (erase) unit, and physical page is that the minimum of non-volatility memorizer writes (program) unit.Due in the time that the storage unit to non-volatility memorizer (memory cell) is programmed, only can fill order to programming (being also programmed for 0 by the value of storage unit by 1), the physical page that therefore data cannot be write direct and had been programmed.In other words, must first the physical page that stores data be wiped afterwards to just this physical page of Reprogrammable.But, just because wiping of non-volatility memorizer is taking physical blocks as unit, therefore carrying out and wipe when running there being the physical page of legacy data, the whole physical blocks under this physical page must be wiped.
Generally speaking, the nonvolatile memory controller of non-volatility memorizer access device can logically be grouped into physical blocks all in non-volatile memory chip system region (system area), data field (data area), spare area (spare area) and replace district (replacement area).Wherein, the physical blocks of system region, in order to the storage important information relevant to non-volatility memorizer access device, replaces the physical blocks in district in order to replace the physical blocks (that is bad physical blocks) of having damaged in data field or spare area.Therefore,, under general access status, host computer system is cannot access system district and the physical blocks replacing in district.As for, the physical blocks that is classified as data field can be stored the valid data that write by writing instruction, and the physical blocks of spare area is in order to the physical blocks in replacement data district in the time that execution writes instruction.Hence one can see that, assigns when writing instruction when host computer system, conventionally can be accompanied by the action that two physical blocks (that is the physical blocks of data field and physical blocks of spare area) merge, and uses the object that just can complete Data Update.
But, in the application of some non-volatility memorizer, particularly, for the digital memory card of microampere (micro secure-digital/SD memory card) with smart card (smartcard), the specifications that such Data renewal mechanism probably cannot meet the digital memory card of existing microampere have defined a time that writes instruction.Generally speaking, the specifications of the digital memory card of microampere clearly define each deadline that writes instruction and must be less than 250ms.
Summary of the invention
The present invention proposes a kind of non-volatility memorizer access method, system and nonvolatile memory controller, in order to guarantee that the time that writes instruction of carrying out is no more than the defined time of specifications.
The present invention proposes a kind of non-volatility memorizer access method, and for managing the multiple physical blocks in non-volatile memory chip, and each physical blocks has multiple physical page.This non-volatility memorizer access method comprises in the time that one of them data of storing of the multiple special entity pages that are connected in first instance block will be updated, judges whether first instance block has sufficient space to write described special entity page.In the time that first instance block has sufficient space to write described special entity page, the valid data of described special entity page and the data that will be updated are write in first instance block.
The present invention separately proposes a kind of non-volatility memorizer access method, for the multiple physical blocks in access non-volatile memory chip.Wherein each physical blocks has multiple physical page, and above-mentioned physical page comprises multiple quick physical page and multiple physical page at a slow speed.This non-volatility memorizer access method comprises in the time that data are write to first instance block by host computer system wish, judges whether the physical page of predetermined number in first instance block is fully written.In the time that the physical page of predetermined number has been fully written, select second instance block to carry out data writing.Wherein, the physical page of predetermined number is at least 2 physical page, and comprises part physical page and part physical page at a slow speed fast, and in the time that the physical page of predetermined number has been fully written, still has part physical page not to be written into data in first instance block.
The present invention also provides a kind of nonvolatile memory controller, be disposed in non-volatility memorizer access device, this non-volatility memorizer access device comprises non-volatile memory chip, wherein non-volatile memory chip comprises multiple physical blocks, and each physical blocks has multiple physical page.Nonvolatile memory controller comprises microprocessor unit, non-volatility memorizer interface unit, host interface unit and Memory Management Unit.Non-volatility memorizer interface unit couples microprocessor unit, in order to be coupled to non-volatile memory chip.Host interface unit is coupled to microprocessor unit, in order to be coupled to host computer system.Memory Management Unit is coupled to microprocessor unit.Wherein, in host computer system wish is upgraded above-mentioned physical blocks in first instance block be connected multiple special entity pages one of them store data time, Memory Management Unit judges whether first instance block has sufficient space to write above-mentioned special entity page.In the time that first instance block has sufficient space to write above-mentioned special entity page, the valid data of above-mentioned special entity page and the data that will be updated are write in first instance block.
The present invention proposes a kind of nonvolatile memory controller, be disposed in non-volatility memorizer access device, non-volatility memorizer access device comprises non-volatile memory chip, wherein non-volatile memory chip comprises multiple physical blocks, and each physical blocks has multiple physical page, and above-mentioned physical page comprises multiple quick physical page and multiple physical page at a slow speed.Nonvolatile memory controller comprises microprocessor unit, non-volatility memorizer interface unit, host interface unit and Memory Management Unit.Non-volatility memorizer interface unit couples microprocessor unit, in order to be coupled to non-volatile memory chip.Host interface unit is coupled to microprocessor unit, in order to be coupled to host computer system.Memory Management Unit is coupled to microprocessor unit.Wherein, in the time that host computer system is wanted data writing to first instance block in above-mentioned physical blocks, Memory Management Unit judges whether the physical page of predetermined number in first instance block is fully written.Wherein, the physical page of predetermined number is at least 2 physical page, and comprises part physical page and part physical page at a slow speed fast.In the time that the physical page of predetermined number has been fully written, in first instance block, still have part physical page not to be written into data, and Memory Management Unit select second instance block with data writing.
The present invention more provides a kind of non-volatility memorizer access system, comprises non-volatile memory chip, connector, and nonvolatile memory controller.Non-volatile memory chip has multiple physical blocks, and each physical blocks has multiple physical page.Connector is in order to be coupled to host computer system.Nonvolatile memory controller is coupled to non-volatile memory chip and connector, when host computer system wish upgrade in above-mentioned physical blocks multiple special entity pages of being connected in first instance block one of them store data time, nonvolatile memory controller judges whether first instance block has sufficient space to write above-mentioned special entity page.If so, the valid data of above-mentioned special entity page and the data that will be updated are write in first instance block.
For above-mentioned feature and advantage of the present invention can be become apparent, multiple embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below, but above-mentioned general description and following embodiment are only exemplary and illustrative, it can not limit the scope that institute of the present invention wish is advocated.
Brief description of the drawings
Figure 1A is that the first exemplary embodiment illustrates the host computer system that uses non-volatility memorizer access device according to the present invention.
Figure 1B is the schematic diagram of exemplary embodiment illustrates according to the present invention computing machine, input/output device and non-volatility memorizer access device.
Fig. 1 C is another exemplary embodiment illustrates according to the present invention host computer system and the schematic diagram of non-volatility memorizer access device.
Fig. 2 is the summary calcspar that illustrates the non-volatility memorizer access device shown in Figure 1A.
Fig. 3 is the running schematic diagram that illustrates the non-volatility memorizer access device shown in Figure 1A.
Fig. 4 A and Fig. 4 B are the schematic diagram of the Data Update that one exemplary embodiment illustrates according to the present invention.
Fig. 5 illustrates the first Thread and second according to one example of the present invention embodiment to carry out the continuous sequential chart that writes instruction of carrying out.
Fig. 6 is the process flow diagram that illustrates non-volatility memorizer access method according to one example of the present invention embodiment.
Fig. 7 is the process flow diagram that illustrates non-volatility memorizer access method according to another example of the present invention embodiment.
[main element symbol description]
1000: host computer system
1100: computing machine
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: Portable disk
1214: storage card
1216: solid state hard disc
1310: digital camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded memory storage
100: non-volatility memorizer access device
102: connector
104: nonvolatile memory controller
106: non-volatile memory chip
106A: the first storage area
106B: the second storage area
202: microprocessor unit
204: Memory Management Unit
206: host interface unit
208: non-volatility memorizer interface unit
252: memory buffer
254: Power Management Unit
256: error correction unit
310: the first Threads
320: the second Threads
P0～P127: physical page
T
1, t
2, t
3, t
4: time point
T
13: the time of the first Thread data writing
T
34: the time of the second Thread data writing
T
14: T.T.
610～650: each step of the non-volatility memorizer access method described in one example of the present invention embodiment
710～770: each step of the non-volatility memorizer access method described in another example of the present invention embodiment
Embodiment
With detailed reference to embodiments of the invention, and the example of described embodiment is described in the accompanying drawings.In addition, all possibility parts are used the element/member of same numeral to represent identical or similar portions in graphic and embodiment.
Figure 1A is the schematic diagram of the host computer system of the use non-volatility memorizer access device that illustrates of exemplary embodiment according to the present invention.Wherein, non-volatility memorizer access device also can be described as non-volatility memorizer access system.
Please refer to Fig. 1, host computer system 1000 comprises computing machine 1100 and I/O (Input/Output, I/O) device 1106.
Computing machine 1100 comprises microprocessor 1102, random access memory (Random AccessMemory, RAM) 1104, system bus 1108, and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, display 1206 and printer 1208 as shown in Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In exemplary embodiment of the present invention, non-volatility memorizer access device 100 can couple by data transmission interface 1110 and other elements of host computer system 1000.Processing by microprocessor 1102, random access memory 1104 with input/output device 1106, host computer system 1000 can write to data non-volatility memorizer access device 100, or from non-volatility memorizer access device 100 reading out data.For example, non-volatility memorizer access device 100 can be storage card 1214, Portable disk 1212 as shown in Figure 1B, or solid state hard disc (Solid State Drive, SSD) 1216.
Host computer system 1000 is for storing any system of data.Although in this exemplary embodiment, host computer system 1000 is to describe with computer system, but in another exemplary embodiment of the present invention, host computer system 1000 can be also the systems such as digital camera, video camera, communicator, audio player or video player.For example, in the time that host computer system is digital camera 1310, non-volatility memorizer access device is its secure digital using (Secure Digital, SD) card 1312, multimedia storage (Multimedia Card, MMC) card 1314, memory stick (Memory Stick) 1316, compact flash (Compact Flash, CF) card 1318 or embedded memory storage 1320 (as shown in Figure 1 C).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly coupled on the substrate of host computer system.
Fig. 2 is the summary calcspar that illustrates the non-volatility memorizer access device shown in Figure 1A.Please refer to Fig. 2, non-volatility memorizer access device 100 comprises connector 102, nonvolatile memory controller 104, and non-volatile memory chip 106.
Connector 102 is coupled to nonvolatile memory controller 104, and in order to be coupled to host computer system 1000.In this exemplary embodiment, the transmission interface kind that connector 102 is supported is safe digital interface (SD interface).But in other exemplary embodiment, the transmission interface kind of connector 102 can be also multimedia storage card (Multimedia Card, MMC) interface, advanced annex (the Serial Advanced Technology Attachment of serial, SATA) interface, parallel advanced annex (Parallel Advanced Technology Attachment, PATA) interface, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 interfaces, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) interface, USB (universal serial bus) (Universal Serial Bus, USB) interface, memory stick (Memory Stick, MS) interface, compact flash (Compact Flash, CF) interface, or integration drives electronics (Integrated Drive Electronics, IDE) any applicable interface such as interface, do not limited at this.
Nonvolatile memory controller 104 can be carried out multiple logic locks or the steering order with hardware pattern or firmware pattern implementation, and in non-volatile memory chip 106, carries out the runnings such as writing, read and wipe of data according to the instruction of host computer system 1000.
In this exemplary embodiment, non-volatile memory chip 106 is flash memory chip, and flash memory chip has multiple physical blocks (block), and each physical blocks has multiple physical page (page).Non-volatile memory chip 106 is in order to store as filesystem informations such as file configuration table (File AllocationTable, FAT), and storage data as general in audio/video file, text etc.In this exemplary embodiment, non-volatile memory chip 106 is multilayered memory unit (MultiLevel Cell, MLC) NAND flash memory chip.But the invention is not restricted to this, also individual layer storage unit (Single Level Cell, SLC) NAND flash memory chip of non-volatile memory chip 106.
In detail, in current NAND flash memory technology, NAND flash memory chip can be divided into SLC NAND flash memory chip and MLC NAND flash memory chip according to storable bit number in each storage unit.In the time that the storage unit of SLC NAND flash memory chip is programmed to (program), only can carry out the programming of single-order, therefore each storage unit only can be stored a bit.The programming of the physical blocks of MLC NAND flash memory chip can be divided into the multistage.For example, taking 2 layers of storage unit as example, the programming of physical blocks can be divided into for 2 stages.First stage is the part that writes of nextpage (lower page), and its physical characteristics is similar to SLC NAND flash memory chip, and page (upper page) on just can programming after completing the first stage.Wherein the writing speed of nextpage can be faster than upper page.Therefore, the included physical page of each physical blocks can be divided into physical page (, upper page) and quick physical page (, nextpage) at a slow speed.
Similarly, in the case of 8 layers of storage unit or 16 layers of storage unit, storage unit can comprise more physical page and can be so that more the multistage writes.At this, physical page the fastest writing speed is called to nextpage, the slower physical page of other writing speeds is referred to as page, that is upper page comprises multiple physical page with different writing speeds.And in other exemplary embodiment, upper page also can be the slowest physical page of writing speed, or writing speed is the slowest and part writing speed faster than the physical page of slow physical page of writing speed.For example, in 4 layers of storage unit, nextpage is the physical page that writing speed is the fastest and writing speed is time fast, upper page be writing speed the most slowly and the inferior slow physical page of writing speed.
In this exemplary embodiment, nonvolatile memory controller 104 comprises microprocessor unit 202, Memory Management Unit 204, host interface unit 206, and non-volatility memorizer interface unit 208.
Microprocessor unit 202 is the main control unit of nonvolatile memory controller 104, in order to the cooperative cooperating such as Memory Management Unit 204, host interface unit 206 and non-volatility memorizer interface unit 208, to carry out the various runnings of non-volatility memorizer access device 100.
Memory Management Unit 204 is coupled to microprocessor unit 202, in order to carry out a non-volatility memorizer access mechanism.In this exemplary embodiment, Memory Management Unit 204 can firmware pattern be embodied in nonvolatile memory controller 104.For example, the Memory Management Unit 204 that comprises multiple steering orders (is for example burned onto to a program storage, ROM (read-only memory) (Read Only Memory, ROM)) in, and this program storage is embedded in to nonvolatile memory controller 104.In the time that non-volatility memorizer access device 100 operates, microprocessor unit 202, by multiple steering orders of execute store administrative unit 204, is carried out non-volatility memorizer access mechanism according to this.The detailed function mode of Memory Management Unit 204 will explain in following cooperation accompanying drawing again.
Host interface unit 206 is coupled to microprocessor unit 202, and is coupled to host computer system 100.Host interface unit 206 is in order to receive the instruction and the data that transmit with identification host computer system 1000.That is to say, the instruction that host computer system 1000 transmits and data can be sent to microprocessor unit 202 by host interface unit 206.In this exemplary embodiment, host interface unit 206 is for meeting SD interface, and in other exemplary embodiment, host interface unit 1042 can be also the interface unit that meets MMC interface, SATA interface, PATA interface, IEEE 1394 interfaces, PCI Express interface, USB interface, MS interface, CF interface, ide interface or other interface standards.
Non-volatility memorizer interface unit 208 is coupled to microprocessor unit 202, and with so that nonvolatile memory controller 104 is coupled to non-volatile memory chip 106, uses and allow nonvolatile memory controller 104 to non-volatile memory chip 106 running of being correlated with.That is to say, the data of wanting to write to non-volatile memory chip 106 can be converted to 106 receptible forms of non-volatile memory chip via non-volatility memorizer interface unit 208.
In another exemplary embodiment, nonvolatile memory controller 104 also comprises memory buffer 252, Power Management Unit 254, and error correction unit 256.
Memory buffer 252 is coupled to microprocessor unit 202, and in order to the temporary data and instruction that comes from host computer system 1000, or in order to the temporary data that come from non-volatile memory chip 106.
Power Management Unit 254 is coupled to microprocessor unit 202, and in order to control the power supply of non-volatility memorizer access device 100.
Error correction unit 256 is coupled to microprocessor unit 202, and in order to carry out an error-correcting routine to guarantee the correctness of data.Specifically, when Memory Management Unit 204 receives while writing instruction from host computer system 1000, error correction unit 256 can produce corresponding bug check and correcting code (Error Checking and Correcting Code for corresponding this data writing that writes instruction, ECC Code), and Memory Management Unit 204 can write to this data writing in non-volatile memory chip 106 with corresponding error-correcting code.Afterwards, when Memory Management Unit 204 can read error-correcting code corresponding to these data when reading out data from non-volatile memory chip 106 simultaneously, and error correction unit 256 can be according to this error-correcting code to read data execution error correction program.
In this exemplary embodiment, nonvolatile memory controller 104 comprises more than one Thread, the real time operation system by nonvolatile memory controller 104 (RealTime Operation System, RTOS) unit (not illustrating) is carried out scheduling by these Threads.That is non-volatility memorizer access device 100 adopts multi-threading framework, and real time operation system unit is used for managing and the execution sequence that determines these Threads.Must special instruction, the present invention not quantity to Thread and action thereof is limited.
For convenience of description, comprise two Threads (the first Thread 310 as shown in Figure 3 and the second Thread 320) at this hypothesis nonvolatile memory controller 104.The first Thread 310 and the second Thread 320 must carry out access to non-volatile memory chip 106 by non-volatility memorizer interface unit 208.Suppose that non-volatility memorizer access device 100 is the digital memory cards of microampere (micro SD memory card) with smart card (smartcard), the first Thread 310 is for example smart card application program so, in order to carry out the instruction relevant to smart card, the second Thread 320 is to be for example responsible for receiving the instruction from host computer system 1000, and reads and writes data from non-volatile memory chip 106.In this exemplary embodiment, although the first Thread 310 and the second Thread 320 all have the demand of access non-volatile memory chip 106, the data access amount of the first Thread 310 can be less than the second Thread 320 in comparison.And what must specify is, real time operation system unit in nonvolatile memory controller 104 need be consigned to after the first Thread 310 by the responsible instruction of the first Thread 310, nonvolatile memory controller 104 just can be responded 1000 messages that work is finished of host computer system, and (mode of response can return message in the time that host computer system 1000 is inquired, or initiatively message is reached to host computer system 1000 by nonvolatile memory controller 104), this measure is that to resolve command content for fear of the first Thread 310 consuming time excessively of a specified duration.But, need be consigned to after the second Thread 320 by the responsible instruction of the second Thread 320 in instant operating system unit, must wait for second Thread 320 is actual and for example finish the work, after (data writing), the message that nonvolatile memory controller 104 just can passback work completes.
In this exemplary embodiment, non-volatile memory chip 106 is at least divided into the first storage area 106A and the second storage area 106B.Wherein, the first Thread 310, in order to the first storage area 106A is carried out to access, can be processed the instruction that writes that data will be write to the first storage area 106A.The second Thread 320 is in order to the second storage area 106B is carried out to access, can process the instruction that writes that data will be write to the second storage area 106B.Furthermore, be smart card access instruction about the instruction that writes of the first storage area 106A, and be safety digital storage card access instruction about the instruction that writes of the second storage area 106B.
Generally speaking, when what nonvolatile memory controller 104 was assigned in execution host computer system 1000 writes instruction, conventionally need to follow the action that two physical blocks are merged, use the object of Data Update.But the specifications of the digital memory card of microampere clearly define each deadline that writes instruction and must be less than or equal to a regulation time limit (i.e. 250 milliseconds (ms)).
The size of supposing each physical page in this exemplary embodiment is 4K byte (byte), and each physical blocks has 128 physical page.The estimation result demonstration of actual metric data, the required time that completes the merging action of two physical blocks is about 155.8ms.Suppose that accordingly nonvolatile memory controller 104 obtains the instruction that writes that need be carried out by the first Thread 310, and the merging action that this writes instruction meeting and produces two physical blocks, if during data are write non-volatile memory chip 106 by the first Thread 310, host computer system 1000 has been assigned again the instruction that writes that need be carried out by the second Thread 320, because the first Thread 310 and the second Thread 320 all must could carry out access to non-volatile memory chip 106 by non-volatility memorizer interface unit 208, therefore the second Thread 320 must wait for that the first Thread 310 could access non-volatile memory chip 106 after completing block merging action.The merging action that what if the second Thread 320 was performed writes instruction also can produce two physical blocks, so the second Thread 320 complete write instruction be about 311.6ms T.T. (, 155.8 × 2), exceed the 250ms of defined regulation time limit of specifications of the digital memory card of microampere.
In order effectively to solve such problem, the instruction that writes of assigning when host computer system 1000 is some physical blocks (being referred to as below first instance block) of wanting in the first storage area 106A of access non-volatile memory chip 106, represents that this writes instruction and need be carried out by the first Thread 310.If this write instruction to be updated in first instance block several special entity pages of being connected one of them store data time, first Memory Management Unit 204 judges whether first instance block has sufficient space to write above-mentioned special entity page.
If first instance block has sufficient space to write above-mentioned special entity page, just Memory Management Unit 204 makes the first Thread 310 that the valid data of above-mentioned special entity page and the data that will be updated are write in first instance block.But in the time that first instance block writes above-mentioned special entity page without sufficient space, Memory Management Unit 204 is selected an empty physical blocks (being referred to as below second instance block) in the included physical blocks of the first storage area 106A, and makes the first Thread 310 that the valid data of above-mentioned special entity page and the data that will be updated are write in second instance block.Must special instruction, in the time that the valid data of above-mentioned special entity page and the data that will be updated are write to first instance block, the first Thread 310 utilize the quick physical page of part in first instance block and part at a slow speed physical page carry out data writing.Similarly, in the time the valid data of above-mentioned special entity page and the data that will be updated need to being write to second instance block, the first Thread 310 utilize the quick physical page of part in second instance block and part at a slow speed physical page carry out data writing.
In this exemplary embodiment, above-mentioned special entity page definition is a data-moving unit as can be seen here, and the quantity of special entity page is more than or equal to 2, and is less than the physical page sum that each physical blocks of non-volatile memory chip 106 comprises respectively.At this, suppose that in non-volatile memory chip 106, a physical blocks has 128 physical page, data-moving unit is for example 4 physical page (quantity that is special entity page is 4), but is not restricted to this.
Taking Fig. 4 A as example, suppose that the data that in first instance block, the special entity page P2 in 4 special entity page P0-P3 stores will be updated, and when the physical page P4-P127 in first instance block does not all have data, Memory Management Unit 204 can be judged first instance block has sufficient space to write the data of 4 special entity pages.Accordingly, Memory Management Unit 204 can make the first Thread 310 first the data of storing (that is valid data) of special entity page P0, P1 and P3 in first instance block be read, and then again read data and new data (that is the data that need be updated) is write to the physical page P4-P7 in first instance block.
But exemplary embodiment as shown in Figure 4 B, suppose that the data that in first instance block, the special entity page P125 in special entity page P123-P126 stores will be updated, and when in first instance block, only remaining physical page P127 does not have data, Memory Management Unit 204 can be judged first instance block does not have sufficient space to write the data of 4 special entity pages.Thus, Memory Management Unit 204 can make the first Thread 310 first select an empty second instance block from the first storage area 106A, and the data of storing (that is valid data) of special entity page P123, P124 and P126 in first instance block are read, then again read data and new data are write to the physical page P0-P3 in second instance block.
At this, the first Thread 310 is using 4 physical page as a data-moving unit.Therefore, in the time will upgrading the data of the first storage area 106A, Memory Management Unit 204 can judgement have or not enough storage spaces to carry out Data Update in same physical blocks, if without enough storage spaces, just can look for new physical blocks and carry out Data Update.In view of this, up-to-date data must be to be arranged in last data-moving unit containing data of physical blocks.Because upgraded data are only occupied the capacity of several physical page in a physical blocks, so the first Thread 310 is wanted the phenomenon of the data merging that two intact block can't occur carry out Data Update in the first storage area 106A time.Promote accordingly the first Thread 310 and in the first storage area 106A, carry out the speed of write activity.
Fig. 5 be according to one example of the present invention embodiment illustrate during data are write non-volatile memory chip 106 by the first Thread 310, host computer system 1000 is assigned again the sequential chart that writes instruction that will be carried out by the second Thread 320.As shown in Figure 5, suppose that the first Thread 310 is at time point t
1to t
3between can data be write to non-volatile memory chip 106 by non-volatility memorizer interface unit 208.Due to the first Thread 310, to complete the physical page quantity included with data-moving unit of required time of write activity relevant, and therefore the included physical page quantity of data-moving unit is fewer, and it is just shorter that the first Thread 310 completes the required time of write activity.For instance, the size of supposing a physical page is that 4K byte and a physical blocks have 128 physical page, and the estimation result of border metric data shows factually, is about 1.15ms the averaging time of a physical page of read-write.If the included physical page quantity of data-moving unit is 1 in this exemplary embodiment, the first Thread 310 completes the required time T of write activity so
131.15ms.
If nonvolatile memory controller 104 is at time point t
2receive need the second storage area 106B of access non-volatile memory chip 106 write instruction (claiming this to write instruction at this, to want the physical blocks of access be the 3rd physical blocks), represent that this writes instruction and need be carried out by the second Thread 320.The second Thread 320 needs to wait for that it (is time point t that the first Thread 310 completes write activity
3) after, can data be write to non-volatile memory chip 106 by non-volatility memorizer interface unit 208.Need follow the merging of physical blocks if what the second Thread 320 was responsible for carrying out writes instruction, Memory Management Unit 204 can be according to the data access mechanism of general non-volatility memorizer, in non-volatile memory chip 106, select an empty physical blocks to be beneficial to carry out block merging with the 3rd physical blocks, and then complete the renewal of data.It is estimated, in the situation that need to merging two physical blocks, the second Thread 320 is actual carries out the time T that data write
34be approximately 155.8ms, even and if add that wait the first Thread 310 completes the required time T of write activity
13after, the second Thread 320 completes a T.T. T who writes instruction
14the specifications that (being 155.8ms+1.15ms) still can be less than the digital memory card of microampere have defined a regulation time limit (being 250ms) that writes instruction.
From the described content of above-mentioned exemplary embodiment, the Managed Solution of taking for the first storage area 106A is the time in order to reduce first Thread 310 access the first storage area 106A as far as possible, so in the time that the first Thread 310 carries out access to the first storage area 106A, size that not only can the restricting data unit of moving, whether must down look for same physical blocks has enough storage spaces to carry out Data Update simultaneously, so can not there is the merging action of two physical blocks, the time of the first storage area 106A being carried out to access in order to shortening the first Thread 310.
On the other hand, the storage space in order to utilize each physical blocks in the second storage area 106B as far as possible for the Managed Solution of the second storage area 106B, so in the time that the second Thread 320 carries out access to the second storage area 106B, can carry out general non-volatility memorizer administrative mechanism.
But, because can adopting two kinds of different Managed Solutions, Memory Management Unit 204 manages the first storage area 106A and the second storage area 106B in non-volatile memory chip 106, even if so the first Thread 310 in nonvolatile memory controller 104 is during writing data the first storage area 106A, the second Thread 320 is obtained the instruction that writes that data need be write to the second storage area 106B, also can guarantee that the specifications that can be less than the digital memory card of microampere T.T. that data are write non-volatile memory chip 106 by the first Thread 310 and the second Thread 320 priorities have defined a regulation time limit that writes instruction.
Fig. 6 is the process flow diagram that illustrates non-volatility memorizer access method according to one example of the present invention embodiment.
Please refer to Fig. 6, the non-volatility memorizer access method of this exemplary embodiment is in order to manage the multiple physical blocks in non-volatile memory chip 106, and each physical blocks has multiple physical page.The non-volatility memorizer access device 100 of this exemplary embodiment adopts multi-threading framework, that is comprise real time operation system unit and multiple Thread (for example the first Thread 310 and the second Thread 320) at nonvolatile memory controller 104, and these Threads are to do scheduling management by real time operation system unit, and the first Thread 310 and the second Thread 320 can pass through non-volatility memorizer interface unit 208 access non-volatile memory chips 106.
First as shown in step 610, interior non-volatile memory chip 106 contained physical blocks is divided into the first storage area 106A and the second storage area 106B.Wherein the first Thread 310 is access the first storage area 106A, and the second Thread 320 is access the second storage area 106B.
Then in step 620, what Receiving Host system 1000 transmitted writes instruction, and what this write that instruction wants to write is a certain physical blocks (being referred to as below first instance block) in the first storage area 106A, writes instruction therefore need carry out this by the first Thread 310.Suppose that this writes instruction is to upgrade one of them data of storing of multiple special entity pages that are connected in first instance block.
Next as shown in step 630, judge by the Memory Management Unit 204 in nonvolatile memory controller 104 whether first instance block has the sufficient space can be in order to write above-mentioned special entity page.
In the time that first instance block has sufficient space to write above-mentioned special entity page, as shown in step 640, the valid data of above-mentioned special entity page and the data that will be updated are write in first instance block, use Data Update.And in the time that first instance block writes above-mentioned special entity page without sufficient space, as shown in step 650, select to be positioned at equally the first storage area 106A and the second instance block for sky, in order to the valid data of above-mentioned special entity page and the data that will be updated are write in second instance block, use Data Update.
Each step as shown in Figure 6, the first Thread 310 is using n special entity page as data-moving unit.Wherein n is more than or equal to 2, is less than the included physical page sum of each physical blocks of non-volatile memory chip simultaneously.To come data writing in the mode shown in Fig. 6 at the first Thread 310, even if when the first Thread 310 is during writing non-volatile memory chip 106 by data, host computer system 1000 transmitted again need be carried out by the second Thread 320 write instruction (for example data will be write to a certain physical blocks in the second storage area 106B), because the included physical page quantity of data-moving unit is less than a physical page sum that physical blocks is included, the first Thread 310 will not have the action generation that merges two physical blocks.Therefore as long as the quantity of the included physical page of data-moving unit is down to a certain degree, though the second Thread 320 be responsible for write the merging whether instruction needs to follow physical blocks, the second Thread 320 complete write instruction T.T. all will can not exceed the regulation time limit.
In another exemplary embodiment, in the first storage area 106A of 310 energy accesses of the first Thread, each included physical blocks is all only carried out data writing by the physical page of predetermined number.Wherein, predetermined number is less than the included physical page sum of each physical blocks of non-volatile memory chip 106, and the physical page of predetermined number is at least 2 physical page, and it comprises part physical page and part physical page at a slow speed fast.For instance, the physical page of predetermined number can be 2 quick physical page and 2 physical page at a slow speed, but the present invention is not as limit.
The size of predetermined number has defined one according to the specifications of the digital memory card of microampere and has write the regulation time limit (being 250ms) of instruction, the averaging time of two physical blocks of merging, and these several the parameters of average required time of a physical page of read-write are tried to achieve.For instance, predetermined number P
numhigher limit can try to achieve via following calculating formula:
Wherein, WCMD
timefor the regulation time limit of specifications definition, Merge
timefor merging the averaging time of two physical blocks, and ONEPAGE
rWit is the average required time of a physical page of read-write.The size of supposing each physical page in non-volatile memory chip 106 is 4K byte, and each physical blocks has 128 physical page, it is estimated Merge averaging time that will merge two physical blocks
timefor 155.8ms, and the average required time ONEPAGE of a physical page of read-write
rWfor 1.15ms.Can try to achieve predetermined number P by above-mentioned calculating formula
numhigher limit be 81.That is each physical blocks can only be carried out data writing by 81 physical page at most in the first storage area 106A.
Accordingly, when nonvolatile memory controller 104 obtain need by the first Thread 310 performed write instruction time, if this writes instruction is a certain physical blocks (being referred to as below first instance block) that data will be write in the first storage area 106A, first the Memory Management Unit 204 in nonvolatile memory controller 104 judges whether the physical page of predetermined number in first instance block is fully written so.
If the physical page of predetermined number is fully written in first instance block, Memory Management Unit 204 can select in addition a physical blocks (being referred to as below second instance block) in order to data writing from the first storage area 106A.It must be emphasized that at this, in the physical page of predetermined number has been fully written in first instance block, in first instance block, still have the physical page of part not to be written into data.And in the time that data are write second instance block by the first Thread 310, with the quick physical page of the part in second instance block and part at a slow speed physical page carry out data writing.
If but the physical page of predetermined number is not yet fully written in first instance block, Memory Management Unit 204 then judges that whether the physical page of predetermined number also has the sufficient space can be in order to data writing.If so, the first Thread 310 just writes to data first instance block.That is, data are write in predetermined number physical page and also do not have data to write part.If but the insufficient space of predetermined number physical page, in 204 physical blocks that can comprise from the first storage area 106A of Memory Management Unit, select in addition a physical blocks (for example second instance block), and then allow the first Thread 310 that data are write to second instance block.
In this exemplary embodiment, when host computer system 1000 assigned need be carried out by the first Thread 310 write instruction time, Memory Management Unit 204 can only have to limit each physical blocks the physical page of predetermined number to can be used to the mode of data writing, avoids the situation that merges two physical blocks to produce.Accordingly, if during the first Thread 310 execution write instruction, host computer system 1000 is assigned the instruction that writes that need be carried out by the second Thread 320, even if writing instruction meeting, this follow the merging of two physical blocks, the second Thread 320 to complete also can not exceed this T.T. that writes instruction the specifications of the digital memory card of microampere to define a regulation time limit that writes instruction.
Fig. 7 is the process flow diagram that illustrates non-volatility memorizer access method according to above-mentioned exemplary embodiment.Refer to Fig. 7, first as shown in step 710, physical blocks contained non-volatile memory chip 106 is divided into can be by the first storage area 106A of 310 accesses of the first Thread and can be by the second storage area 106B of 320 accesses of the second Thread.
Then, in step 720, what Receiving Host system 1000 transmitted writes instruction, and this writes that instruction wants to write is the first instance block in the first storage area 106A.
As shown in step 730, Memory Management Unit 204 judges whether the physical page of predetermined number in first instance block is fully written.If the physical page of predetermined number is fully written,, as shown in step 740, Memory Management Unit 204 is selected the second instance block in the first storage area 106A and then is allowed the first Thread 310 carry out data writing.
If the physical page of predetermined number is not yet fully written in first instance block, in step 750, Memory Management Unit 204 judges whether the physical page of predetermined number in first instance block has the sufficient space can data writing.If space is enough,, as shown in step 760, data are write to first instance block by the first Thread 310.If otherwise insufficient space,, as shown in step 770, data are write to second instance block by the first Thread 310.
By the way, Memory Management Unit 204 avoids the first Thread 310 in the time that execution writes instruction, to produce the situation that needs to merge two physical blocks, wait for thereby reduce the second Thread 320 time that the first Thread 310 completes write activity, to have guaranteed that a time that writes instruction can not exceed the regulation time limit of the specifications institute specification of the digital memory card of microampere.
In sum, non-volatility memorizer access method, system and nonvolatile memory controller proposed by the invention be by controlling the size of data-moving unit of a Thread, and then guarantee that specifications that can be less than the digital memory card of microampere T.T. that two Threads successively write data non-volatile memory chip define each and write completing the time limit of instruction.
But, the foregoing is only the preferred embodiments of the present invention, when not limiting scope of the invention process with this, the simple equivalence of generally doing according to the present patent application the scope of the claims and invention description content changes and modifies, and all still remains within the scope of the patent.
In addition, arbitrary exemplary embodiment of the present invention or claim must not reached whole object disclosed in this invention or advantage or feature.In addition, summary part and title are only for the use of auxiliary patent document search, are not used for limiting interest field of the present invention.
Claims (12)
1. a non-volatility memorizer access method, for the multiple physical blocks in access one non-volatile memory chip, wherein each these physical blocks has multiple physical page, and this non-volatility memorizer access method comprises:
Receive the new data more for upgrading data that are stored in a first instance block, wherein this first instance block comprises multiple special entity pages, the plurality of special entity page comprises a first instance page and multiple second instance page, and described data are stored in this first instance page and described multiple second instance page stores valid data;
Judge whether this first instance block has sufficient space to write this more new data and this valid data; And
When having sufficient space, this first instance block writes this more when new data and this valid data, by this more new data write to one the 3rd physical page of this first instance block and these valid data copied to multiple the 4th physical page of this first instance block from described multiple second instance pages
Wherein these special entity pages are a data-moving unit, and the quantity of these special entity pages is more than or equal to 2, and are less than the physical page sum that each these physical blocks of this non-volatile memory chip comprise respectively.
2. non-volatility memorizer access method as claimed in claim 1, also comprises:
When this first instance block writes this more when new data and this valid data without sufficient space, select an empty second instance block from these physical blocks;
By these valid data that copy from this first instance block write to this second instance block and by this more new data write in this second instance block.
3. non-volatility memorizer access method as claimed in claim 2, wherein these physical page comprise multiple quick physical page and multiple physical page at a slow speed, wherein this more new data and this valid data are written into these physical page at a slow speed of these quick physical page of part and part in this first instance block or this second instance block.
4. non-volatility memorizer access method as claimed in claim 2, also comprises:
Dividing these physical blocks is one first storage area and one second storage area, and wherein this first instance block and this second instance block belong to this first storage area.
5. non-volatility memorizer access method as claimed in claim 4, also comprises:
Order write this more new data and this valid data also then move one the 3rd physical blocks all physical page to the 4th physical blocks be less than or equal to a regulation time limit T.T., wherein the 3rd physical blocks and the 4th physical blocks belong to this second storage area.
6. a nonvolatile memory controller, be disposed in a non-volatility memorizer access device, this non-volatility memorizer access device comprises a non-volatile memory chip, wherein this non-volatile memory chip comprises multiple physical blocks, and each these physical blocks has multiple physical page, and this nonvolatile memory controller comprises:
One microprocessor unit;
One non-volatility memorizer interface unit, couples this microprocessor unit, in order to be coupled to this non-volatile memory chip;
One host interface unit, is coupled to this microprocessor unit, in order to be coupled to a host computer system; And
One Memory Management Unit, is coupled to this microprocessor unit,
Wherein, this Memory Management Unit receives the new data more for upgrading data that are stored in a first instance block, wherein this first instance block comprises multiple special entity pages, the plurality of special entity page comprises a first instance page and multiple second instance page, described data are stored in this first instance page and described multiple second instance page stores valid data
Wherein, this Memory Management Unit judges whether this first instance block has sufficient space to write this more new data and this valid data,
When having sufficient space, this first instance block writes this more when new data and this valid data, this Memory Management Unit by this more new data write to one the 3rd physical page of this first instance block and these valid data copied to multiple the 4th physical page of this first instance block from described multiple second instance pages
Wherein these special entity pages are a data-moving unit, and the quantity of these special entity pages is more than or equal to 2, and are less than the physical page sum that each these physical blocks of this non-volatile memory chip comprise respectively.
7. nonvolatile memory controller as claimed in claim 6, wherein when this first instance block writes this more when new data and this valid data without sufficient space, this Memory Management Unit is selected an empty second instance block from these physical blocks, by these valid data that copy from this first instance block write to this second instance block and by this more new data write in this second instance block.
8. nonvolatile memory controller as claimed in claim 7, wherein these physical page comprise multiple quick physical page and multiple physical page at a slow speed, wherein this more new data and this valid data are written into these physical page at a slow speed of these quick physical page of part and part in this first instance block or this second instance block.
9. nonvolatile memory controller as claimed in claim 7, wherein these physical blocks are divided into one first storage area and one second storage area, and this first instance block and this second instance block belong to this first storage area.
10. a non-volatility memorizer access system, comprising:
One non-volatile memory chip, has multiple physical blocks, and each these physical blocks has multiple physical page;
A connector, in order to be coupled to a host computer system; And
One nonvolatile memory controller, is coupled to this non-volatile memory chip and this connector,
Wherein, this nonvolatile memory controller receives the new data more for upgrading data that are stored in a first instance block, wherein this first instance block comprises multiple special entity pages, the plurality of special entity page comprises a first instance page and multiple second instance page, described data are stored in this first instance page and described multiple second instance page stores valid data
Wherein, this nonvolatile memory controller judges whether this first instance block has sufficient space to write this more new data and this valid data,
When having sufficient space, this first instance block writes this more when new data and this valid data, this nonvolatile memory controller by this more new data write to one the 3rd physical page of this first instance block and these valid data copied to multiple the 4th physical page of this first instance block from described multiple second instance pages
Wherein these special entity pages are a data-moving unit, and the quantity of these special entity pages is more than or equal to 2, and are less than the physical page sum that each these physical blocks of this non-volatile memory chip comprise respectively.
11. non-volatility memorizer access systems as claimed in claim 10, wherein when this first instance block writes this more when new data and this valid data without sufficient space, this nonvolatile memory controller is selected an empty second instance block from these physical blocks, by these valid data that copy from this first instance block write to this second instance block and by this more new data write in this second instance block.
12. non-volatility memorizer access systems as claimed in claim 11, wherein these physical page comprise multiple quick physical page and multiple physical page at a slow speed, wherein this more new data and this valid data are written into these physical page at a slow speed of these quick physical page of part and part in this first instance block or this second instance block.
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| TW200903492A (en) * | 2007-05-21 | 2009-01-16 | Sandisk Il Ltd | Systems and methods for optimizing page selection in flash-memory devices |
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