CN102117238A - Universal method and platform for verifying compatibility between intellectual property (IP) core and advanced microcontroller bus architecture (AMBA) bus interface - Google Patents
Universal method and platform for verifying compatibility between intellectual property (IP) core and advanced microcontroller bus architecture (AMBA) bus interface Download PDFInfo
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Abstract
The invention provides a universal platform of verifying compatibility between an intellectual property (IP) core and an advanced microcontroller bus architecture (AMBA) bus interface, which comprises a functional simulation tool, an AMBA bus infrastructure, a third-party verification IP core, a controller, a driver, a stimulus, a checker, an advanced peripheral bus (APB) bridge, an advanced high-performance bus (AHB) master interface, an AHB slave interface and an APB slave interface, wherein all the modules are connected to form an integrated coordinating verification environment by adopting a verification component and hierarchical packaging and interconnections ways provided by a SystemVerilog language and advanced verification methodology (AVM). The platform can verify the compatibility of different types of IP core interfaces, and the development time and cost of the verification platform and a verification method are reduced. The invention also provides the universal method for verifying the compatibility between the IP core and the AMBA bus interface. In the method, excitation is produced more normatively, scientifically and accurately, unnecessary iteration is reduced and the verification time is shortened.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, be specifically related to compatible generic validation platform of a kind of IP kernel and AMBA bus interface and verification method.
Background technology
Along with the VLSI (very large scale integrated circuit) technology to the striding forward of 45nm, the SoC design complexities significantly promotes, the multiplexing main path that realizes the SoC design that also become of IP kernel.At present, 85% IC design corporation is in the process of carrying out the SoC design, and all can adopt IP reuse is main predetermined module.
In the SoC design multiplexing based on IP kernel, the compatibility that guarantees communications protocol on IP interface and the sheet is the effective means that SoC design reuse methodology solves the integrated difficult problem of SoC, and therefore, it is particularly crucial that the design of on-chip bus and checking become.There is multiple on-chip bus standard at present in the industry, mainly contains: OCP, AMBA, CoreConnect, Wishbone etc.Wherein the AMBA on-chip bus has become the main standard that SoC makes up and the IP storehouse is developed, and about in the market 70% reusable numeral IP kernel uses the AMBA on-chip bus.
As shown in Figure 1, AMBA on-chip bus framework comprises high performance system bus--peripheral bus of AHB and low-power consumption--APB.System bus is be responsible for to connect such as ARM high-speed memory, high-speed interface on embedded type CPU, DMA, the sheet, and high speed IP kernel such as important coprocessor, video/audio encoding and decoding, peripheral bus then is to be used for connected system peripheral element and low speed IP kernel, the relative AHB of APB agreement is comparatively simple, meets AHB by bridging.
Wherein ahb bus has following characteristics:
Single clock is supported 8～1024bit transmission along synchronous triggering;
Non-tristate bus line, synchronization have only a main equipment to take bus concurrency to play data transmission;
Support a plurality of master/slave arrangements, finish the handing-over of main device bus control in the monocycle;
Stream line operation supports data burst transmission (Burst transfer) and data to cut apart transmission (Split transaction);
Support bus arbitration, bus request, bus are authorized and handshake mechanisms such as lock bus;
Support non-fixed length transmission, segment transmissions and transmission back-to-back.
We can say the peripheral bus (APB) of the existing simple possible of AMBA2.0 agreement, function complexity, system bus (AHB) that throughput is high are arranged again.The complicated various of AMBA bus brought great challenge for comprehensive checking of I P nuclear AMBA bus interface.
Though AMBA bus inferface protocol function complexity than being easier to formalization, is fit to definition coverage rate model, carries out the function coverage analysis.The function coverage analysis is exactly at first to find out the zone that also is not capped in the coverage rate model, find out then next step need at the process of functional verification demand.The agreement characteristics of AMBA bus are fit to use third party's instrument and checking IP to set up complete protocol testing mechanism very much, in the condition and range of constraint, carry out random test simultaneously, verify various boundary conditions, ordinal relation, function coverage is made it.
Current, general verification platform often only at certain interface type customized development, is not considered versatility, and different interface types needs different verification platforms, has increased the development time and the cost of verification platform.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of and can verify a plurality of IP kernels and AMBA bus interface compatibility verification platform and verification method.
For solving above technical matters, the invention provides the compatible generic validation platform of a kind of IP kernel and AMBA bus interface, comprise the functional simulation instrument, AMBA bus underlying basis framework (Infrastructure), the third-party authentication IP kernel, control module (Controller), driver module (Driver), excitation generation module (Stimulus), verification module (Checker), APB bridge, AHB master interface, AHB slave interface and APB slave interface
Checking assembly that described verification platform employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module, the SystemVerilog language provides natural generation mechanism at random of asserting authentication mechanism and belt restraining, what carry that the AVM verification methodology can verify each abstraction hierarchy asserts checking at random, verification efficiency and accuracy rate improve greatly
Described AMBA bus underlying basis framework is supported the handshake mechanism and the various transmission mode of AMBA bus protocol, and all functions of AMBA bus are provided, and ensures each master-slave equipment unimpeded swap data on bus,
Described third-party authentication IP kernel, the function coverage model of necessary AMBA bus protocol reference set is provided and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation, QVL third party IP storehouse, embedded advanced person asserts testing mechanism, can accomplish seamless AMBA bus timing inspection, and AMBA bus functionality coverage rate analysis
Described control module is collected the sequential inspection and the coverage rate information of each QVL checking IP kernel, and at the intelligentized not sensitive factor of covering function item that excites of high level of abstraction,
Described driver module is responsible for the test procedure of high level of abstraction is translated as the concrete RTL interface excitation vector of protocol compliant requirement and sends to tested interface,
Described excitation generation module produces the random test program of belt restraining, is used for producing the arbitrary excitation of belt restraining,
The data consistent check mechanism that described verification module provides tested interface to carry out bus transfer, and data not during normal transmission the various information of accurate reporting errors data with convenient location mistake,
Described APB bridge is connected to AHB to the APB interface, and AHB master interface, AHB slave interface are connected the various IP kernels that have AHB master interface, AHB slave interface and APB slave interface with APB slave interface.
Preferably, in above-mentioned IP kernel and the compatible generic validation platform of AMBA bus interface, described functional simulation instrument is the Questa of a Mentor company front-end simulation instrument.
Preferably, in above-mentioned IP kernel and the compatible generic validation platform of AMBA bus interface, described AMBA bus underlying basis framework adopts 3 grades of flowing water designs, and supports the bus handshake mechanism and the various transmission mode of AMBA2.0 agreement fully.
Preferably, in above-mentioned IP kernel and the compatible generic validation platform of AMBA bus interface, the QVL storehouse that described third-party authentication IP kernel is a Mentor company.
The present invention also provides a kind of IP kernel and the compatible generic validation method of AMBA bus interface, it is characterized in that described verification method may further comprise the steps:
(1) adopt script, write the master operating station of the compatible generic validation of an IP kernel and AMBA bus interface, this operator's console is responsible for the operating process control to emulation tool;
(2) foundation is verified working directory and is changed catalogue work over to;
(3) call in and compile each work package of verification platform;
(4) excitation of generation belt restraining comprises that checking has just begun the arbitrary excitation of the belt restraining of the random test program generation of excitation generation module generation belt restraining in artificial excitation of importing and the proof procedure;
(5) the data consistent check mechanism that verification module provides tested interface to carry out bus transfer, if data are inconsistent, then interface to be measured is revised in debugging, returns step (4) then, if data consistent then carries out the function coverage analysis by QVL;
(6) judge whether sequential meets the demands, if do not satisfy, then interface to be measured is revised in debugging, returns step (4) then;
(7) judge whether to satisfy the target coverage rate,, then verify loop ends,, then return step (4) if do not satisfy if satisfy.
The described verification platform of step (3) comprises the functional simulation instrument, AMBA bus underlying basis framework, the third-party authentication IP kernel, control module, driver module, verification module, the APB bridge, AHB master interface, AHB slave interface and APB slave interface, checking assembly that described verification platform employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module;
Described AMBA bus underlying basis framework is supported the handshake mechanism and the various transmission mode of AMBA bus protocol;
Described third-party authentication IP kernel provides the function coverage model of necessary AMBA bus protocol reference set and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation;
Described control module is collected the sequential inspection and the coverage rate information of each QVL checking IP kernel, and at the intelligentized not sensitive factor of covering function item that excites of high level of abstraction;
Described driver module is responsible for the test procedure of high level of abstraction is translated as the concrete RTL interface excitation vector of protocol compliant requirement and sends to tested interface;
Described excitation generation module produces the random test program of belt restraining, is used for producing the arbitrary excitation of belt restraining;
The data consistent check mechanism that described verification module provides tested interface to carry out bus transfer, and data not during normal transmission the various information of accurate reporting errors data with convenient location mistake;
Described APB bridge is connected to AHB to the APB interface, and AHB master interface, AHB slave interface are connected the various IP kernels that have AHB master interface, AHB slave interface and APB slave interface with APB slave interface.
In above-mentioned IP kernel and the compatible generic validation method of AMBA bus interface, the excitation of the belt restraining in the step (4) comprises the excitation of artificial input or the excitation that randomization produces, and the excitation that described randomization produces is generated by the random test program that excitation generation module in the proof procedure produces belt restraining.
Preferably, in above-mentioned IP kernel and the compatible generic validation method of AMBA bus interface, described functional simulation instrument is the Questa of a Mentor company front-end simulation instrument.
Preferably, in above-mentioned IP kernel and the compatible generic validation method of AMBA bus interface, described AMBA bus underlying basis framework adopts 3 grades of flowing water designs, and supports the bus handshake mechanism and the various transmission mode of AMBA2.0 agreement fully.
Preferably, in above-mentioned IP kernel and the compatible generic validation method of AMBA bus interface, the QVL storehouse that described third-party authentication IP kernel is a Mentor company.
Technique effect of the present invention is, by providing a kind of IP kernel and AMBA bus interface compatible generic validation platform, compare with current verification platform at certain interface type customized development, can verify dissimilar IP kernel interface compatibilities, can within a short period of time, more comprehensively finish the validation task of bus interface, reduced the development time and the cost of verification platform and verification method.Described generic validation platform and checking flow process are only avoided numerous and diverse IP kernel internal logic functional verification at the checking of AMBA bus interface.
The compatible generic validation method of IP kernel provided by the invention and AMBA bus interface, with current verification method ratio, standardization more, science, generation excitation have accurately reduced unnecessary iteration, thereby have reduced the proving time.The excitation that verification method provided by the invention also uses randomization to produce, need report according to the coverage rate that QVL produces, adjust excitation and produce code, the randomization data generation mechanism of utilization SystemVerilog language zone constraint condition adds the random data of directed about fasciculation.By continuous adjustment authentication to, iteration is used the random test of belt restraining, effectively strengthened the not test of covering space, to the coverage rate target approaches of intended target, finally reaching the objective function coverage rate with the actual functional capability coverage rate is the standard that checking finishes rapidly.
Description of drawings
Fig. 1 is an AMBA bus system framed structure.
Fig. 2 is IP kernel provided by the invention and the compatible generic validation platform of AMBA bus interface composition diagram.
Fig. 3 is an oc8051AHBmaster interface compatibility verification platform composition diagram.
Fig. 4 is the Checker fundamental diagram.
Fig. 5 is the process flow diagram of IP kernel provided by the invention and the compatible generic validation method of AMBA bus interface.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
As shown in Figure 2, the compatible generic validation platform of IP kernel provided by the invention and AMBA bus interface comprises the functional simulation instrument, AMBA bus underlying basis framework, the third-party authentication IP kernel, control module, driver module, the excitation generation module, the verification module, the APB bridge, AHB master interface, AHB slave interface and APB slave interface, checking assembly that this verification platform employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module; Checking assembly that this verification platform employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module; MBA bus underlying basis framework is supported the handshake mechanism and the various transmission mode of AMBA bus protocol; The third-party authentication IP kernel provides the function coverage model of necessary AMBA bus protocol reference set and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation; Control module is collected the sequential inspection and the coverage rate information of each QVL checking IP kernel, and at the intelligentized not sensitive factor of covering function item that excites of high level of abstraction; Driver module is responsible for the test procedure of high level of abstraction is translated as the concrete RTL interface excitation vector of protocol compliant requirement and sends to tested interface; The excitation generation module produces the random test program of belt restraining, is used for producing the arbitrary excitation of belt restraining; The data consistent check mechanism that the verification module provides tested interface to carry out bus transfer, and data not during normal transmission the various information of accurate reporting errors data with convenient location mistake; The APB bridge is connected to AHB to the APB interface, and AHB master interface, AHB slave interface are connected the various IP kernels that have AHB master interface, AHB slave interface and APB slave interface with APB slave interface.
In the present embodiment, verification platform uses Questa emulation tool and SystemVerilog language to carry AVM verification methodology structure.The SystemVerilog language is the higher level lanquage of a kind of hardware description and checking, can be used as the RTL design language, also can be used as the checking language.It not only has good homology with Verilog, can accomplish and RTL design seamless link, and have high characteristics of abstraction level, set up level of abstraction in transaction-level and solved Verilog complex time, shortcoming such as height is consuming time, code efficiency is low in checking fully.
Simultaneously we also use Mentor company QVL storehouse (Questa Verification Library) as third-party authentication IP, the function coverage model of necessary AMBA bus protocol reference set is provided and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation.
After the generic validation platform framework formed, we selected the IP kernel of a kind of oc8051 as IP to be measured (DUT).It has AMBA AHB master interface, is the promoter of bus operation.Can finish the control of bus and the kind of selecting data transmission according to the control bit of dependent instruction operation and related register.AMBA Infrastructure is except that carry oc8051 in the general-purpose platform, gone back carry Defaultmaster, two AHB master of dma controller.Simultaneously at the AHB slave end on-chip memory of having gone back carry so that the various data of oc8051 access, the concrete customization as shown in Figure 3.
This oc8051 finishes the operation with access of moving to various data in the Memory (AHB slave) by AHB master interface.AHB master has 25 functions and covers item in QVL coverage rate model, and wherein 15 is that oc8051 supports.Unsupported covering item screens in advance, and the effective like this complexity that has reduced checking makes checking have more specific aim.Xiang Rubiao 1 is checked in concrete checking.
As shown in Figure 4, we have designed a data detector (Checker) with the SystemVerilog language, its principle is: Stimulus produces a write affairs type sequence (write (address, data)), this sequence is carried out oneself's copy (copy sequence) simultaneously, former sequence is interpreted as Driver to be fit to the pumping signal of bus protocol, write out by AHB master, through storing the appropriate address of on-chip memory behind the address decoding of bus into, the then storage automatically in Checker of copy sequence; After Stimulus sends a read affairs type sequence (read (address)) of same batch in same address, Checker will originally copy sequence automatically and compare with the data from the read sequence that bus is read in.Comparison result will come out with the formal representation of report.
The higher level lanquage abstract property of Checker has been liberated the data read-write operation of script based on temporal aspect.Make the consistency check of data need not to depend on sequential, but finish at the transaction layer of higher abstraction hierarchy.
The present invention also provides a kind of IP kernel and the compatible generic validation method of AMBA bus interface, it is characterized in that described verification method may further comprise the steps:
Step S11 adopts script, writes the master operating station of the compatible generic validation of an IP kernel and AMBA bus interface, and this operator's console is responsible for the operating process control to emulation tool;
Step S12 sets up the checking working directory and changes catalogue work over to;
Step S13 calls in and compiles each work package of verification platform;
Step S14, the excitation of generation belt restraining comprises that checking has just begun the arbitrary excitation of the belt restraining of the random test program generation of excitation generation module generation belt restraining in artificial excitation of importing and the proof procedure;
Step S15, the data consistent check mechanism that the verification module provides tested interface to carry out bus transfer, if data are inconsistent, then interface to be measured is revised in debugging, returns step S14 then, if data consistent then carries out the function coverage analysis by QVL;
Step S 16, judge whether sequential meets the demands, if do not satisfy, then interface to be measured is revised in debugging, returns step S14 then;
Step S17 judges whether to satisfy the target coverage rate, if satisfy, then verifies loop ends, if do not satisfy, then returns step S14.
In the present embodiment, verification platform comprises the functional simulation instrument, AMBA bus underlying basis framework, the third-party authentication IP kernel, control module, driver module, the verification module, the APB bridge, AHB master interface, checking assembly that AHB slave interface and APB slave interface employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module; AMBA bus underlying basis framework is supported the handshake mechanism and the various transmission mode of AMBA bus protocol; The third-party authentication IP kernel provides the function coverage model of necessary AMBA bus protocol reference set and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation; Control module is collected the sequential inspection and the coverage rate information of each QVL checking IP kernel, and at the intelligentized not sensitive factor of covering function item that excites of high level of abstraction; Driver module is responsible for the test procedure of high level of abstraction is translated as the concrete RTL interface excitation vector of protocol compliant requirement and sends to tested interface; The excitation generation module produces the random test program of belt restraining, is used for producing the arbitrary excitation of belt restraining; The data consistent check mechanism that the verification module provides tested interface to carry out bus transfer, and data not during normal transmission the various information of accurate reporting errors data with convenient location mistake; The APB bridge is connected to AHB to the APB interface, and AHBmaster interface, AHB slave interface are connected the various IP kernels that have AHB master interface, AHB slave interface and APB slave interface with APB slave interface.
In the present embodiment, the excitation of the belt restraining in the step (4) comprises the excitation of artificial input or the excitation that randomization produces, and the excitation that described randomization produces is generated by the random test program that excitation generation module in the proof procedure produces belt restraining.
In the present embodiment, AMBA bus underlying basis framework adopts 3 grades of flowing water designs, and support the bus handshake mechanism and the various transmission mode of AMBA2.0 agreement fully, and the functional simulation instrument is the Questa of a Mentor company front-end simulation instrument, the third-party authentication IP kernel is the QVL storehouse of Mentor company.
Before specifically verifying, need making checking plan, wherein be necessary the easy Cornercases that ignores in the emphasis consideration AMBAAHB master checking, for example:
After master authorizes bus, must carry out data transmission;
When slave inserted waiting status, master should keep address and control signal (htrans, hwrite, hsize, hburst and hprot) constant;
When the transport-type of master was busy, the address should be reacted with control signal and is the next one transmission relevant with its burst transmission;
The current address of the transmission of a SEQUENTIAL type must be relevant with last address;
Master should enter the IDLE state immediately after receiving an ERROR/RETRY/SPLIT response;
Behind the Hreset, all signals of AHB can not be X or Z;
The reconstruction inspection of Early brusttemination.
Above-mentioned Cornercases has been reflected in asserting of QVL coverage rate model check, can carry out concrete sequential inspection according to the limit testing that adds.Check that with asserting adjusting Stimulus sends various operative combination by the various coverage rate analysis that QVL obtains, farthest improve function coverage with this.
At first finish the function that the oc8051AHBmaster bus is grabbed at the checking initial stage.For this reason, specially added two AHBmaster of Defaultmater and dma controller in the verification platform, the priority orders that they take bus is followed successively by dma controller, oc8051, Defaultmaster from high to low.Can test the bus control right that oc8051 grabs Default mater successively like this, dma controller is grabbed the bus control right of oc8051.And check the correctness of sequential and function in grabbing process.
On the basis of carrying out the checking of oc8051AMBA bus compatible basic function, also carried out the randomization excitation and produced and test.Under the guidance of the coverage rate model of specifically verifying target and authentication policy, need report according to the coverage rate that QVL produces, adjust excitation and produce code, the randomization data generation mechanism of utilization SystemVerilog language zone constraint condition adds the random data of directed about fasciculation.Use the random test of belt restraining by continuous adjustment authentication to, iteration, effectively strengthened the not test of covering space, rapidly to the coverage rate target approaches of intended target.
In the time of sequence check, the Stimulus iteration is carried out the various data checks of different transport-types, by Checker, checks the consistance of data in transmission course.
At AMBA bus compatible generic validation platform, the randomization verification method of utilization coverage rate rotating band constraint has been finished the interface checking work of oc8051 AHB master in a short time by oc8051.The random test of more than 5000 belt restraining has been used in whole checking, finds mistake 11 places that oc8051 AHB master hides altogether.Formed complete coverage rate report, removed oc8051 AHB master to the unsupported part of agreement, final total effective coverage rate reaches 100%, and has effectively ensured the correctness of data transmission in the checking by the data check device.
Along with the continuous increase of SoC scale, IP reuse becomes requisite part in the SoC design.The AMBA bus has become the de facto standard of IP kernel interface interconnection.Particularly important to the compatibility verification of IP kernel AMBA bus interface in the SoC integrating process.The universality of a kind of IP kernel AMBA bus interface compatibility verification platform provided by the invention and verification method is good, preferably resolves this difficult problem.In the present embodiment, use this platform that the AHB master interface of a kind of oc 8051 is verified after, again respectively to UART (APB slave) and MPEG2 (AHB slave﹠amp; AHB master) carried out the compatibility verification of AMBA bus interface.Use this generic validation platform can within a short period of time, more comprehensively finish the validation task of bus interface.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the instructions.
Claims (9)
1. the compatible generic validation platform of IP kernel and AMBA bus interface, comprise the functional simulation instrument, AMBA bus underlying basis framework, the third-party authentication IP kernel, control module, driver module, excitation generation module and verification module, checking assembly that described verification platform employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module
Described AMBA bus underlying basis framework is supported the handshake mechanism and the various transmission mode of AMBA bus protocol,
Described third-party authentication IP kernel provides the function coverage model of necessary AMBA bus protocol reference set and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation,
Described control module is collected the sequential inspection and the coverage rate information of each QVL checking IP kernel, and at the intelligentized not sensitive factor of covering function item that excites of high level of abstraction,
Described driver module is responsible for the test procedure of high level of abstraction is translated as the concrete RTL interface excitation vector of protocol compliant requirement and sends to tested interface,
Described excitation generation module produces the random test program of belt restraining, is used for producing the arbitrary excitation of belt restraining,
The data consistent check mechanism that described verification module provides tested interface to carry out bus transfer, and data not during normal transmission the various information of accurate reporting errors data with convenient location mistake,
It is characterized in that,
Described verification platform also comprises the APB bridge, AHB master interface, AHB slave interface and APB slave interface, described APB bridge is connected to AHB to the APB interface, AHB master interface, AHB slave interface are connected the various IP kernels that have AHB master interface, AHB slave interface and APB slave interface with APB slave interface.
2. the compatible generic validation platform of IP kernel according to claim 1 and AMBA bus interface is characterized in that described functional simulation instrument is the Questa of a Mentor company front-end simulation instrument.
3. the compatible generic validation platform of IP kernel according to claim 1 and AMBA bus interface, it is characterized in that, described AMBA bus underlying basis framework adopts 3 grades of flowing water designs, and supports the bus handshake mechanism and the various transmission mode of AMBA2.0 agreement fully.
4. the compatible generic validation platform of IP kernel according to claim 1 and AMBA bus interface is characterized in that the QVL storehouse that described third-party authentication IP kernel is a Mentor company.
5. the compatible generic validation method of IP kernel and AMBA bus interface is characterized in that described verification method may further comprise the steps:
(1) adopt script, write the master operating station of the compatible generic validation of an IP kernel and AMBA bus interface, this operator's console is responsible for the operating process control to emulation tool;
(2) foundation is verified working directory and is changed catalogue work over to;
(3) call in and compile each work package of verification platform;
(4) excitation of generation belt restraining; Comprise that checking has just begun the arbitrary excitation of the belt restraining of the random test program generation of excitation generation module generation belt restraining in artificial excitation of importing and the proof procedure;
(5) the data consistent check mechanism that verification module provides tested interface to carry out bus transfer; If data are inconsistent, then interface to be measured is revised in debugging, returns step (4) then, if data consistent then carries out the function coverage analysis by QVL;
(6) judge whether sequential meets the demands, if do not satisfy, then interface to be measured is revised in debugging, returns step (4) then;
(7) judge whether to satisfy the target coverage rate,, then verify loop ends,, then return step (4) if do not satisfy if satisfy.
Verification platform comprises the functional simulation instrument described in the step (3), AMBA bus underlying basis framework, third-party authentication IP kernel, control module, driver module, verification module, APB bridge, AHBmaster interface, AHB slave interface and APB slave interface; Checking assembly that employing SystemVerilog language and AVM verification methodology are provided and stratification packing, mutual contact mode are with the interconnected integrated coordination verification environment of each module;
Described AMBA bus underlying basis framework is supported the handshake mechanism and the various transmission mode of AMBA bus protocol;
Described third-party authentication IP kernel provides the function coverage model of necessary AMBA bus protocol reference set and monitors the AMBA bus inferface protocol that occurs in the proof procedure and violate situation;
Described control module is collected the sequential inspection and the coverage rate information of each QVL checking IP kernel, and at the intelligentized not sensitive factor of covering function item that excites of high level of abstraction;
Described driver module is responsible for the test procedure of high level of abstraction is translated as the concrete RTL interface excitation vector of protocol compliant requirement and sends to tested interface;
Described excitation generation module produces the random test program of belt restraining, is used for producing the arbitrary excitation of belt restraining;
The data consistent check mechanism that described verification module provides tested interface to carry out bus transfer, and data not during normal transmission the various information of accurate reporting errors data with convenient location mistake;
Described APB bridge is connected to AHB to the APB interface, and AHB master interface, AHB slave interface are connected the various IP kernels that have AHB master interface, AHB slave interface and APB slave interface with APB slave interface.
6. the compatible generic validation method of IP kernel according to claim 5 and AMBA bus interface, it is characterized in that, the excitation of the belt restraining in the step (4) comprises the excitation of artificial input or the excitation that randomization produces, and the excitation that described randomization produces is generated by the random test program that excitation generation module in the proof procedure produces belt restraining.
7. the compatible generic validation method of IP kernel according to claim 5 and AMBA bus interface is characterized in that described functional simulation instrument is the Ques ta of a Mentor company front-end simulation instrument.
8. the compatible generic validation method of IP kernel according to claim 5 and AMBA bus interface, it is characterized in that, described AMBA bus underlying basis framework adopts 3 grades of flowing water designs, and supports the bus handshake mechanism and the various transmission mode of AMBA2.0 agreement fully.
9. the compatible generic validation method of IP kernel according to claim 5 and AMBA bus interface is characterized in that the QVL storehouse that described third-party authentication IP kernel is a Mentor company.
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