CN101917185A - D latch and 50% duty ratio tri-frequency divider using D-latch - Google Patents
D latch and 50% duty ratio tri-frequency divider using D-latch Download PDFInfo
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Abstract
The invention discloses a D latch and a 50% duty ratio tri-frequency divider using the D latch. The D latch controls the polarity of clock trigger by a phase switching control module and controls a data input and output module to output data signals or controls a data latching module to latch and output data signals. By the invention, both the raising edge and the falling edge of a clock can trigger the D latch; the D latches are connected to form a tri-frequency divider for outputting tri-frequency division signals having 50% duty ratio.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to 50% duty ratio tri-frequency divider of a kind of D-latch and this D-latch of application.
Background technology
Latch is a kind of storage unit circuit of paired pulses level-sensitive, they can be under the effect of specific input pulse level the change state.Latch is not when latch data, and the signal of output changes with input signal, and is the same by a buffer with regard to image signal, does the time spent in case latch signal rises to latch, and then data are lockable, and input signal is inoperative.Latch, temporary signal exactly to keep certain level state.
In traditional D-latch, the rising edge of input clock signal or trailing edge can trigger it, can't realize that rising edge of clock signal and trailing edge all can trigger it.In the application of some circuit, for example the odd number of 50% duty ratio time frequency dividing circuit will inevitably require the rising edge and the trailing edge of input clock signal all can trigger it, with the odd number time frequency division requirement that realizes 50% duty ratio.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of D-latch and has used 50% duty ratio tri-frequency divider of this D-latch, with the purpose that realizes that rising edge clock and trailing edge all can trigger D-latch, and provide the tri-frequency divider of 50% duty ratio, technical scheme is as follows:
A kind of D-latch comprises:
The reference voltage conversion and the electric current supply module that link to each other with reference voltage input terminal; Described reference voltage input signal provides circuit required electric current through reference voltage conversion and electric current supply module;
The level switch module that links to each other with phase place switching controls input; Described reference voltage conversion is connected with described level switch module with the electric current supply module;
The phase switching module that is connected with described level switch module; Phase place switching controls input signal converts suitable level to, the control phase handover module through behind the described level switch module;
By the clock input module that described reference voltage is changed and the electric current supply module links to each other with the differential clock signal input; Described clock input module is connected with described phase switching module; The polarity that described phase switching module decision clock triggers;
Data input/output module that is connected with described phase switching module and data latching module respectively; Described data input/output module is connected with the differential data signals input; Described phase switching module control data input/output module output clock triggers pairing data-signal constantly, and perhaps control data latch module latch clock triggers pairing data-signal of last clock and output.
Preferably, described level switch module comprises: the first level conversion submodule and the second level conversion submodule;
Described phase place switching controls input signal is controlled the first level conversion submodule and the second level conversion submodule, realizes level conversion.
Preferably, described phase switching module comprises: the first phase place switching submodule, the second phase place switching submodule, third phase position switching submodule and the 4th phase place switching submodule;
The described first phase place switching submodule is connected with the described first level conversion submodule respectively with the second phase place switching submodule; Described first level conversion submodule control determines the polarity that clock triggers by the described first phase place switching submodule and the second phase place switching submodule;
Described third phase position switching submodule is connected with the described second level conversion submodule respectively with the 4th phase place switching submodule; Described second level conversion submodule control determines the polarity that clock triggers by described third phase position switching submodule and the 4th phase place switching submodule;
The described first phase place switching submodule is connected with described data input/output module respectively with the second phase place switching submodule;
Described third phase position switching submodule is connected with described data latching module respectively with the 4th phase place switching submodule.
Preferably, described clock input module comprises: first clock input submodule and second clock input submodule;
Described first clock input submodule is connected with the 4th phase place switching submodule with the described first phase place switching submodule respectively;
Described second clock input submodule is connected with third phase position switching submodule with the described second phase place switching submodule respectively;
Described differential clocks input signal is controlled first clock input submodule and second clock input submodule, finishes clock signal input and current offset.
A kind of tri-frequency divider of 50% duty ratio comprises three D-latchs as claimed in claim 1, is respectively first order D-latch, second level D-latch and third level D-latch;
The differential clocks input signal of described first order D-latch, second level D-latch and third level D-latch is a homophase;
Described first order D-latch, second level D-latch and the reference voltage input terminal of third level D-latch are connected;
The differential data input (d2p, d2n) of the difference output end of described first order D-latch (z1p, z1n) and described second level D-latch is with being connected, and with differential phase switching controls input (phi3p, phi3n) anti-phase connection of described third level D-latch;
The difference output end of described second level D-latch (z2p, z2n) is connected together with the differential data input (d3p, d3n) of described third level D-latch, and is connected together with the differential phase switching controls input (phi1p, phi1n) of described first order D-latch;
Differential data input (d1p, d1n) the anti-phase connection of the difference output end of described third level D-latch (z3p, z3n) and described first order D-latch, and with differential phase switching controls input (phi2p, phi2n) anti-phase connection of described second level D-latch;
Described first order D-latch, second level D-latch and third level D-latch, it is opposite that the clock of two D-latchs of adjacent connection triggers polarity;
The clock that the differential phase switching controls input signal of described D-latch is controlled this D-latch triggers polarity.
By using above technical scheme, by the polarity of phase place switching controls module controls decision clock triggering, and control is by data input/output module outputting data signals, perhaps by control data latch module latch data signal and output.D-latch provided by the invention has realized that rising edge clock and trailing edge all can trigger it, and utilizes D-latch provided by the invention to connect to form tri-frequency divider, exports the three frequency division signal of 50% duty ratio.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do simple the introduction to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The structural representation of the D-latch that Fig. 1 is provided for the embodiment of the invention one;
The structural representation of the D-latch that Fig. 2 is provided for the embodiment of the invention two;
The circuit diagram of the D-latch that Fig. 3 is provided for the embodiment of the invention two;
The structural representation of 50% duty ratio tri-frequency divider that Fig. 4 is provided for the embodiment of the invention three;
Fig. 5 imports and the oscillogram of exporting for the clock of the tri-frequency divider that the embodiment of the invention three is provided.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Embodiment one:
The structural representation of the D-latch that Fig. 1 provides for the embodiment of the invention one.
The reference voltage conversion links to each other with reference voltage input terminal with electric current supply module 101, the reference voltage input signal is through reference voltage conversion and electric current supply module 101, provide circuit required electric current, level switch module 102 is connected with phase place switching controls input, the reference voltage conversion is connected with described level switch module 102 with electric current supply module 101, phase switching module 103 is connected with level switch module 102, phase place switching controls input signal is through behind the level switch module, convert suitable level to, control phase handover module 103, the differential clocks input is connected with clock input module 104, clock input module 104 is connected with phase switching module 103 with electric current supply module 101 with the reference voltage conversion respectively, the differential clocks input signal is behind oversampling clock input module 104, polarity by phase switching module 103 control decision clocks triggerings, data input/output module 105 is connected with phase switching module 103 respectively with data latching module 106, the differential data input is connected with data input/output module 105, phase switching module 103 control data input/output modules 105 output clocks trigger pairing data-signal constantly, and perhaps control data latch module 106 latch clocks trigger the data-signal and the output of last clock correspondence.
The D-latch that the embodiment of the invention one provides, behind phase place switching controls input signal process level switch module, the differential clocks input signal is behind the oversampling clock input module, common control phase handover module, the polarity that phase switching module control decision clock triggers, realize that rising edge triggers or trailing edge triggers, and control data input/output module outputting data signals, perhaps control data latch module latch data signal and output.
Embodiment two:
Referring to Fig. 2, the structural representation of the D-latch that provides for the embodiment of the invention two.
The specific implementation of the D-latch that the embodiment of the invention two is provided describes below, referring to Fig. 3, is the circuit diagram of D-latch.A power supply Vdd is arranged in the circuit, a ground Vss, two clock difference are imported clkp and clkn, and two data difference are imported d1p and d1n, and two phase place switching controls are imported phip and phin, a Voltage Reference input vref, two difference outputs z1p, z1n.Each device annexation of circuit is as follows: the base stage of transistor Q1 links to each other with the emitter of transistor Q9, the collector electrode of Q11 and the base stage of Q4 respectively, the emitter of transistor Q1 links to each other with the collector electrode of transistor Q13 and the emitter of Q2 respectively, and the collector electrode of transistor Q1 links to each other with the emitter of transistor Q5, the emitter of Q6 and the collector electrode of Q3 respectively.The base stage of transistor Q2 links to each other with the emitter of transistor Q10, the collector electrode of Q12 and the base stage of Q3 respectively, and the collector electrode of transistor Q2 links to each other with the emitter of transistor Q7, the emitter of Q8 and the collector electrode of Q4 respectively.The emitter of transistor Q3 links to each other with the emitter of transistor Q4 and the collector electrode of Q14.The base stage of transistor Q5 links to each other with differential data input d1p, and the collector electrode of transistor Q5 links to each other with output z1n with the collector electrode of transistor Q7, the base stage of Q8, the negative pole of resistance R 1 respectively.The base stage of transistor Q6 links to each other with differential data input d1n, and the collector electrode of transistor Q6 links to each other with output z1p with the base stage of transistor Q7, the collector electrode of Q8, the negative pole of resistance R 2 respectively.The base stage of transistor Q9 links to each other with phase place switching controls input phip, and the collector electrode of transistor Q9 links to each other with power supply Vdd.The base stage of transistor Q10 links to each other with phase place switching controls input phin, and collector electrode links to each other with power supply Vdd.The base stage of transistor Q11 links to each other with the negative pole of resistance R 3, and emitter links to each other with the positive pole of resistance R 7.The base stage of transistor Q12 links to each other with the negative pole of resistance R 4, and emitter links to each other with the positive pole of resistance R 8.The base stage of transistor Q13 links to each other with the negative pole of capacitor C 1 and the negative pole of resistance R 5 respectively, and the emitter of transistor Q13 links to each other with the positive pole of resistance R 9.The base stage of transistor Q14 links to each other with the negative pole of capacitor C 2 and the negative pole of resistance R 6 respectively, and emitter links to each other with the positive pole of resistance R 10.Power supply Vdd links to each other with the positive pole of resistance R 1 and the positive pole of R2 respectively.Voltage Reference input vref links to each other with the positive pole of resistance R 3, the positive pole of R4, the positive pole of R5 and the positive pole of R6 respectively.Differential clocks input clkp links to each other with the positive pole of capacitor C 1.Differential clocks input clkn links to each other with the positive pole of capacitor C 2.Ground Vss links to each other with the negative pole of resistance R 7, the negative pole of R8, the negative pole of R9 and the negative pole of R10 respectively.
The connecting line that connecting line is marked with like-identified among Fig. 3 is represented to be connected, that is: the connecting line that indicates phiefp jointly is connected, and the connecting line that indicates phiefn jointly is connected.
Operation principle to above-mentioned D-latch is described further:
D1p is a low level when the differential data input, and d1n is a high level; Phase place switching controls input phip is a low level, and phin is a high level; Differential clocks input clkp is a low level, and clkn is a high level.Transistor Q14, Q3 and Q6 conducting at this moment, then difference output z1p is a low level, z1n is a high level.
D1p is a low level when the differential data input, and d1n is a high level; Phase place switching controls input phip is a low level, and phin is a high level; Differential clocks input clkp is a high level, and clkn is a low level.This moment transistor Q13 and transistor Q2 conducting, the emission of transistor Q7 and transistor Q8 is low level very, this moment is if difference output z1p is a high level, the difference output z1n of corresponding next state is a low level, if difference output z1n is a high level, the difference output z1p of corresponding next state is a low level.Therefore the output of difference output z1p and z1n is to keep, and the data that just latch last clock cycle correspondence are constant.
Specifically can see Table 1, be similar to the 1st row and the 2nd explanation of going in the above-mentioned his-and-hers watches 1, table 1 has been listed other state about D-latch input and output, no longer describes in detail here, and " 0 " represents low level in the table 1, and " 1 " represents high level:
The input and the output state conversion table of table 1D latch
| d1p/d1n? | phip/phin? | clkp/clkn? | z1p/z1n? |
| 0/1? | 0/1? | 0/1? | 0/1? |
| 0/1? | 0/1? | 1/0? | Maintenance/maintenance |
| 0/1? | 1/0? | 0/1? | Maintenance/maintenance |
| 0/1? | 1/0? | 1/0? | 0/1? |
| 1/0? | 0/1? | 0/1? | 1/0? |
| 1/0? | 0/1? | 1/0? | Maintenance/ |
| 1/0? | 1/0? | 0/1? | Maintenance/ |
| 1/0? | 1/0? | 1/0? | 1/0? |
From table 1 state exchange of the input and output of D-latch as can be seen, clkp is 0 in the 1st row, i.e. the trailing edge of input clock, output z1p saltus step is 0; Clkp is 1 in the 4th row, i.e. the rising edge of input clock, and output z1p saltus step is 0.Thereby can illustrate that the rising edge of the input clock of the D-latch that the embodiment of the invention provides or trailing edge all can trigger it.
Embodiment three:
Referring to Fig. 4, the tri-frequency divider of 50% duty ratio that the embodiment of the invention three provides comprises the D-latch that three the foregoing descriptions provide, and is respectively first order D-latch I1, second level D-latch I2 and third level D-latch I3.
The differential clocks input signal of first order D-latch I1, second level D-latch I2 and third level D-latch I3 is a homophase, and first order D-latch I1, second level D-latch I2 are connected with the reference voltage input terminal vref of third level D-latch I3.Difference output end z1p, the z1n of first order D-latch I1 are connected together with d2n with the differential data input d2p of second level D-latch I2, and are connected with phi3n is anti-phase with the differential phase switching controls input phi3p of third level D-latch I3; Difference output end z2p and the z2n of second level D-latch I2 are connected together with d3n with the differential data input d3p of third level D-latch I3, and are connected together with phi1n with the differential phase switching controls input phi1p of first order D-latch I1; Difference output end z3p and the z3n of third level D-latch I3 are connected with d1n is anti-phase with the differential data input d1p of first order D-latch I1, and are connected with phi2n is anti-phase with the differential phase switching controls input phi2p of second level D-latch I2.
The connecting line that connecting line is marked with like-identified among Fig. 4 is represented to be connected, that is: the connecting line that indicates q1p, q1n respectively jointly is connected respectively, the difference output of expression first order D-latch I1; The connecting line that indicates q2p, q2n respectively jointly is connected respectively, the difference output of expression second level D-latch I2; The connecting line that indicates q3p, q3n respectively jointly is connected respectively, the difference output of expression third level D-latch I3.
Referring to Fig. 5, the oscillogram of clock input with the output of three 50% duty ratio tri-frequency divider is provided for the embodiment of the invention, how to obtain below in conjunction with the 50% duty ratio three frequency division signal of the output q1p of table 1 explanation first order D-latch I1.Need to prove: the state transition graph of table 1 has 2 to keep the output of 0 states, and 2 keep the output of 1 states, and 2 saltus steps are that 0 output and two saltus steps are 1 output.In the tri-frequency divider of correspondence for the connected mode of Fig. 4, the state exchange output of first order D-latch I1 and third level D-latch I3 is the same, in the correspondence table 1 the 2nd, 3,4,5,6 and 7 row, the 1st, 2,3,6,7 and 8 row in the state exchange output correspondence table 1 of first order D-latch I2.
When the difference output q2p of second level D-latch I2 is a low level, when the difference output q3p of third level D-latch I3 is low level, the differential data input d1p of first order D-latch I1 is that high level and phase place switching controls input phi1p are low level, if descend clock along triggering this moment, table look-up 1 the 5th the row, it is 1 that the difference of first order D-latch I1 output q1p answers saltus step, this just in time with Fig. 5 in clock CLK1 trailing edge clock trigger before difference output q2p and q3p state and to trigger the state of back difference output q1p corresponding; If rise clock along triggering this moment, table look-up 1 the 6th the row, the output q1p of first order D-latch I1 should remain 1, this just in time with Fig. 5 in clock CLK2 trailing edge clock trigger before difference output q2p and q3p state and to trigger the state of back difference output q1p corresponding.
When the difference output q2p of second level D-latch I2 is a high level, when the difference output q3p of third level D-latch I3 is low level, the differential data input d1p of first order D-latch I1 is that high level and phase place switching controls input phi1p are high level, if descend clock along triggering this moment, 1 the 7th row of tabling look-up, the difference of first order D-latch I1 output q1 should remain 1.This just in time with Fig. 5 in clock CLK3 trailing edge clock trigger before the state of difference output q2p and q3p, and the state correspondence that triggers back difference output q1p.
When the difference output q2p of I2 is a high level, when the difference output q3p of I3 is high level, the differential data input d1p of I1 is that low level and phase place switching controls input phi1p are high level, if rise clock along triggering this moment, table look-up 1 the 4th the row, it is 0 that the difference of I1 output q1p answers saltus step, this just in time with Fig. 5 in clock CLK4 trailing edge clock trigger before the state of difference output q2p and q3p, and the state correspondence that triggers back difference output q1p; If descend clock along triggering this moment, 1 the 3rd row of tabling look-up, the output q1p of I1 should remain 0.This just in time with Fig. 5 in clock CLK5 trailing edge clock trigger before the state of difference output q2p and q3p, and the state correspondence that triggers back difference output q1p.
When the difference output q2p of I2 is a low level, when the difference output q3p of I3 was high level, the differential data input d1p of I1 was that low level and phase place switching controls input phi1p are low level, if rise clock along triggering this moment, 1 the 2nd row of tabling look-up, the difference of I1 output q1p should remain 0.This just in time with Fig. 5 in clock CLK6 trailing edge clock trigger before the state of difference output q2p and q3p, and the state correspondence that triggers back difference output q1p.
The difference that in like manner can obtain second level D-latch I2 is exported the 50% duty ratio three frequency division signal of the difference output q3p of q2p and third level D-latch I3.The difference output q2n of difference output q1n, the second level D-latch I2 of same first order D-latch I1 and the difference output q3n of third level D-latch I3 also are 50% duty ratio three frequency division signal.
As can be seen, the output of first order D-latch I1, second level D-latch I2 and third level D-latch I3 is the three frequency division of input clock, and duty ratio is 50%.When the rising edge of one of them D-latch at clock triggers, level D-latch in back triggers at the trailing edge of clock so, this is to switch input and back level data output by the phase place of every grade of D-latch among Fig. 4, the polarity decision of data output and back level data input annexation.
In several embodiment that the application provided, should be understood that disclosed method not surpassing in the application's the spirit and scope, can realize in other way.Current embodiment is a kind of exemplary example, should be as restriction, and given particular content should in no way limit the application's purpose.For example, the division of described unit or subelement only is that a kind of logic function is divided, and during actual the realization other dividing mode can be arranged, and for example a plurality of unit or a plurality of subelement combine.In addition, a plurality of unit can or assembly can in conjunction with or can be integrated into another system, or some features can ignore, or do not carry out.
In addition, the schematic diagram of the different embodiment of institute's tracing device, in the scope that does not exceed the application, can be integrated with other system or module.Another point, the shown or coupling each other discussed or directly to be coupled or to communicate to connect can be by some interfaces, the indirect coupling of device or unit or communicate to connect can be electrically, machinery or other form.
The above only is the specific embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (5)
1. a D-latch is characterized in that, comprising:
The reference voltage conversion and the electric current supply module that link to each other with reference voltage input terminal; Described reference voltage input signal provides circuit required electric current through reference voltage conversion and electric current supply module;
The level switch module that links to each other with phase place switching controls input; Described reference voltage conversion is connected with described level switch module with the electric current supply module;
The phase switching module that is connected with described level switch module; Phase place switching controls input signal converts suitable level to, the control phase handover module through behind the described level switch module;
By the clock input module that described reference voltage is changed and the electric current supply module links to each other with the differential clock signal input; Described clock input module is connected with described phase switching module; The polarity that described phase switching module decision clock triggers;
Data input/output module that is connected with described phase switching module and data latching module respectively; Described data input/output module is connected with the differential data signals input; Described phase switching module control data input/output module output clock triggers pairing data-signal constantly, and perhaps control data latch module latch clock triggers pairing data-signal of last clock and output.
2. D-latch according to claim 1 is characterized in that, described level switch module comprises: the first level conversion submodule and the second level conversion submodule;
Described phase place switching controls input signal is controlled the first level conversion submodule and the second level conversion submodule, realizes level conversion.
3. D-latch according to claim 2 is characterized in that, described phase switching module comprises: the first phase place switching submodule, the second phase place switching submodule, third phase position switching submodule and the 4th phase place switching submodule;
The described first phase place switching submodule is connected with the described first level conversion submodule respectively with the second phase place switching submodule; The described first level conversion submodule is controlled the described first phase place switching submodule and the second phase place switching submodule, the polarity that the decision clock triggers;
Described third phase position switching submodule is connected with the described second level conversion submodule respectively with the 4th phase place switching submodule; The described second level conversion submodule is controlled described third phase position switching submodule and the 4th phase place switching submodule, the polarity that the decision clock triggers;
The described first phase place switching submodule is connected with described data input/output module respectively with the second phase place switching submodule;
Described third phase position switching submodule is connected with described data latching module respectively with the 4th phase place switching submodule.
4. D-latch according to claim 3 is characterized in that, described clock input module comprises: first clock input submodule and second clock input submodule;
Described first clock input submodule is connected with the 4th phase place switching submodule with the described first phase place switching submodule respectively;
Described second clock input submodule is connected with third phase position switching submodule with the described second phase place switching submodule respectively;
Described differential clocks input signal is controlled first clock input submodule and second clock input submodule, finishes clock signal input and current offset.
5. the tri-frequency divider of a duty ratio is characterized in that, comprises three D-latchs as claimed in claim 1, is respectively first order D-latch, second level D-latch and third level D-latch;
The differential clocks input signal of described first order D-latch, second level D-latch and third level D-latch is a homophase;
Described first order D-latch, second level D-latch and the reference voltage input terminal of third level D-latch are connected;
The differential data input (d2p, d2n) of the difference output end of described first order D-latch (z1p, z1n) and described second level D-latch is with being connected, and with differential phase switching controls input (phi3p, phi3n) anti-phase connection of described third level D-latch;
The difference output end of described second level D-latch (z2p, z2n) is connected together with the differential data input (d3p, d3n) of described third level D-latch, and is connected together with the differential phase switching controls input (phi1p, phi1n) of described first order D-latch;
Differential data input (d1p, d1n) the anti-phase connection of the difference output end of described third level D-latch (z3p, z3n) and described first order D-latch, and with differential phase switching controls input (phi2p, phi2n) anti-phase connection of described second level D-latch;
Described first order D-latch, second level D-latch and third level D-latch, it is opposite that the clock of two D-latchs of adjacent connection triggers polarity;
The clock that the differential phase switching controls input signal of described D-latch is controlled this D-latch triggers polarity.
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| JP2003243970A (en) * | 2002-02-15 | 2003-08-29 | Matsushita Electric Ind Co Ltd | Double edge trigger type flip-flop circuit |
| CN1981441A (en) * | 2004-04-02 | 2007-06-13 | 卡本研究有限公司 | Phase frequency detector with anovel D flip flop |
| US20070013424A1 (en) * | 2005-07-18 | 2007-01-18 | Padaparambil Muralikumar A | Differential dual-edge triggered multiplexer flip-flop and method |
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| CN101917185B (en) | 2012-05-09 |
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