CN101847634A - Integration component of PMOS (P-channel Metal Oxide Semiconductor) transistor and Schottky diode - Google Patents
Integration component of PMOS (P-channel Metal Oxide Semiconductor) transistor and Schottky diode Download PDFInfo
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- CN101847634A CN101847634A CN200910127931A CN200910127931A CN101847634A CN 101847634 A CN101847634 A CN 101847634A CN 200910127931 A CN200910127931 A CN 200910127931A CN 200910127931 A CN200910127931 A CN 200910127931A CN 101847634 A CN101847634 A CN 101847634A
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Abstract
The invention provides an integration component of a PMOS (P-channel Metal Oxide Semiconductor) transistor and a Schottky diode, comprising a PMOS transistor and a Schottky diode, wherein the PMOS transistor comprises a grid electrode, a source electrode, a drain electrode and a channel area between the source electrode and the drain electrode, wherein the source electrode, the drain electrode and the channel area are arranged in a matrix and a parasitic diode is formed between the drain electrode and the channel area; the Schottky diode oppositely connected with the parasitic diode in series is arranged in the matrix, one end of the Schottky diode is connected with the parasitic diode and the other end is connected with the source electrode.
Description
Technical field
The present invention relates to the integrated element of a kind of PMOS transistor and Schottky diode (Schottky Diode).
Background technology
Often need use in the power control circuit by the power switch component that constitutes of Schottky diode independently of PMOS transistor AND gate independently.See also Fig. 1, PMOS transistor 14 is connected as power switch component with Schottky diode 12, comprises parasitic diode 14D in the PMOS transistor 14, is formed between the drain electrode and channel region of PMOS transistor 14.The grid of control circuit 10 control PMOS transistors 14 is to convert input voltage vin to output voltage V o.The effect of Schottky diode 12 is to be higher than under the situation of input voltage vin at output voltage V o, prevents that electric current from through parasitic diode 14D adverse current, undermining input voltage vin.
The shortcoming of above-mentioned prior art is, the PMOS transistor AND gate suitable footprint area of Schottky diode independently independently, and the series connection back increases input voltage vin to the conducting resistance (Ron) between the output voltage V o, under big current flow, can cause great power dissipation up to 0.8V even higher by the pressure drop due to this conducting resistance.
In view of this, the present invention proposes a kind of integrated element of PMOS transistor and Schottky diode promptly at above-mentioned the deficiencies in the prior art, with the area that reduces power switch component and reduce its conducting resistance.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art and defective, propose a kind of integrated element of PMOS transistor and Schottky diode, this integrated element can be plane formula or ditch mortise formula.
For reaching above-mentioned purpose, with regard to one of them viewpoint speech, the invention provides a kind of integrated element of PMOS transistor and Schottky diode, comprise: a PMOS transistor, it comprises the channel region between grid, source electrode, drain electrode and source-drain electrode, this source electrode, drain electrode and channel region are positioned at a matrix, and form parasitic diode between this drain electrode and this channel region; And the Schottky diode with this parasitic diode differential concatenation, this Schottky diode is positioned at this matrix, and the one end is connected with this parasitic diode, and the other end is connected with this source electrode.
In a preferable enforcement kenel, this Schottky diode comprises identical conduction kenel with this channel region and does not have a part of wellblock of ohmic contact.
In a preferable enforcement kenel, this Schottky diode also comprises the doped region of different conduction kenels with this channel region.
For reaching above-mentioned purpose, with regard to one of them semiconductor structure viewpoint speech, the integrated element of a kind of PMOS transistor and Schottky diode proposed by the invention comprises: matrix; Be positioned at the conductor layer on this matrix, constitute the transistorized grid of this PMOS; Be positioned at N type first wellblock of this matrix, its part constitutes the transistorized channel region of this PMOS; Be positioned at a P type doped region of this first wellblock, constitute this PMOS transistor drain, wherein form parasitic diode between this drain electrode and this channel region; Be positioned at the 2nd P type doped region of this first wellblock, constitute the transistorized source electrode of this PMOS; And,, in this another part of first wellblock, do not have the ohmic contact of N type with this parasitic diode differential concatenation by the Schottky diode that another part constituted of this first wellblock.
In a preferable enforcement kenel, in this another part of first wellblock, also comprise the 3rd P type doped region.
For reaching above-mentioned purpose, with regard to another semiconductor structure viewpoint speech, the integrated element of a kind of PMOS transistor and Schottky diode proposed by the invention comprises: a P mold base constitutes this PMOS transistor drain; Be positioned at two conductors of inserting of this matrix, constitute the transistorized grid of this PMOS; Be positioned at the N type wellblock between this two conductor, its part constitutes the transistorized channel region of this PMOS, wherein forms parasitic diode between this drain electrode and this channel region; Be positioned at the P type doped region of this top, N type wellblock, constitute the transistorized source electrode of this PMOS; And,, in this another part of first wellblock, do not have the ohmic contact of N type with this parasitic diode differential concatenation by the Schottky diode that another part constituted of this first wellblock.
In a preferable enforcement kenel, above this N type wellblock, should be provided with at least two P type doped regions.
In a preferable enforcement kenel, this matrix should comprise the crystals growth of heap of stone district of body with the low concentration that is positioned at the body top of higher concentration.
Illustrate in detail below by specific embodiment, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 marks the power switch component of prior art, wherein comprises independently independently Schottky diode of PMOS transistor AND gate;
Fig. 2 illustrates one embodiment of the present of invention with the circuit diagram form;
One of them embodiment that Fig. 3 marks the present invention when realizing with semiconductor;
Another embodiment that Fig. 4 marks the present invention when realizing with semiconductor.
Symbol description among the figure
10 control circuits
12 Schottky diodes
14 PMOS transistors
The 14D parasitic diode
20 integrate power switch component
22 Schottky diodes
24 PMOS transistors
The 24D parasitic diode
201 N type wellblocks
202 grids
203 P+ doped regions
204 P+ doped regions
205 P+ doped regions
210 P mold bases
211 P+ type bodies
212 P types are built the crystals growth district
213 grid oxic horizons
214 grids
215 N type wellblocks
216 P+ doped regions
Embodiment
The icon of this specification all belongs to signal, and its dimension does not fully proportionally illustrate.
Please refer to Fig. 2, wherein show one embodiment of the present of invention with the circuit diagram form.As shown in the figure, in the present embodiment, Schottky diode 22 is not to connect with PMOS transistor 24, but integrates a part that becomes PMOS transistor 24, to constitute power switch component 20.This Schottky diode 22 is formed on the semiconductor substrate of PMOS transistor 24, with the parasitic diode 24D differential concatenation of PMOS transistor 24; This parasitic diode 24D then is formed between the drain electrode and channel region of PMOS transistor 14.Under this kind structure, only relate to the conducting resistance of PMOS transistor 24 between input voltage vin and the output voltage V o, and do not have the pressure drop of Schottky diode, so its power dissipation can significantly reduce.
Above circuit is during with semiconductor fabrication, and its example of implementing kenel sees also Fig. 3.As shown in the figure, in matrix, form N type wellblock 201, and on matrix, deposit grid oxic horizon (not illustrating) and grid layer 202, implant mode forms high concentration in matrix P+ type doped region 203,204 with ion again, respectively as the drain electrode and the source electrode of PMOS transistor 24.Input voltage vin also directly is connected with N type wellblock 201 except that with the P+ type doped region 204 of PMOS transistor 24 is connected.Because input voltage vin and 201 direct junctions, N type wellblock do not provide ohmic contact (ohmic contact), so the conducting obstacle at this place is higher, be equal to and be provided with a Schottky diode, with the parasitic diode differential concatenation that P+ type doped region 203 and N type wellblock 201 are constituted, make electric current be difficult for being fed back into end Vin through N type wellblock 201 adverse currents from output end vo.In addition, in better embodiment, also can in N type wellblock 201, high concentration P+ doped region 205 be set the position of Schottky diode in addition, with the reverse leakage current of further control Schottky diode.
As shown in Figure 3, area occupied of the present invention only is equivalent to the area area of P+ doped region 205 (or increase slightly again) of single PMOS transistor 24, is low far beyond prior art.Because the unit are of overall power switch element descends, therefore under the identical power switch component gross area, because of having saved the zone of Schottky diode, PMOS transistor 24 of the present invention can use bigger area, and its conducting resistance is descended more.More in detail, if compare with prior art of the same area, the conducting resistance of power switch component of the present invention only is 1/4 of a prior art approximately, and because of the present invention does not have Schottky diode in the input-output tandem paths, and PMOS transistor 24 conducting resistance only are half approximately.
Fig. 4 shows an alternative embodiment of the invention, and the PMOS transistor in the present embodiment is the plough groove type transistor.As shown in the figure, on P mold base 210, make two grooves, form grid oxic horizon 213, and insert conductor 214 (for example silicon or other conductor), promptly constituted the transistorized grid of plough groove type PMOS for having mixed with thermal oxidation method or alternate manner.In the matrix region between two grooves, form the wellblock 215 (this step before or after forming groove, carry out all can) of doped N-type impurity with ionic-implantation, and form the P+ doped region 216 of high concentration on the surface of N type wellblock 215, promptly constitute the transistorized source electrode of plough groove type PMOS, and be drain electrode with the back side of matrix.In better embodiment, for preferable drain electrode contact resistance is provided, P mold base 210 should comprise the P+ type body 211 and the P type crystals growth district 212 of heap of stone of higher concentration.With last embodiment similarly, input voltage vin is except that with the P+ type doped region 216 of PMOS transistor 24 is connected, also directly be connected, and input voltage vin and 215 direct junctions, N type wellblock do not provide ohmic contact, make this place be equal to a Schottky diode with N type wellblock 215.In the present embodiment, P+ type doped region 216 one side are as the source electrode of PMOS transistor 24, the reverse leakage current of may command Schottky diode on the one hand.
Below at preferred embodiment the present invention is described, just the above for making those skilled in the art be easy to understand content of the present invention, is not to be used for limiting interest field of the present invention only.Under same spirit of the present invention, those skilled in the art can think and various equivalence changes, and all should be included within the scope of the present invention.
Claims (8)
1. the integrated element of a PMOS transistor and Schottky diode is characterized in that, comprises:
A PMOS transistor, it comprises the channel region between grid, source electrode, drain electrode and source-drain electrode, this source electrode, drain electrode and channel region are positioned at a matrix, and form parasitic diode between this drain electrode and this channel region; And
Schottky diode with this parasitic diode differential concatenation, this Schottky diode is positioned at this matrix, and the one end is connected with this parasitic diode, and the other end is connected with this source electrode.
2. the integrated element of PMOS transistor and Schottky diode as claimed in claim 1, wherein, this Schottky diode comprises identical conduction kenel with this channel region and does not have a part of wellblock of ohmic contact.
3. the integrated element of PMOS transistor and Schottky diode as claimed in claim 1, wherein, this Schottky diode also comprises the doped region of different conduction kenels with this channel region.
4. the integrated element of a PMOS transistor and Schottky diode is characterized in that, comprises:
Matrix;
Be positioned at the conductor layer on this matrix, constitute the transistorized grid of this PMOS;
Be positioned at N type first wellblock of this matrix, its part constitutes the transistorized channel region of this PMOS;
Be positioned at a P type doped region of this first wellblock, constitute this PMOS transistor drain, wherein form parasitic diode between this drain electrode and this channel region;
Be positioned at the 2nd P type doped region of this first wellblock, constitute the transistorized source electrode of this PMOS; And
By the Schottky diode that another part constituted of this first wellblock,, in this another part of first wellblock, do not have the ohmic contact of N type with this parasitic diode differential concatenation.
5. the integrated element of PMOS transistor and Schottky diode as claimed in claim 4 wherein, also comprises the 3rd P type doped region in this another part of first wellblock.
6. the integrated element of a PMOS transistor and Schottky diode is characterized in that, comprises:
A P mold base constitutes this PMOS transistor drain;
Be positioned at two conductors of inserting of this matrix, constitute the transistorized grid of this PMOS;
Be positioned at the N type wellblock between this two conductor, its part constitutes the transistorized channel region of this PMOS, wherein forms parasitic diode between this drain electrode and this channel region;
Be positioned at the P type doped region of this top, N type wellblock, constitute the transistorized source electrode of this PMOS; And
By the Schottky diode that another part constituted of this first wellblock,, in this another part of first wellblock, do not have the ohmic contact of N type with this parasitic diode differential concatenation.
7. the integrated element of PMOS transistor and Schottky diode as claimed in claim 6 wherein, is provided with at least two P type doped regions above this N type wellblock.
8. the integrated element of PMOS transistor and Schottky diode as claimed in claim 6, wherein, this matrix comprises the crystals growth of heap of stone district of body with the low concentration that is positioned at the body top of higher concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910127931A CN101847634A (en) | 2009-03-27 | 2009-03-27 | Integration component of PMOS (P-channel Metal Oxide Semiconductor) transistor and Schottky diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910127931A CN101847634A (en) | 2009-03-27 | 2009-03-27 | Integration component of PMOS (P-channel Metal Oxide Semiconductor) transistor and Schottky diode |
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| CN101847634A true CN101847634A (en) | 2010-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910127931A Pending CN101847634A (en) | 2009-03-27 | 2009-03-27 | Integration component of PMOS (P-channel Metal Oxide Semiconductor) transistor and Schottky diode |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102759697B (en) * | 2012-07-26 | 2017-05-03 | 上海华虹宏力半导体制造有限公司 | Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method |
| CN110601143A (en) * | 2019-09-25 | 2019-12-20 | 深圳奥简科技有限公司 | Battery protection circuit and battery charging and discharging system |
-
2009
- 2009-03-27 CN CN200910127931A patent/CN101847634A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102759697B (en) * | 2012-07-26 | 2017-05-03 | 上海华虹宏力半导体制造有限公司 | Method for testing package level of metal oxide semiconductor (MOS) transistor and MOS transistor manufacturing method |
| CN110601143A (en) * | 2019-09-25 | 2019-12-20 | 深圳奥简科技有限公司 | Battery protection circuit and battery charging and discharging system |
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Application publication date: 20100929 |