CN101615584B - Packaging method of chip reconfiguration structure - Google Patents
Packaging method of chip reconfiguration structure Download PDFInfo
- Publication number
- CN101615584B CN101615584B CN2008101250507A CN200810125050A CN101615584B CN 101615584 B CN101615584 B CN 101615584B CN 2008101250507 A CN2008101250507 A CN 2008101250507A CN 200810125050 A CN200810125050 A CN 200810125050A CN 101615584 B CN101615584 B CN 101615584B
- Authority
- CN
- China
- Prior art keywords
- chip
- metal wire
- wire sections
- fan
- patterning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 111
- 239000002184 metal Substances 0.000 claims abstract description 111
- 238000000059 patterning Methods 0.000 claims description 109
- 238000012856 packing Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 238000005476 soldering Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 89
- 238000005516 engineering process Methods 0.000 description 36
- 239000000463 material Substances 0.000 description 30
- 239000011241 protective layer Substances 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 20
- 238000005520 cutting process Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229920000800 acrylic rubber Polymers 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000006071 cream Substances 0.000 description 4
- 229920000058 polyacrylate Polymers 0.000 description 4
- 229920002379 silicone rubber Polymers 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 239000004568 cement Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention relates to a packaging structure of chip reconfiguration, which comprises a chip, a packaging body, a patterned protection layer, a fan-out patterned metal segment, a second patterned protection layer, a patterned UBM layer and a conductive assembly, wherein the packaging body is annularly covered on four surfaces of the chip so as to expose an active surface and a back surface of the chip out; the patterned protection layer is formed on the surface of the packaging body and covered on the active surface of the chip and exposes a plurality of soldering pads of the chip out; one end of the fan-out patterned metal segment is electrically connected with soldering pads of the chip, and the other end of the fan-out patterned metal segment extends towards the outer side and is covered on the first patterned protection layer; the second patterned protection layer is covered on the patterned metal segment and exposes the partial surface of the patterned metal segment out; the patterned UBM layer is formed on the partial surface of the exposed patterned metal segment; and the conductive assembly is formed on the pattern UBM layer and is electrically connected with the patterned metal segment through the patterned UBM layer.
Description
Technical field
Relevant a kind of semiconductor package structure of the present invention and method, particularly relevant a kind of chip or a plurality of chip are reconfigured to the support plate with packaging body after, reconfigure layer (RDL) through use again and form modular encapsulating structure and method for packing thereof.
Background technology
Semi-conductive technology has developed suitable rapidly, therefore microminiaturized semiconductor chip (Dice) must have the demand of diversified function, make semiconductor chip must in very little zone, dispose more I/o pad (I/O pads), thereby make the density of metal pin (pins) also improve fast.Therefore, early stage leaded package technology has been not suitable for the high-density metal pin; So develop the encapsulation technology that a kind of ball array (Ball Grid Array:BGA), the ball array encapsulation is except having than the more highdensity advantage of leaded package, and its tin ball also relatively is not easy infringement and distortion.
Popular along with 3C Product, for example: mobile phone (Cell Phone), PDA(Personal Digital Assistant) or iPod etc., all the System on Chip/SoC of many complexity must be put into a very little space, therefore be this problem of solution, a kind of being called " wafer-class encapsulation (wafer level package; WLP) " encapsulation technology develops out, and it can just encapsulate wafer earlier before cut crystal becomes one by one chip.The U.S. the 5th, 323, No. 051 patent has promptly disclosed this " wafer-class encapsulation " technology.Yet, this " wafer-class encapsulation " technology is along with the increase of the weld pad on the chip active surface (pads) number, make that the spacing of weld pad (pads) is too small, except meeting causes the problem of signal coupling or signal interference, also can cause the problems such as reliability reduction of encapsulation because the weld pad spacing is too small.Therefore, after chip further dwindles again, make aforesaid encapsulation technology all can't satisfy.
For solving this problem, the U.S. the 7th, 196, No. 408 patent has disclosed a kind of wafer that will finish the semiconductor fabrication operation, after test and cutting, with test result is that good chip (good die) reapposes on another substrate, and then carry out packaging process, so, make these chip chambers that reapposed have the spacing of broad, so horizontal expansion (or fan-out) (fan out) technology is for example used in distribution that can the weld pad on the chip is suitable, therefore can effectively solve because of spacing too small, the problem that causes signal coupling or signal to disturb except meeting.
Yet, for making semiconductor chip that less and thin encapsulating structure can be arranged, before carrying out the wafer cutting, can carry out thinning to wafer earlier and handle, for example wafer is thinned to 2～20 mils (mil), and then cuts into chip one by one in back of the body mill (backside lapping) mode.This chip through the thinning processing through reconfiguring on another substrate, forms a packaging body with injection molded with a plurality of chips again; Because chip is very thin, make that packaging body also is very thin, so after packaging body disengaging substrate, the stress of packaging body itself can make packaging body generation warpage increases follow-up difficulty of carrying out cutting action.
In addition, after wafer cutting, chip be reconfigured in another size than the size of original substrate also during large substrates, owing to need by fetching device (pick﹠amp; Place) chip is picked up, then with after the chip upset, to cover crystal type the active surface of chip is attached on the substrate, and in the process of fetching device with the chip upset, can produce inclination (tilt) easily and cause displacement, for example: tilt to surpass 5 microns, so can make chip to aim at, and then make follow-up planting in the ball operation also can't aim at, and cause the reliability of encapsulating structure to reduce.
Summary of the invention
In view of above problem, main purpose of the present invention is to provide a kind of packaging body that utilizes to be formed on the support plate, makes chip can reconfigure at another support plate by packaging body, can allow each chip be configured on the support plate accurately whereby.
Another main purpose of the present invention is at the method for packing that provides a kind of chip to reconfigure, it can be reconfigured in the chip that wafer cut out on the substrate of 8 o'clock wafers at 12 o'clock, so can effectively use the sealed in unit that promptly has of 8 o'clock wafers, and need not to re-establish the sealed in unit of 12 o'clock wafers, can reduce the packaging cost of 12 o'clock wafers.
Of the present invention also have a main purpose at the method for packing that provides a kind of chip to reconfigure, and makes that the chip that encapsulates all is " known is normally functioning chip " (Known good die), can save encapsulating material, so also can reduce the technology cost.
According to above-mentioned purpose, the invention provides a kind of chip packaging method, comprise: a support plate is provided, has a upper surface face and an a lower surface; Forming a packaging body on upper surface of said carrier plate, is that the packaging body that will have at least one opening is formed on the upper surface of said carrier plate, makes opening expose the part upper surface of support plate; Attaching the part upper surface of a chip at the support plate that has exposed to the open air, is with an active surface of chip up, and a back side that has a plurality of weld pads and chip on the active surface is attached to the part upper surface of support plate by an adhesion layer; Form first patterned protection layer on packaging body, and cover on the active surface of chip, and expose a plurality of weld pads on the active surface of chip; Form the metal wire sections of the patterning of a plurality of fan-outs, a plurality of weld pads on the active surface of one end and chip form and electrically connect, and partly the metal wire sections of the patterning of a plurality of fan-outs is formed on the part first patterned protection layer; Form second patterned protection layer,, and expose the surface of the other end of metal wire sections of the patterning of each fan-out with the metal wire sections of the patterning of the active surface that covers chip and each fan-out; The UBM layer that forms a plurality of patternings and forms with the metal wire sections of a plurality of patternings and to electrically connect on the surface of the fan-out structure of extending laterally of the metal wire sections of each patterning; Forming a plurality of conductive components, is to form electric connection by the UBM layer of a plurality of patternings and the metal wire sections of a plurality of patternings; And remove support plate, to form a chip-packaging structure.
The present invention also provides a kind of method for packing of multicore sheet, comprises: a support plate is provided, has a upper surface and a lower surface; Forming a packaging body on upper surface of said carrier plate, is that the packaging body that will have a plurality of openings is formed on upper surface of said carrier plate, makes each opening expose the part upper surface of support plate; Attaching the part upper surface of a plurality of chips at the support plate that has exposed to the open air, is with the active surface of each chip up, and the back side that has a plurality of weld pads and each chip on the active surface is attached on the part upper surface of the support plate that has exposed to the open air by an adhesion layer; Form a first patterned protection layer on packaging body, and cover on the active surface of each chip, and expose a plurality of weld pads of the active surface of each chip; Form the metal wire sections of the patterning of a plurality of fan-outs, a plurality of weld pads on the active surface of one end and each chip form and electrically connect, and partly the metal wire sections of the patterning of a plurality of fan-outs is formed on the part first patterned protection layer; Form second patterned protection layer,, and expose the surface of the other end of metal wire sections of the patterning of each fan-out with the metal wire sections of the patterning of the active surface that covers each chip and each fan-out; The UBM layer that forms a plurality of patternings and forms with the metal wire sections of a plurality of patternings and to electrically connect on the surface of the fan-out structure of extending laterally of the metal wire sections of each patterning; Forming a plurality of conductive components, is to form electric connection by the UBM layer of a plurality of patternings and the metal wire sections of a plurality of patternings; And remove support plate, form a multichip packaging structure.
According to above-mentioned method for packing, the encapsulating structure that the present invention also provides a kind of chip to reconfigure comprises: a chip, dispose a plurality of weld pads on the one active surface and a back side has an adhesion layer; One packaging body, its ring are overlying on active surface and the back side of four faces to expose chip of chip; One first patterned protection layer, its surface that is formed on packaging body is gone up and is covered on the active surface of chip, and exposes a plurality of weld pads of chip; The metal wire sections of the patterning of a plurality of fan-outs, a plurality of weld pads on the active surface of one end and chip form and electrically connect, and its other end then extends laterally in the fan-out mode and covers a plurality of first patterned protection layer; One second patterned protection layer, it is covered on the metal wire sections of patterning of a plurality of fan-outs, and exposes the part surface of a fan-out structure of the active surface outside to chip of metal wire sections of the patterning of a plurality of fan-outs extending; The UBM layer of a plurality of patternings, it is formed on the part surface of the fan-out structure of extending to the active surface of the chip outside of metal wire sections of patterning of a plurality of fan-outs that exposed to the open air; And a plurality of conductive components, be formed on the UBM layer of a plurality of patternings, and the metal wire sections formation electric connection of the UBM layer by a plurality of patternings and the patterning of a plurality of fan-outs.
The encapsulating structure that the present invention provides a kind of multicore sheet to reconfigure in addition comprises: a plurality of chips, and the back side that disposes a plurality of weld pads and each chip on the active surface of its each chip has an adhesion layer; One packaging body, its ring are overlying on active surface and the back side of four faces to expose each chip of a plurality of chips; A plurality of first patterned protection layer, it is formed on the surface of packaging body and covers on the active surface of a plurality of chips, and exposes a plurality of weld pads on the active surface of each chip; The metal wire sections of a plurality of patternings, a plurality of weld pads on the active surface of one end and a plurality of chips form and electrically connect, and its other end then extends in the fan-out mode and is covered on a plurality of first patterned protection layer; A plurality of second patterned protection layer, it is covered in the metal wire sections of the patterning of a plurality of fan-outs, and exposes the part surface of the fan-out structure of extending to the active surface of each chip outside of metal wire sections of the patterning of a plurality of fan-outs; The UBM layer of a plurality of patternings, it is formed on the part surface of the fan-out structure of extending to the active surface of each chip outside of metal wire sections of patterning of a plurality of fan-outs that exposed to the open air; And a plurality of conductive components, be formed on the UBM layer of a plurality of patternings, and the metal wire sections formation electric connection of the UBM layer by a plurality of patternings and the patterning of a plurality of fan-outs.
Description of drawings
For can clearer understanding purpose of the present invention, characteristics and advantage, below conjunction with figs. is described in detail preferred embodiment of the present invention, wherein:
Fig. 1 is disclosed technology according to the present invention, is illustrated in the schematic cross-section that forms packaging body on the support plate;
Fig. 2 is disclosed technology according to the present invention, and expression is seated in schematic cross-section on the support plate with packaging body with a plurality of chips;
Fig. 3 to Fig. 4 is disclosed technology according to the present invention, and expression forms the schematic cross-section that a plurality of first patterned protection layer are formed on the step on the packaging body;
Fig. 5 is disclosed technology according to the present invention, and expression forms the schematic cross-section of metal level on first protective layer and a plurality of weld pad;
Fig. 6 is disclosed technology according to the present invention, and the metal wire sections of representing a plurality of patternings is formed on the schematic cross-section on the weld pad of packaging body and a plurality of chips;
Fig. 7 is disclosed technology according to the present invention, represents that second protective layer is formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Fig. 8 is disclosed technology according to the present invention, represents that a plurality of second patterned protection layer are formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Fig. 9 is disclosed technology according to the present invention, is illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that has exposed to the open air;
Figure 10 is disclosed technology according to the present invention, represents that a plurality of conductive components are formed on the schematic cross-section on the UBM layer of a plurality of patternings;
Figure 11 is disclosed technology according to the present invention, and the schematic cross-section of the one chip encapsulating structure of encapsulation is finished in expression;
Figure 12 is disclosed technology according to the present invention, and expression is by the system in package that the chip constituted (System-In-Package of a plurality of difference in functionalitys and size; SIP) vertical view;
Figure 13 is disclosed technology according to the present invention, and expression is seated in schematic cross-section on the support plate with packaging body with the chip of different size and function;
Figure 14 is disclosed technology according to the present invention, represents that first protective layer is formed on the schematic cross-section on the packaging body;
Figure 15 is disclosed technology according to the present invention, represents that a plurality of first patterned protection layer are formed on the schematic cross-section on the packaging body;
Figure 16 is disclosed technology according to the present invention, and the expression metal level is formed on the schematic cross-section on a plurality of first patterned protection layer;
Figure 17 is disclosed technology according to the present invention, and the metal wire sections of representing a plurality of patternings is formed on the schematic cross-section on a plurality of first patterned protection layer;
Figure 18 is disclosed technology according to the present invention, represents that second protective layer is formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Figure 19 is disclosed technology according to the present invention, represents that a plurality of second patterned protection layer are formed on the schematic cross-section on the metal wire sections of a plurality of patternings;
Figure 20 is disclosed technology according to the present invention, is illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that has exposed to the open air; And
Figure 21 is disclosed technology according to the present invention, represents that a plurality of conductive components are formed on the UBM layer of a plurality of patternings, finish the schematic cross-section of the multichip packaging structure of encapsulation.
Embodiment
The present invention is the method for packing that a kind of chip reconfigures in this direction of inquiring into, a plurality of chips is reconfigured on the support plate with packaging body the method that encapsulates then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the those of ordinary skill of the mode of chip stack is familiar with.On the other hand, the detailed step of back segment operations such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.
In the semiconductor packaging process in modern times, all be that a wafer (wafer) of having finished leading portion operation (Front EndProcess) is carried out thinning processing (Thinning Process) earlier, for example the thickness with wafer is ground between 2～20 mils (mil); Then, carry out the cutting (sawing process) of wafer to form chip one by one; Then, use fetching device (pick and place) that chip one by one is positioned on another support plate one by one.Clearly, the street zone on the support plate is bigger than chip, therefore, and can be so that these chip chambers that reapposed have the spacing of broad, so distribution that can the weld pad on the chip is suitable.
At first, provide a wafer (not expression in the drawings) and on wafer, dispose a plurality of chips (not expression in the drawings),, have a plurality of weld pads (not expression in the drawings) on each chip at this.Then, with reference to figure 1, be to be illustrated in the schematic cross-section that has packaging body on the support plate.In Fig. 1, be that a packaging body 20 is formed on the support plate 10, and in packaging body 20, have a plurality of openings 202 to expose the part surface of support plate 10 to the open air.In this enforcement, comprise in the step that forms packaging body 20 on the support plate 10: be coated with a macromolecular material (expression in the drawings) earlier on the front of support plate 10, and use a die device (not expression in the drawings) the macromolecular material pressing with a plurality of protrusion ribs (expression in the drawings).
In addition, in an embodiment of the present invention, also can select to use injection molded (molding process) that macromolecular material is formed on the support plate 10.Similarly, the die device that will have a plurality of protrusion ribs is pressed together on the support plate 10 with macromolecular material, then, again with macromolecular material, epoxy resin mould closure material (EpoxyMolding Compound for example; EMC), inject the space of die device and support plate 10, make macromolecular material be formed on the support plate 10 with a plurality of protrusion ribs.
Then, after finishing the program of macromolecular material, can optionally carry out a baking program, so that macromolecular material solidifies to macromolecular material.Follow again, carry out demoulding program, the die device that will have a plurality of protrusion ribs with solidify after macromolecular material separate, make and on the surface of support plate 10, have packaging body 20 by the formed a plurality of openings of a plurality of protrusion ribs, by these openings, can be as in subsequent handling, putting the district in order to the chip of putting chip (not expression in the drawings).
Then, use cutter (not expression in the drawings) on the surface of packaging body 20, to form many Cutting Roads 210, equally as shown in Figure 2.In this embodiment, the degree of depth of each Cutting Road 210 is 0.5～1 mil (mil), and the width of Cutting Road 210 then is 5 to 25 microns.In a preferred embodiment, this Cutting Road 210 can be mutual vertical interlaced, and the reference line when can be used as actual diced chip.
Then, equally with reference to figure 2, at first, be that previous wafer (expression) is in the drawings cut into a plurality of chips 30, then up with the active surface of each chip 30; Then, use fetching device (expression in the drawings) each chip 30 to be picked up and the back side of each chip 30 is seated on the surface of the support plate 10 that has exposed to the open air, make packaging body 20 rings be overlying on four faces of each chip 30 by active surface; Because, all dispose a plurality of weld pads 302 on the active surface of each chip 30, therefore, fetching device can Direct Recognition goes out the position of each weld pad 302 on each chip 30 its active surface; When fetching device will be positioned over chip 30 on the support plate 10, can each chip 30 accurately be positioned on the surface of having exposed to the open air of support plate 10 again by the position on the support plate 10.Therefore, when a plurality of chips 30 reconfigure on support plate 10, just chip 30 can be positioned on the surface of being exposed to the open air on the support plate 10 exactly; In addition, put a plurality of chips 30 again, the accuracy in the time of chip 30 can be improved by the relative position in the chip configuration district being reconfigured in support plate 10 by the chip configuration district that is constituted on support plate 10 surfaces of exposing to the open air by a plurality of openings 202 on the packaging body 20.
In addition, in the present embodiment, on the back side of each chip 30, also comprise one deck adhesion layer 40, its objective is when each chip 30 is seated on the surface of the support plate 10 that has exposed to the open air, can make the back side of each chip 30 be fixed on the surface of the support plate 10 that has exposed to the open air by adhesion layer 40, the material of this adhesion layer 40 is the rubber-like adhesion material, for example: silicon rubber (silicone rubber), silicones (silicone resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber), chip cutting glue, hot releasable material (thermalrelease material) or adhesive tape (tape).
Then, Fig. 3 and Fig. 4 are that expression forms the schematic cross-section that a plurality of first patterned protection layer are formed on the step on the packaging body.At first, in Fig. 3, be earlier first protective layer (not expression in the drawings) to be covered on packaging body 20 and each chip 30; Then, utilize semiconductor technology again, form a patterned light blockage layer (not expression in the drawings) on first protective layer; Next; carry out etching step; remove partly first protective layer forming first patterned protection layer 502 on packaging body 20, and expose a plurality of weld pads 302 on the active surface of each chip 30 and a plurality of opening 202 to expose the part surface of support plate 10, as shown in Figure 4.In this embodiment, the material of first protective layer can be tin cream (paste), two-stage thermosetting cement material (B-stage) or polyimides (polyimide).
And then, after the position of a plurality of weld pads 302 of determining each chip 30, can use the traditional operation that reroutes (Redistribution Layer; RDL) on a plurality of weld pads 302 that each chip 30 is exposed to the open air; form the metal wire sections 602 of the patterning of a plurality of fan-outs; wherein a plurality of weld pads on the active surface of an end of the metal wire sections 602 of each patterning and each chip 30 302 form and electrically connect, and partly the other end of the metal wire sections 602 of a plurality of patternings is to be formed on the first patterned protection layer 502 in the fan-out mode.At this, the formation step of the metal wire sections 602 of the patterning of a plurality of fan-outs comprises: form earlier a crystal seed layer (seedlayer) (expression in the drawings) on the part surface of first patterned protection layer 60 and a plurality of weld pads 302 at the active surface of each chip 30; Then, utilize to electroplate the mode of (electroplate), a metal level 60 is formed on the crystal seed layer, and electrically connect a plurality of weld pads 302 on the active surface of each chip 30, as shown in Figure 5; Then, carry out semiconductor technology, another patterned light blockage layer (not expression in the drawings) is formed on the metal level 60; Then, carry out an etching step, etching is metal level 60 partly, removing the metal level 60 on the first patterned protection layer partly, with the metal wire sections 602 of the patterning that forms a plurality of fan-outs; Wherein partly an end of the metal wire sections 602 of the patterning of fan-out electrically connects a plurality of weld pads 302 on the active surface of each chip 30; and partly the other end of the metal wire sections 602 of a plurality of patternings is outward extending fan-out structures and covers on the first patterned protection layer 502, as shown in Figure 6.
Then, Fig. 7 and Fig. 8 represent that a plurality of second patterned protection layer are formed on the schematic cross-section of each step on the metal wire sections of patterning of a plurality of fan-outs.At first, in Fig. 7, utilize semiconductor technology, form earlier on the metal wire sections 602 of second protective layer 70 with the patterning that covers a plurality of fan-outs; Then; form another patterned light blockage layer (not expression in the drawings) on second protective layer 70; then; carry out etching step; remove part second protective layer 70 to form a plurality of second patterned protection layer 702; and on the surface of extending, form the surface of a plurality of openings 704, as shown in Figure 8 with the metal wire sections 602 of the patterning that exposes each fan-out corresponding to the active surface outside to each chip 30 of the metal wire sections 602 of each patterning.In this embodiment, the material of second protective layer can be tin cream (paste), two-stage thermosetting cement material (B-stage) or polyimide.
Then, with reference to figure 9, be illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that has exposed to the open air.As shown in Figure 9, be on the surface of the other end of the metal wire sections 602 of the patterning of each fan-out that exposes, form a UBM layer (expression in the drawings) in the mode of sputter (sputtering); Then, utilize semiconductor technology, on the UBM layer, form a patterned light blockage layer (not expression in the drawings), then, utilize etching step, remove partly UBM layer, on the surface that extend in the outside to chip of metal wire sections 602 that makes the UBM layer 802 of multiple bar chart caseization be formed on the patterning of each fan-out that exposes, and electrically connect with the metal wire sections 602 of a plurality of patternings; In the present embodiment, the material of UBM layer 802 can be Ti/Ni or Ti/W.
At last, on the UBM of each patterning layer 802, form a plurality of conductive components 90 again, make a plurality of conductive components 90 to form electric connection, as shown in figure 10 by the UBM layer of a plurality of patternings and the metal wire sections of a plurality of patternings.At this, conductive component 90 can be metal coupling (metal bump) or tin ball (solderball).Then, remove after the support plate 10, can carry out last cutting packaging body.In the present embodiment, with one chip as the cutting unit, to form a chip-packaging structure of finishing packaging process, as shown in figure 11.
Then, Figure 12 is system in package that the chip constituted (System-In-Package of expression by a plurality of difference in functionalitys and size; SIP) vertical view.At this, these chips are chips of different size and function, and it comprises micro treatmenting device (microprocessor means) 30A, storage arrangement (memorymeans) 30B or storage control device (memory controller means) 30C at least; Wherein have a plurality of weld pad 302A, 302B, 302C on the active surface of each chip 30A, 30B, 30C, and on weld pad 302A, the 302B of each chip 30A, 30B, 30C, 302C, form many strip metals line segment 602, electrically connect adjacent chip 30A, 30B, 30C and electrically connect with conductive component 90 with series connection or mode in parallel.
Figure 13 to Figure 21 is each flow chart of steps that expression forms system-in-package structure.To be expression be seated in schematic diagram on the support plate with packaging body with the chip of different size and function to Figure 13.As shown in figure 13, similarly, be on support plate 10, to form earlier packaging body 20 with opening, be to desire to be seated in chip 30A, the 30B of the difference in functionality on the support plate 10, the size of 30C in corresponding to subsequent handling in the size of this each opening.Then, identical with prior statement, be that the wafer that will have difference in functionality respectively cuts, to form a plurality of chip 30A, 30B, 30C, then up with the active surface of chip 30A, the 30B of each difference in functionality, 30C with different size and function; Then, use fetching device (not shown in the diagram) respectively chip 30A, 30B, the 30C of each difference in functionality and size to be picked up, and chip 30A, the 30B of each difference in functionality, the back side of 30C are seated on the partial front of the support plate 10 that has exposed by active surface; Because, all dispose a plurality of weld pad 302A, 302B, 302C on chip 30A, the 30B of each difference in functionality, the active surface of 30C, therefore, fetching device can Direct Recognition goes out chip 30A, 30B, each weld pad 302A, 302B on its active surface of 30C of each difference in functionality, the position of 302C; When fetching device will be positioned over chip 30A, 30B, the 30C of each difference in functionality on the support plate 10, can be again by the position on the support plate 10, on chip 30A, the 30B of each difference in functionality, the surface of having exposed to the open air that 30C accurately is positioned over support plate 10.Therefore, when a plurality of chip 30A, 30B, 30C with difference in functionality reconfigure on support plate 10, just chip 30A, 30B, the 30C of each difference in functionality can be seated on the support plate 10 exactly.In addition, can put chip 30A, 30B, the 30C of a plurality of difference in functionalitys again, the accuracy when reconfiguring to improve chip by the surface of the support plate that a plurality of opening exposed to the open air 10 in the packaging body 20.
In addition, in the present embodiment, on the back side of chip 30A, the 30B of each difference in functionality, 30C, also comprise an adhesion layer 40, its objective is when chip 30A, 30B when each difference in functionality, 30C put to the surface of the support plate 10 that has exposed to the open air, chip 30A, the 30B of each difference in functionality, the back side of 30C are fixed on the surface of the support plate 10 that has exposed to the open air.In this embodiment, the material of adhesion layer 40 is the rubber-like adhesion material, and it can be silicon rubber (silicone rubber), silicones (silicone resin), elasticity PU, porous PU, acrylic rubber (acrylic rubber), chip cutting glue, hot releasable material (thermal release material) or adhesive tape (tape).
Then, Figure 14 and Figure 15 are the schematic cross-sections that expression forms a plurality of first patterned protection layer.Its formation method comprises: earlier first protective layer 50 is formed on the active surface of chip 30A, 30B, 30C of packaging body 20 and each difference in functionality, as shown in figure 14; Then, utilize semiconductor technology again, form a patterned light blockage layer (not expression in the drawings) on first protective layer 50; Next; be etched with and remove part first protective layer 50 to form a plurality of first patterned protection layer 502 on packaging body 20; and expose a plurality of weld pad 302A, 302B, 302C on the active surface of chip 30A, 30B, 30C of each difference in functionality, as shown in figure 15.At this, the material of first protective layer 50 can be tin cream (paste), two-stage thermosetting formula glue material (B-stage) or polyimides (polyimide).
And then, after the position of a plurality of weld pad 302A that determine chip 30A, the 30B of each difference in functionality, 30C, 302B, 302C, can use the traditional operation that reroutes (Redistribution Layer; RDL) on a plurality of weld pad 302A that chip 30A, 30B, the 30C of each difference in functionality are exposed to the open air, 302B, 302C; form the metal wire sections 602 of the patterning of a plurality of fan-outs; wherein a plurality of weld pad 302A on the active surface of chip 30A, the 30B of an end of the metal wire sections 602 of each patterning and each difference in functionality, 30C, 302B, 302C electrically connect, and partly the other end of the metal wire sections 602 of a plurality of patternings is to be formed on a plurality of first patterned protection layer 502 in the fan-out mode.At this, the formation step of the metal wire sections 602 of a plurality of patternings comprises: a plurality of weld pad 302A, 302B, 302C that a crystal seed layer (expression) in the drawings is formed on the part surface of a plurality of first patterned protection layer 502 and is formed on the active surface of chip 30A, the 30B of each difference in functionality, 30C; Electroplate a metal level 60 on crystal seed layer; Next, form another patterned light blockage layer (not expression in the drawings) on metal level 60; Be etched with the metal level 60 that removes on the part first patterned protection layer 502; metal wire sections 602 with the patterning that forms a plurality of fan-outs; wherein partly a plurality of weld pad 302A, 302B, the 302C of the active surface of chip 30A, the 30B of an end of the metal wire sections 602 of the patterning of fan-out and each difference in functionality, 30C form electric connection; and partly the other end of the metal wire sections 602 of a plurality of patternings is an outward extending fan-out structure and covers on a plurality of first patterned protection layer 502, as shown in figure 17.
Then, be that expression forms the schematic cross-section of a plurality of second patterned protection layer on the metal wire sections of the patterning of a plurality of fan-outs with reference to Figure 18 and Figure 19.Its formation method comprises: be to utilize semiconductor process, with metal wire sections 602 and the part first patterned protection layer 502 of second protective layer 70 to cover the part patterning, as shown in figure 18.Then, on second protective layer 70, form a patterned light blockage layer (not expression in the drawings); Then; carry out an etching step; to remove partly second protective layer 70; to form a plurality of second patterned protection layer 702; and on the surface of extending, form the surface of a plurality of openings 704, as shown in figure 19 with the other end of the metal wire sections 602 of the patterning that exposes each fan-out corresponding to the active surface outside of chip 30A, the 30B to each difference in functionality of the metal wire sections 602 of each patterning, 30C.At this, the material of second protective layer can be tin cream (paste), two-stage thermosetting cement material (B-stage) or polyimides (polyimide).
Then, Figure 20 is to be illustrated in the schematic cross-section that forms the UBM layer of a plurality of patternings on the surface of the other end of metal wire sections of patterning of each fan-out that exposes.As shown in figure 20, be on the surface of the other end of the metal wire sections 602 of the patterning of each fan-out that exposes, form a UBM layer (expression in the drawings) in the mode of sputter (sputtering); Then, utilize semiconductor technology, on the UBM layer, form a patterned light blockage layer (not expression in the drawings), then, utilization is etched with and removes partly UBM layer,, on the surface of the metal wire sections 602 of the patterning of each fan-out that exposes, and electrically connect with the UBM layer 802 that forms the multiple bar chart caseization with the metal wire sections 602 of a plurality of patternings; In the present embodiment, the material of UBM layer 802 can be Ti/Ni or Ti/W.
At last, on the UBM of each patterning layer 802, form a plurality of conductive components 90 again, so that as chip 30A, the 30B of each difference in functionality, the contact that 30C externally electrically connects; Wherein, this conductive component 90 can be metal coupling (metal bump) or tin ball (solder ball); And can form electric connection by the UBM layer 802 of a plurality of patternings and the metal wire sections 602 of a plurality of patternings, and then support plate 10 is removed, promptly can finish the encapsulating structure of multicore sheet, as shown in figure 21.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; any those of ordinary skill of being familiar with present technique; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.
Claims (5)
1. chip packaging method comprises:
One support plate is provided, has a upper surface and a lower surface;
Forming a packaging body this upper surface at this support plate, is that this packaging body that will have at least one opening is formed on this upper surface of this support plate, makes this opening expose the part upper surface of this support plate;
Attach the part upper surface of a chip at this support plate that has exposed to the open air, be up with an active surface of this chip, and a back side that has a plurality of weld pads and this chip on this active surface is attached to the part upper surface of this support plate that exposes to the open air by an adhesion layer, makes the packaging body ring be overlying on four faces of chip;
Form a first patterned protection layer on this packaging body and cover on this active surface of this chip, and expose these weld pads on this active surface of this chip;
Form the metal wire sections of the patterning of a plurality of fan-outs, the metal wire sections that these weld pads on an end of the metal wire sections of the patterning of these fan-outs and this active surface of this chip form the patterning of electric connection and these fan-outs of part is formed on this first patterned protection layer of part;
Form a second patterned protection layer,, and expose the surface of the other end of metal wire sections of the patterning of each this fan-out with the metal wire sections of the patterning that covers each this fan-out;
The UBM layer that forms a plurality of patternings and forms with the metal wire sections of these patternings and to electrically connect on this surface of the fan-out structure of extending laterally of the metal wire sections of each this patterning;
Forming a plurality of conductive components, is that these conductive components are formed electric connection by the UBM layer of these patternings and the metal wire sections of these patternings; And
Remove this support plate, to form a chip-packaging structure.
2. the method for packing of a multicore sheet comprises:
One support plate is provided, has a upper surface and a lower surface;
Forming a packaging body on this upper surface of this support plate, is this upper surface that this packaging body that will have a plurality of openings is formed on this support plate, makes that each this opening is the part upper surface that exposes this support plate;
Attach the part upper surface of a plurality of chips at this support plate that has exposed to the open air, be up with an active surface of each this chip, and a back side that has a plurality of weld pads and each this chip on this active surface is attached on the part upper surface of this support plate that has exposed to the open air by an adhesion layer, makes the packaging body ring be overlying on four faces of each this chip;
Form a first patterned protection layer on this packaging body and cover on this active surface of each this chip, and expose these weld pads of this active surface of each this chip;
Form the metal wire sections of the patterning of a plurality of fan-outs, the metal wire sections that these weld pads on an end of the metal wire sections of the patterning of these fan-outs and this active surface of each this chip form the patterning of electric connection and these fan-outs of part is formed on this first patterned protection layer of part;
Form a second patterned protection layer,, and expose the surface of the other end of metal wire sections of the patterning of each this fan-out with the metal wire sections of the patterning that covers each this fan-out;
The UBM layer that forms a plurality of patternings and forms with the metal wire sections of these patternings and to electrically connect on this surface of the fan-out structure of extending laterally of the metal wire sections of each this patterning;
Forming a plurality of conductive components, is that these conductive components are formed electric connection by the UBM layer of these patternings and the metal wire sections of these patternings; And
Remove this support plate, to form a multichip packaging structure.
3. method for packing according to claim 2 is characterized in that these chips are chips of identical function and size.
4. method for packing according to claim 2 is characterized in that these chips are chips of difference in functionality and size.
5. method for packing according to claim 2, the metal wire sections that it is characterized in that forming the patterning of these fan-outs comprises:
Form a crystal seed layer on the part of this first patterned protection layer surface and a plurality of weld pads at this active surface of this chip;
Electroplate a metal level on this crystal seed layer, and electrically connect these weld pads of this active surface of this chip;
The photoresist layer that forms a patterning is on this metal level; And
Etching is this metal level partly; remove the metal level on this first patterned protection layer of part; metal wire sections with the patterning that forms these fan-outs; wherein an end of the metal wire sections of these patternings is electrically connected to these weld pads of this active surface of each this chip, and the other end of the metal wire sections of these patternings is outward extending fan-out structures and is covered on this first patterned protection layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101250507A CN101615584B (en) | 2008-06-25 | 2008-06-25 | Packaging method of chip reconfiguration structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101250507A CN101615584B (en) | 2008-06-25 | 2008-06-25 | Packaging method of chip reconfiguration structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101615584A CN101615584A (en) | 2009-12-30 |
| CN101615584B true CN101615584B (en) | 2011-06-15 |
Family
ID=41495142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101250507A Expired - Fee Related CN101615584B (en) | 2008-06-25 | 2008-06-25 | Packaging method of chip reconfiguration structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101615584B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489790A (en) * | 2012-06-14 | 2014-01-01 | 智瑞达科技（苏州）有限公司 | Encapsulation method for chip fan-out encapsulation structure |
| CN103745937B (en) * | 2014-02-08 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | The manufacture craft of fan-out wafer level package |
| CN105575825A (en) * | 2015-12-24 | 2016-05-11 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging method and packaging assembly |
| CN114551258A (en) * | 2022-02-21 | 2022-05-27 | 江苏卓胜微电子股份有限公司 | Fan-out type wafer level packaging method and packaging structure |
| CN114551257B (en) * | 2022-02-21 | 2023-09-22 | 江苏卓胜微电子股份有限公司 | Fan-out type wafer level packaging method and packaging structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392025A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
| US7196408B2 (en) * | 2003-12-03 | 2007-03-27 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
| CN101202253A (en) * | 2006-12-13 | 2008-06-18 | 育霈科技股份有限公司 | Wafer level package with good coefficient of thermal expansion efficiency performance and method of the same |
-
2008
- 2008-06-25 CN CN2008101250507A patent/CN101615584B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1392025A (en) * | 2002-06-28 | 2003-01-22 | 威盛电子股份有限公司 | Forming method for high resolution welding lug |
| US7196408B2 (en) * | 2003-12-03 | 2007-03-27 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
| CN101202253A (en) * | 2006-12-13 | 2008-06-18 | 育霈科技股份有限公司 | Wafer level package with good coefficient of thermal expansion efficiency performance and method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101615584A (en) | 2009-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI387074B (en) | Chip stacked structure and the forming method | |
| TWI387014B (en) | A chip rearrangement structure with a dummy substrate and the package method | |
| US6965160B2 (en) | Semiconductor dice packages employing at least one redistribution layer | |
| US7521285B2 (en) | Method for fabricating chip-stacked semiconductor package | |
| CN101221936B (en) | Wafer level package with die receiving through-hole and method of the same | |
| US7445963B2 (en) | Semiconductor package having an interfacial adhesive layer | |
| JP2018523315A (en) | Fan-out type package structure embedded in silicon substrate and manufacturing method thereof | |
| CN101621041B (en) | Packaging structure with reconfiguration chip and method thereof | |
| CN101567322B (en) | Encapsulating structure and encapsulating method of chip | |
| CN101615583B (en) | Chip stacking structure forming method | |
| CN101477955B (en) | Encapsulation structure and method for tablet reconfiguration | |
| CN101615584B (en) | Packaging method of chip reconfiguration structure | |
| TW200939407A (en) | Multi-chip package structure and the method thereof | |
| CN101477956A (en) | Encapsulation structure and method for tablet reconfiguration | |
| CN101436553B (en) | Method for manufacturing package structure with reconfigured chip by metal projection | |
| CN101609822A (en) | Encapsulating structure that chip reconfigures and method thereof | |
| CN101452862B (en) | Encapsulation method with grains reconfigured | |
| CN100590823C (en) | Method for making registration mark used in packaging structure of crystal grain rearrangement | |
| CN101465299B (en) | Method for manufacturing grind used in encapsulation structure of chip reconfiguration | |
| CN101488462B (en) | Modulated multi-die package construction and method thereof | |
| US20070281393A1 (en) | Method of forming a trace embedded package | |
| CN100576478C (en) | The method for packing that crystal grain reconfigures | |
| CN101572237B (en) | Encapsulation structure and encapsulation method for modularization crystal grains | |
| CN101447437B (en) | Encapsulation structure for reconfiguring crystal grain and preconfigured fan-out structure used thereinto | |
| CN101436552B (en) | Method for manufacturing package structure with reconfigured crystal particle by net-shaped structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110615 |