CN101599480B - Semiconductor chip encapsulating structure - Google Patents
Semiconductor chip encapsulating structure Download PDFInfo
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- CN101599480B CN101599480B CN2008100384595A CN200810038459A CN101599480B CN 101599480 B CN101599480 B CN 101599480B CN 2008100384595 A CN2008100384595 A CN 2008100384595A CN 200810038459 A CN200810038459 A CN 200810038459A CN 101599480 B CN101599480 B CN 101599480B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a semiconductor chip encapsulating structure comprising a first chip, a first power supply loop line, a second power supply loop line, a second chip and a plurality of second power supply weld lines, wherein the first chip has a central region and a peripheral region and comprises a plurality of first power supply contact mats and a plurality of second power supply contact mats positioned on the top surface of the first chip; the first power supply loop line and the second power supply loop line are arranged in the first chip and respectively electrically connected to the plurality of first power supply contact mats and the plurality of second power supply contact mats; the second chip is fixed on the central region of the first chip and comprises a plurality of power supply contact mats arranged on the top surface of the second chip; and the plurality of second power supply weld lines are respectively electrically connected to the plurality of power supply contact mats of the second chip and the plurality of second power supply contact mats.
Description
Technical field
The invention relates to a kind of semiconductor chip package, particularly relevant for a kind of multicore sheet (multi-chip) encapsulating structure of multiple power supply.
Background technology
Along with electronic product towards trend light, thin, short, little development, also (multi-chip package, MCP) structural development is to reach multi-functional and high performance requirements towards multicore sheet encapsulation for the encapsulating structure of semiconductor chip.Existing multichip packaging structure is to need the dissimilar semiconductor chip of different operating power supply, and for example logic chip, analog chip, control chip or memory chip are incorporated in the single encapsulating structure.In order to reach the power supply requirement of existing multichip packaging structure, the I/O of general use multiple power supply chip (multi-powerchip) and encapsulating structure electrically connects (input/output electrical connections) (for example contact mat or lead), to supply and also electrically to completely cut off different operating powers.
Because multichip packaging structure needs different operating powers, the layout of its power line (power net) circuit is comparatively complicated.Therefore, prior art is the power line with segmentation (segment), is arranged in the multiple power supply chip, and is electrically connected to corresponding contact mat, and the substrate via BGA Package (BGA) winds the line to the package pin positions (pin assignment) of appointment again.Yet, in the existing multichip packaging structure, connect the position that the position of the chip contact mat of different electrical power must the corresponding segments power line and can't change, can cause the waste of layout area, and BGA Package (BGA) can the raising packaging cost.
In this technical field, have and need a kind of high density of integration and semiconductor chip package cheaply.
Summary of the invention
One embodiment of the invention provide a kind of semiconductor chip package, comprise one first chip, be with one first power operation, it has a center and an external zones, above-mentioned first chip comprises a plurality of first power supply contact mats and a plurality of second source contact mat, be arranged in the above-mentioned external zones, and be positioned on the end face of above-mentioned first chip; One first a power supply ringed line and a second source ringed line, be arranged in above-mentioned first chip, the wherein above-mentioned first power supply ringed line is to be electrically connected to above-mentioned a plurality of first power supply contact mat, and above-mentioned second source ringed line is to be electrically connected to above-mentioned a plurality of second source contact mat; One second chip is with second source operation, is fixed on the above-mentioned center of above-mentioned first chip, and above-mentioned second chip comprises a plurality of power supply contact mats, is arranged on the end face of above-mentioned second chip; Many second source bonding wires are electrically connected to a plurality of power supply contact mats and above-mentioned a plurality of second source contact mat of above-mentioned second chip respectively.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 a is the vertical view of the semiconductor chip package of one embodiment of the invention.
Fig. 1 b is the profile along the A-A ' tangent line of Fig. 1 a, and it shows the semiconductor chip package of one embodiment of the invention.
Fig. 2 a is the part enlarged drawing of Fig. 1 a, the electrical connection of the first power supply contact mat, second source contact mat, the first power supply ringed line and the second source ringed line of the semiconductor chip package of its demonstration one embodiment of the invention.
Fig. 2 b is the profile along the B-B ' tangent line of Fig. 2 a, the first power supply ringed line of the semiconductor chip package of its demonstration one embodiment of the invention and the electrical connection of the first power supply contact mat.
Fig. 2 c is the profile along the C-C ' tangent line of Fig. 2 a, the second source ringed line of the semiconductor chip package of its demonstration one embodiment of the invention and the electrical connection of second source contact mat.
The primary clustering symbol description:
200～the first chips;
202～center;
203,211～edge;
204～external zones;
206,206a, 206b, 206c, 206d～second source contact mat;
207,207a, 207b～first power supply contact mat;
208,217～contact mat;
210～the second chips;
212,214～bonding material;
216,216a, 216b, 216c, 216d～power supply contact mat;
220,220a, 220b, 220c, 220d～second source bonding wire;
222,222a, 222b～first power supply bonding wire;
224～lead frame;
226～put crystal cup;
228,228a, 228b, 229～pin;
230～encapsulating material;
240～zone;
242～the first power supply interlayer connectors;
244～second source interlayer connector;
250～wafer;
252,252a, 252b, 252c, 252d～dielectric layer;
254～semiconductor subassembly;
270～the first power supply ringed lines;
280～second source ringed line;
500～semiconductor chip package.
Embodiment
Below describe and be accompanied by the example of description of drawings in detail with each embodiment, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover, the part of each assembly will be to describe explanation respectively in the accompanying drawing, it should be noted that, the assembly that does not illustrate among the figure or describe, for having the form of knowing usually known to the knowledgeable in the affiliated technical field, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
Fig. 1 a is the vertical view of the semiconductor chip package 500 of one embodiment of the invention.Fig. 1 b is the profile along the A-A ' tangent line of Fig. 1 a.In an embodiment of the present invention, semiconductor chip package 500 can be leaded package (the lead frame based package) structure of the multicore sheet (multi-chip) of integrating multiple power supply, for example can be four limit flat packaging (quad flat package, the QFP) structure of a multicore sheet.Shown in Fig. 1 a and Fig. 1 b, semiconductor chip package 500 comprises a lead frame 224, it has the crystal cup of putting 226 and a plurality of pin 228 and 229, and wherein pin 228 can be considered power supply (power) I/O (input/output, I/O) power pins 228 of electrically connect.One first chip 200 can be fixed in by a bonding material 212 of for example elargol (silver paste) or epoxy resin (epoxy resin) and put on the crystal cup 226.In an embodiment of the present invention, first chip 200 can be a multiple power supply chip (multi-power chip) 200.For instance, first chip 200 can be a chip 200 with electric potential transfer circuit (level shifter).Generally speaking, the operating power that offers chip is fixed, and has chip 200 convertible its operating powers of electric potential transfer circuit, needs the zone of different operating power supply or the chip of different operating power supply to use with supply.First chip 200 is with first power operation, and it has a center 202 and an external zones 204.First chip 200 comprises a plurality of first power supply contact mats 207, a plurality of second source contact mat 206 and a plurality of contact mat 208.The aforesaid first power supply contact mat 207, second source contact mat 206 and contact mat 208 are the external zoness 204 that are arranged in first chip 200, and be positioned on the end face of first chip 200, and can be arranged in an annular array along the edge 203 of first chip 200.In an embodiment of the present invention, the first power supply contact mat 207, second source contact mat 206 can be used as the I/O (input/output of the power supply (power) of first chip 200, I/O) electrically connect, and contact mat 208 can be used as the signal (signal) of first chip 200 or I/O (I/O) electrically connect of ground connection (ground).First chip 200 comprises one first a power supply ringed line 270 and a second source ringed line 280, is arranged in first chip 200.As shown in Figure 1a, the first power supply ringed line 270 and second source ringed line 280 are parallel to each other, and electrically isolated mutually.In an embodiment of the present invention, the first power supply ringed line 270 and second source ringed line 280 can be positioned at all first power supply contact mats 207, all second source contact mats 206 and all contact mats 208 under, and be parallel to the formed annular array of above-mentioned contact mat in fact.In another embodiment of the present invention, the first power supply ringed line 270 and second source ringed line 280 can only be arranged in the external zones 204 of first chip 200, but be not positioned at all first power supply contact mats 207, all second source contact mats 206 and all contact mats 208 under.The first power supply ringed line 270 is to be electrically connected to each first power supply contact mat 207, and second source ringed line 280 is to be electrically connected to each second source contact mat 206.In addition, first chip 200 also can comprise earth connection or holding wire (figure does not show).Many first power supply bonding wires 222 are electrically connected to the pin 228 and the first power supply contact mat 207 respectively.For instance, the first power supply bonding wire 222a is electrically connected to the pin 228a and the first power supply contact mat 207a, and the first power supply bonding wire 222b is electrically connected to the pin 228b and the first power supply contact mat 207b.
In addition, shown in Fig. 1 a and Fig. 1 b, semiconductor chip package 500 comprises one second chip 210, and wherein the area of first chip 200 can be greater than the area of second chip 210.In an embodiment of the present invention, second chip 210 can be a core logic chipset (core logic chip) 210, it is operated with second source, and can be fixed on the center 202 of first chip 200 by a bonding material 214 of for example elargol (silver paste) or epoxy resin (epoxy resin).Second chip 210 comprises a plurality of power supply contact mats 216 and a plurality of contact mat 217, is positioned on the end face of second chip 210, and can be arranged in an annular array along edge 211 settings of second chip 210.In an embodiment of the present invention, power supply contact mat 216 can be used as the I/O (input/output of the power supply (power) of second chip 210, I/O) electrically connect, and contact mat 217 can be used as the signal (signal) of second chip 210 or I/O (I/O) electrically connect of ground connection (ground).The power supply contact mat 216 of second chip 210 can be electrically connected to a plurality of second source contact mats 206 of first chip 200 via many second source bonding wires 220 respectively, with second source ringed line 280 power supply to the second chips 210 by first chip 200.For instance, power supply contact mat 216a can be electrically connected to the second source contact mat 206a of first chip 200 via second source bonding wire 220a, power supply contact mat 216b can be electrically connected to the second source contact mat 206b of first chip 200 via second source bonding wire 220b, power supply contact mat 216c can be electrically connected to the second source contact mat 206c of first chip 200 via second source bonding wire 220c, and power supply contact mat 216d can be electrically connected to the second source contact mat 206d of first chip 200 via second source bonding wire 220d.For convenience of description, the icon of the embodiment of the invention only shows the I/O (input/output of first chip 200 and second chip, 210 power supplys (power), I/O) electrically connect, other for example I/O (I/O) electrically connect of signal (signal) or ground connection (ground) do not show at this.
Shown in Fig. 1 a and Fig. 1 b, semiconductor chip package 500 also comprises an encapsulating material 230, coats first chip 200, second chip 210, puts crystal cup 226, pin 228 and 229 inside part, the first power supply bonding wire 222 and second source bonding wire 220.In an embodiment of the present invention, the material of encapsulating material 230 can comprise for example macromolecular material of epoxy resin (epoxy resin).
Fig. 2 a is the part enlarged drawing of Fig. 1 a, the electrical connection of the first power supply contact mat 207a to 207b, the second source contact mat 206b to 206d of the semiconductor chip package 500 of its demonstration one embodiment of the invention and the first power supply ringed line 270, second source ringed line 280.Fig. 2 b is the profile along the B-B ' tangent line of Fig. 2 a, first power supply ringed line 270 of the semiconductor chip package of its demonstration one embodiment of the invention and the electrical connection of the first power supply contact mat 207b.Fig. 2 c is the profile along the C-C ' tangent line of Fig. 2 a, the second source ringed line 280 of the semiconductor chip package of its demonstration one embodiment of the invention and the electrical connection of second source contact mat 260d.For convenience of description, the first power supply bonding wire 222 as shown in Figure 1a and second source bonding wire 220 do not show at this.Shown in Fig. 2 a, the first power supply ringed line 270 and second source ringed line 280 are positioned under the first power supply contact mat 207a to 207b, second source contact mat 206b to 206d and the contact mat 208, and are parallel to the orientation of the first power supply contact mat 207a to 207b, second source contact mat 206b to 206d and contact mat 208 in fact.A plurality of first power supply interlayer connectors 242 are arranged in first chip 200, and the first power supply contact mat 207a to 207b is electrically connected to the first power supply ringed line 270 via the first power supply interlayer connector 242 respectively.A plurality of second source interlayer connectors 244 are arranged in first chip 200, and second source contact mat 206b to 206d is electrically connected to second source ringed line 280 via second source interlayer connector 244 respectively.Shown in 2b, 2c figure, in an embodiment of the present invention, the first power supply ringed line 270 and second source ringed line 280 are to be positioned on the wafer 250, and the first power supply ringed line 270 or second source ringed line 280 can be electrically connected to the semiconductor subassembly 254 that is positioned on the wafer 250.The first power supply ringed line 270 and second source ringed line 280 are to be arranged in the interconnect structure 252 that comprises dielectric layer 252a to 252d.In an embodiment of the present invention, the first power supply ringed line 270 and second source ringed line 280 can be arranged at among one deck dielectric layer 252b.Perhaps, in other embodiment of the present invention, the first power supply ringed line 270 and second source ringed line 280 can be arranged on (figure shows) in the dielectric layer of different layers, and are electrically insulated from each other.Shown in Fig. 2 b, the first power supply ringed line 270 is to be electrically connected to the first power supply contact mat 207b that is arranged in dielectric layer 252d via the first power supply interlayer connector 242.Shown in Fig. 2 c, second source ringed line 280 is to be electrically connected to the second source contact mat 206d that is arranged in dielectric layer 252d via second source interlayer connector 244.The first power supply contact mat 207 that first above-mentioned power supply ringed line 270 and second source ringed line 280 are corresponding with it and the electric connection mode of second source contact mat 206, the first power supply contact mat 207 and second source contact mat 206 are disposed arbitrarily, make it more flexible.Shown in Fig. 2 a, one of them of the first power supply contact mat 207, for example the first power supply contact mat 207a can be respectively adjacent to second source contact mat 206b and 206c along the both sides of the column direction of above-mentioned annular array.Perhaps, one of them of second source contact mat 206, for example second source contact mat 206c is respectively adjacent to first power supply contact mat 207a and the 207b along the both sides of the column direction of above-mentioned annular array.Above-mentioned first power supply contact mat 207 and second source contact mat 206 can be and be staggered, or are spaced with the optional position.In addition, the quantity of the power supply contact mat of the different electrical power that the power supply ringed line of above-mentioned different electrical power is corresponding with it is also unrestricted, can decide according to design requirement.
Owing to be in first chip 200 of multiple power supply chip for example, the power supply ringed line of many different electrical power that are parallel to each other can be electrically connected to the power supply contact mat of different electrical power respectively respectively via different power supply interlayer connectors, to input or output different power supplys respectively, need the zone of different operating voltage or the chip of different operating voltage to use with supply, for example can supply with the operating power of second chip 210 via second source ringed line 280, can save the area of power line layout, and save the quantity that input and output (IO) electrically connect, make first chip 200 of the embodiment of the invention and second chip 210 can utilize the lower lead frame encapsulation structure of price to finish.In addition, under the situation about can't change for the foundation design rule in the pin position (pin assignment) of each pin of lead frame encapsulation structure, the electric connection mode of above-mentioned power supply ringed line and power supply contact mat can make the power supply contact mat of different electrical power dispose arbitrarily, make it more flexible, form the semiconductor chip package 500 of the embodiment of the invention with the collocation lead frame.Therefore, the semiconductor chip package 500 of the embodiment of the invention can not need the higher ball grid array package structure of price (BGA), can finish the purpose of the semiconductor chip package of multicore sheet.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (12)
1. semiconductor chip package comprises:
One first chip is with one first power operation, and it has a center and an external zones, and this first chip comprises:
A plurality of first power supply contact mats and a plurality of second source contact mat are arranged in this external zones, and are positioned on the end face of this first chip; And
One first a power supply ringed line and a second source ringed line are arranged in this first chip, and wherein this first power supply ringed line is to be electrically connected to this a plurality of first power supply contact mats, and this second source ringed line is to be electrically connected to this a plurality of second source contact mats;
One second chip is with second source operation, is fixed on this center of this first chip, and this second chip comprises a plurality of power supply contact mats, is arranged on the end face of this second chip; And
Many second source bonding wires are electrically connected to a plurality of power supply contact mats of this second chip and these a plurality of second source contact mats respectively.
2. semiconductor chip package as claimed in claim 1 is characterized in that also comprising:
A plurality of first power supply interlayer connectors are arranged in this first chip, and these a plurality of first power supply interlayer connectors are electrically connected to these a plurality of first power supply contact mats and this first power supply ringed line respectively; And
A plurality of second source interlayer connectors are arranged in this first chip, and these a plurality of second source interlayer connectors are electrically connected to these a plurality of second source contact mats and this second source ringed line respectively.
3. semiconductor chip package as claimed in claim 1 is characterized in that also comprising a lead frame, and it has the crystal cup of putting and a plurality of pin, and wherein this first chip is to be fixed in this to put on the crystal cup.
4. semiconductor chip package as claimed in claim 3 is characterized in that also comprising many first power supply bonding wires, is electrically connected to these a plurality of pins and these a plurality of first power supply contact mats respectively.
5. semiconductor chip package as claimed in claim 1 is characterized in that, this first power supply ringed line and this second source ringed line are parallel to each other, and electrically isolated mutually.
6. semiconductor chip package as claimed in claim 1 is characterized in that, this first power supply ringed line and this second source ringed line are positioned under all these a plurality of first power supply contact mats and all these a plurality of second source contact mats.
7. semiconductor chip package as claimed in claim 1 is characterized in that, these a plurality of first power supply contact mats and these a plurality of second source contact mats are to be arranged in an annular array.
8. semiconductor chip package as claimed in claim 7 is characterized in that, the both sides of one of them of these a plurality of first power supply contact mats are respectively adjacent to this different second source contact mats.
9. semiconductor chip package as claimed in claim 7 is characterized in that, the both sides of one of them of these a plurality of second source contact mats are respectively adjacent to this different first power supply contact mats.
10. semiconductor chip package as claimed in claim 7 is characterized in that, these a plurality of first power supply contact mats and these a plurality of second source contact mats are to be staggered.
11. semiconductor chip package as claimed in claim 1 is characterized in that, this first area of chip is greater than this second area of chip.
12. semiconductor chip package as claimed in claim 4, it is characterized in that also comprising an encapsulating material, coat this first chip, this second chip, this puts the inside part of crystal cup, these a plurality of pins, these many first power supply bonding wires and this many second source bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100384595A CN101599480B (en) | 2008-06-03 | 2008-06-03 | Semiconductor chip encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100384595A CN101599480B (en) | 2008-06-03 | 2008-06-03 | Semiconductor chip encapsulating structure |
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| Publication Number | Publication Date |
|---|---|
| CN101599480A CN101599480A (en) | 2009-12-09 |
| CN101599480B true CN101599480B (en) | 2011-06-15 |
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| CN2008100384595A Active CN101599480B (en) | 2008-06-03 | 2008-06-03 | Semiconductor chip encapsulating structure |
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| TW201530726A (en) * | 2014-01-29 | 2015-08-01 | Eorex Corp | Memory chip and memory storage device |
| TWI539565B (en) * | 2014-01-29 | 2016-06-21 | 森富科技股份有限公司 | Memory and layout method of memory ball pads |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1373511A (en) * | 2002-04-17 | 2002-10-09 | 威盛电子股份有限公司 | External power supply ring with multiple slender tapes for decreasing voltage drop of integrated circuit |
| CN1430267A (en) * | 2003-01-15 | 2003-07-16 | 威盛电子股份有限公司 | Ballgrid array parkaging body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1373511A (en) * | 2002-04-17 | 2002-10-09 | 威盛电子股份有限公司 | External power supply ring with multiple slender tapes for decreasing voltage drop of integrated circuit |
| CN1430267A (en) * | 2003-01-15 | 2003-07-16 | 威盛电子股份有限公司 | Ballgrid array parkaging body |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2001-127199A 2001.05.11 |
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| CN101599480A (en) | 2009-12-09 |
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