CN101589467B - Semiconductor device comprising electromigration prevention film and manufacturing method thereof - Google Patents
Semiconductor device comprising electromigration prevention film and manufacturing method thereof Download PDFInfo
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- CN101589467B CN101589467B CN200880002910.6A CN200880002910A CN101589467B CN 101589467 B CN101589467 B CN 101589467B CN 200880002910 A CN200880002910 A CN 200880002910A CN 101589467 B CN101589467 B CN 101589467B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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Abstract
A semiconductor device includes a semiconductor substrate, a plurality of wiring lines which are provided on one side of the semiconductor substrate and which have connection pad portions, and a plurality of columnar electrodes respectively provided on the connection pad portions of the wiring lines, each of the columnar electrodes including an outer peripheral surface and a top surface. An electromigration prevention film is provided on at least the surfaces of the wiring lines. A sealing film is provided around the outer periphery surfaces of the columnar electrodes.
Description
Technical field
The present invention relates to comprise the semiconductor device and the manufacturing approach thereof of electromigration prevention film.
Background technology
In the open No.2004-207306 of Japanese patent application KOKAI, a kind of semiconductor device that is called as chip size packages (CSP) has been described.This semiconductor device comprises Semiconductor substrate, and said substrate has a plurality of connection pads that are arranged on its upper surface.On the upper surface that is arranged at the dielectric film on the Semiconductor substrate, a plurality of wirings are set, make them be electrically connected with corresponding connection pads.Columnar electrode is arranged on the connection pads respective upper surfaces partly of these wirings.Diaphragm seal is arranged on the upper surface of wiring and dielectric film, makes that the upper surface of sealing film is concordant with the upper surface of columnar electrode.Soldered ball is separately positioned on the upper surface of columnar electrode.
In above-mentioned conventional semiconductor device, directly the diaphragm seal of capping wiring is processed by epoxy resin, thereby exists metal (copper) ion in the wiring to be diffused into the problem in the diaphragm seal because of electromigration takes place, and this is a factor that between wiring, causes short circuit.
In addition, the epoxy resin processed by for example silica of wherein filler can be used as the material of diaphragm seal.In this semiconductor device, wiring may receive the mechanical damage of filler.Rupture the problem that the miniaturization of existence wiring is restricted because of mechanical damage in order to prevent wiring.
Summary of the invention
Therefore the purpose of this invention is to provide a kind of semiconductor device and manufacturing approach thereof, even its short circuit that causes because of electromigration between can preventing to connect up and be used as at the resin that comprises filler also can to prevent to connect up under the situation of diaphragm seal material and receive the mechanical damage of filler at an easy rate.
The semiconductor device of the one side of claim 1 comprises according to the present invention:
Semiconductor substrate;
The a plurality of wirings that are arranged on a side of Semiconductor substrate and have the connection pads part;
Be separately positioned on a plurality of columnar electrodes on the connection pads part of wiring, each all comprises outer surface and top surface these columnar electrodes;
At least be arranged on the lip-deep electromigration prevention film of wiring; And
The diaphragm seal that is provided with around the outer surface of columnar electrode.
A kind of semiconductor device of the second aspect of claim 6 according to the present invention comprises:
Semiconductor substrate;
Be arranged on a plurality of wirings of the upside of Semiconductor substrate;
Be arranged on the inorganic insulating membrane that has opening on the surface of wiring and in the corresponding part of connection pads part with wiring;
The outer embrane of processing by organic resin that is arranged on the upper surface of inorganic insulating membrane and has opening on the upside of Semiconductor substrate and in the corresponding part of connection pads part with wiring; And
Be arranged in the opening of inorganic insulating membrane and among the pallial opening with top and a plurality of columnar electrodes of partly being electrically connected with the connection pads of wiring.
Manufacturing approach of the present invention according to third aspect present invention comprises:
On the upside of Semiconductor substrate, form a plurality of wirings;
On the connection pads part of wiring, form a plurality of columnar electrodes;
Forming electromigration prevention film on the surface on the surface of wiring, at columnar electrode and on the upside in Semiconductor substrate;
On electromigration prevention film, form diaphragm seal; And
Upper surface one side of grinding-in film is to expose the upper surface of columnar electrode.
Manufacturing approach of the present invention according to fourth aspect present invention comprises:
On the upside of Semiconductor substrate, form a plurality of wirings;
On the connection pads part of wiring, form a plurality of columnar electrodes;
Forming electromigration prevention film on the surface on the surface of wiring, at columnar electrode and on the upside in Semiconductor substrate;
Removal is formed on the lip-deep electromigration prevention film on the top of columnar electrode;
On electromigration prevention film and columnar electrode, form diaphragm seal; And
Upper surface one side of grinding-in film is to expose the upper surface of columnar electrode.
Manufacturing method for semiconductor device according to fifth aspect present invention comprises:
On the upside of Semiconductor substrate, form a plurality of wirings;
On the surface of wiring, form inorganic insulating membrane, this inorganic insulating membrane has opening in the corresponding part of connection pads part with wiring;
Form the outer embrane of being processed by organic resin at the upside of Semiconductor substrate and on inorganic insulating membrane, said outer embrane has opening in the corresponding part of connection pads part with wiring; And
Through metallide in the opening of inorganic insulating membrane and outside among the opening of mantle with above form columnar electrode.
According to the present invention, electromigration prevention film is arranged on the surface of wiring at least, and the short circuit between the wiring that therefore can prevent to be caused by electromigration.And electromigration prevention film plays the effect of diaphragm, receives the mechanical damage of filler at an easy rate even under the resin that comprises filler is used as the situation of diaphragm seal material, also can prevent to connect up like this.
Description of drawings
Fig. 1 is the cutaway view as the semiconductor device of first embodiment of the invention;
Fig. 2 is the cutaway view of the initial preparation assembly in an instance of the method for making semiconductor device shown in Figure 1;
Fig. 3 is the cutaway view of the step after Fig. 2;
Fig. 4 is the cutaway view of the step after Fig. 3;
Fig. 5 is the cutaway view of the step after Fig. 4;
Fig. 6 is the cutaway view of the step after Fig. 5;
Fig. 7 is the cutaway view of the step after Fig. 6;
Fig. 8 is the cutaway view of the step after Fig. 7;
Fig. 9 is the cutaway view of the step after Fig. 8;
Figure 10 is the cutaway view of the step after Fig. 9;
Figure 11 is the cutaway view as the semiconductor device of second embodiment of the invention;
Figure 12 is the cutaway view of the predetermined process in an instance of the method for making semiconductor device shown in Figure 11;
Figure 13 is the cutaway view of the step after Figure 12;
Figure 14 is the cutaway view as the semiconductor device of third embodiment of the invention;
Figure 15 is the cutaway view of the assembly of the initial preparation in an instance of the method for making semiconductor device shown in Figure 14;
Figure 16 is the cutaway view of the step after Figure 15;
Figure 17 is the cutaway view of the step after Figure 16;
Figure 18 is the cutaway view of the step after Figure 17;
Figure 19 is the cutaway view of the step after Figure 18;
Figure 20 is the cutaway view of the step after Figure 19;
Figure 21 is the cutaway view of the step after Figure 20;
Figure 22 is the cutaway view of the step after Figure 21;
Figure 23 is the cutaway view of the step after Figure 22;
Figure 24 is the cutaway view of the step after Figure 23;
Figure 25 is the cutaway view of the step after Figure 24;
Figure 26 is the cutaway view as the semiconductor device of four embodiment of the invention;
Figure 27 is the cutaway view of the predetermined process in an instance of the method for making semiconductor device shown in Figure 26;
Figure 28 is the cutaway view of the step after Figure 27;
Figure 29 is the cutaway view of the step after Figure 28;
Figure 30 is the cutaway view of the step after Figure 29;
Figure 31 is the cutaway view of the step after Figure 30;
Figure 32 is the cutaway view of the step after Figure 31;
Figure 33 is the cutaway view of the step after Figure 32; And
Figure 34 is the cutaway view as the semiconductor device of fifth embodiment of the invention.
Embodiment
(first execution mode)
Fig. 1 representes the cutaway view as the semiconductor device of first embodiment of the invention.This semiconductor device is called as CSP, and comprises silicon substrate (Semiconductor substrate) 1.The integrated circuit (not shown) be arranged on the upper surface of silicon substrate 1 or among, and be arranged on the peripheral part of the upper surface of silicon substrate 1 by a plurality of connection pads 2 of processing of metal (for example aluminium based metal), make these connection pads be electrically connected with integrated circuit.
The dielectric film of being processed by inorganic material (for example silica or silicon nitride) 3 is arranged on the upper surface of the connection pads 2 except that the center of connection pads 2 and on the upper surface of silicon substrate 1.Expose through the opening 4 that is arranged on the dielectric film 3 at the center of connection pads 2.(for example the electric insulation diaphragm 5 processed of polyimide resin or polyparaphenylene Ben Bing Er oxazole (PBO) resin is arranged on the upper surface of dielectric film 3 by inorganic material.Opening 6 is arranged in opening 4 corresponding parts diaphragm 5 and dielectric film 3.Recess or groove 7 are arranged on the peripheral part of diaphragm 5.
A plurality of wirings 8 are arranged on the upper surface of diaphragm 5.Each wiring 8 all has double-decker, and it is made up of with the last metal level 10 that is become by the copper on the upper surface that is arranged on foundation metal layer 9 foundation metal layer 9 that is for example become by the copper on the upper surface that is arranged on diaphragm 5.One end of wiring 8 is electrically connected with connection pads 2 through the opening 4,6 of the aligning of dielectric film 3 and diaphragm 5.The columnar electrode 11 that is made of copper is arranged on wiring 8 the other end or on the upper surface of connection pads part.
Process and part is given prominence to electromigration prevention film 12 with the outer surface of capping columnar electrode 11 cylindrically and is arranged on the surface of wiring 8 and on the upper surface of diaphragm 5 by polyimide resin or PBO resin.Recess 13 with the recess 7 corresponding parts of diaphragm 5 in be arranged on the peripheral part of electromigration prevention film 12.Therefore, the outer surface of diaphragm 5 is preferably concordant with the outer surface of electromigration prevention film 12.
The recess 7 that passes through diaphragm 5 and electromigration prevention film 12 at dielectric film 3; The diaphragm seal of being processed by epoxy resin 14 is set on 13 upper surfaces that expose and on the upper surface of electromigration prevention film 12; Said epoxy resin comprises the filler of being processed by for example silica, makes that the upper surface of said diaphragm seal 14 can be concordant with the upper surface of columnar electrode 11.Sealing film 14 is through the side surface of the cylindrical projections sealing columnar electrode 11 of electromigration prevention film 12.Soldered ball 15 is separately positioned on the upper surface of corresponding columnar electrode 11.
Below, with an instance describing the method for making said semiconductor device.At first; As shown in Figure 2; Prepare such assembly; Dielectric film 3 that wherein on the upside that is in the silicon substrate (hereinafter referred to as semiconductor wafer 21) under the wafer state, forms the connection pads 2 processed by aluminium based metal, processes by for example silica or silicon nitride and the diaphragm of processing by for example polyimide resin or PBO resin 5, and through passing the center that opening 4,6 that dielectric film 3 and diaphragm 5 form exposes connection pads 2.
In this case, the integrated circuit (not shown) with predetermined function is formed in the zone of formation semiconductor device of upper surface of semiconductor wafer 21, and every group of connection pads 2 be formed on appropriate section in integrated circuit in each be electrically connected.In Fig. 2, corresponding with line by the zone of Reference numeral 22 expressions.Recess that extends along the upper surface of wafer 21 or groove 7 be formed on diaphragm 5 with line 22 corresponding parts in and be formed on its both sides.
Then, as shown in Figure 3, foundation metal layer 9 is formed on the center upper surface that the opening 4,6 that passes through dielectric film 3 and diaphragm 5 of connection pads 2 exposes, on the dielectric film 3 and on the entire upper surface of diaphragm 5.The formation method and the conductive material of this foundation metal layer 9 are unrestricted; And can only be the copper layer that forms through electroless plating; Can only be the copper layer that forms through sputter, perhaps can be through on thin layer (titanium layer that for example forms through sputter), carrying out the copper layer that sputter forms.
Then, electroplate etchant resist formation film and be formed on the upper surface of foundation metal layer 9, and this film is patterned to form plating etchant resist 23.Opening 24 is formed on electroplates going up in the regional corresponding part of metal level 10 with formation of etchant resist 23.Afterwards, utilize foundation metal layer 9 to implement to have the metallide of copper, on the upper surface that is in the part in the opening 24 of electroplating etchant resist 23 of foundation metal layer 9, form metal level 10 thus as the electroplating current path.Subsequently, remove plating etchant resist 23.
Then, as shown in Figure 4, electroplate etchant resist formation film and be formed on the upper surface of metal level 10 and foundation metal layer 9, and this film is patterned to form plating etchant resist 25.In this case, opening 26 be formed on electroplate etchant resist 25 with form the connection pads part just in the regional corresponding part of columnar electrode 11 that goes up metal level 10.Afterwards, utilize foundation metal layer 9 to implement to have the metallide of copper, make columnar electrode 11 be formed on being on the connection pads respective upper surfaces partly in the opening 26 of electroplating etchant resist 25 of metal level 10 as the electroplating current path.
Then, remove and electroplate etchant resist 25, and utilize subsequently and go up metal level 10 as mask etching and the foundation metal layer 9 of removing the zone that is not in metal level 10 belows.Thereby, foundation metal layer 9 belows that only are retained in metal level 10 as shown in Figure 5.In this state, wiring 8 is made up of foundation metal layer 9 and last metal level 10 on the upper surface that is formed on foundation metal layer 9.
Then, through proper method (for example whirl coating) on wiring 8 surface, at the electromigration prevention film 12 that outer surface (upper surface and outer circumferential side surface) is gone up and formation is processed by for example polyimide resin or PBO resin on the upper surface of diaphragm 5 of columnar electrode 11.Afterwards, as shown in Figure 6, form recess 13 through photoetching process in recess 7 corresponding parts electromigration prevention film 12 and diaphragm 5.
Then; As shown in Figure 7; For example pass through silk screen print method or whirl coating at recess 7 through diaphragm 5 and electromigration prevention film 12; Form the diaphragm seal of processing by for example epoxy resin 14 on the upper surface of 13 dielectric films 3 that expose and the upper surface of electromigration prevention film 12; Said epoxy resin comprises the filler of being processed by for example silica, makes that the thickness of sealing film 14 can be bigger than the height of columnar electrode 11 (thickness that comprises the part on the upper surface that is formed on columnar electrode 11 of electromigration prevention film 12).
Then; Upper surface one side of diaphragm seal 14 is suitably ground and is removed; With the upper surface of the cylindrical part on the outer surface that is formed on columnar electrode 11 of upper surface that exposes columnar electrode 11 as shown in Figure 8 and electromigration prevention film 12, and the upper surface of the diaphragm seal 14 that comprises these exposing surfaces is flattened.
Then, as shown in Figure 9, soldered ball 15 is formed on the upper surface of corresponding columnar electrode 11.Afterwards, shown in figure 10, along tangent line 22 cutting semiconductor chips 21, dielectric film 3 and diaphragm seal 14, obtain a plurality of semiconductor devices shown in Figure 1 thus.
In thus obtained semiconductor device, the surface (upper surface and side surface) of wiring 8 and the outer surface of columnar electrode 11 are coated with the electromigration prevention film of being processed by for example polyimide resin or PBO 12, and be as shown in Figure 1.Therefore, between wiring, any electromigration can be do not produced, the short circuit that produces because of 8 the electromigration of connecting up can be prevented thus.
In addition; In semiconductor device shown in Figure 1; Wiring 8 surface coverage has the electromigration prevention film of being processed by for example polyimide resin or PBO resin 12, is used as the mechanical damage that wiring 8 under the situation of material of diaphragm seal 14 can not be easy to receive filler yet even make at the epoxy resin that comprises the filler of being processed by for example silica.
In semiconductor device shown in Figure 1; The whole outer surface of columnar electrode 11 is coated with electromigration prevention film 12; And soldered ball 15 only is arranged on the upper surface of columnar electrode 11, makes the upper surface of cylindrical part of outer surface of covering columnar electrode 11 of electromigration prevention film 12 in the upper surface of diaphragm seal 14, expose.In this case, if electromigration prevention film 12 is processed by polyimide resin or PBO resin, anti-damp reliability reduces because of these resins have moisture absorption.Therefore second execution mode of the present invention that can improve anti-damp reliability will be described below.
(second execution mode)
Figure 11 representes the cutaway view as the semiconductor device of second embodiment of the invention.The difference of this semiconductor device and semiconductor device shown in Figure 1 is that the following outer surface of columnar electrode 11 is coated with electromigration prevention film 12; And the last outer surface of columnar electrode 11 is coated with diaphragm seal 14, makes the upper surface of cylindrical part of electromigration prevention film 12 in the upper surface of diaphragm seal 14, not expose.
Below, with an instance describing the method for making this semiconductor device.In this case; After step shown in Figure 6; Through whirl coating for example on the recess that passes through diaphragm 5 and electromigration prevention film 12 of dielectric film 3 or the upper surface that groove 7,13 exposes and removing formation etchant resist 41 on the upper surface of the part the top of cylindrical part of the electromigration prevention film 12 on the outer surface that is formed on columnar electrode 11 shown in figure 12 on the electromigration prevention film 12.In this case, the thickness of the part on the upper surface that is formed on electromigration prevention film 12 of etchant resist 41 is height roughly half the of columnar electrode 11.
Then; Obtain etching and removal on the last outer surface that is formed on columnar electrode 11 of electromigration prevention film 12 and than the outstanding higher cylindrical part of the upper surface of etchant resist 41, make outstanding higher shown in figure 13 exposing of last outer surface of upper surface of ratio etchant resist 41 of columnar electrode 11.Subsequently, the same with manufacturing approach in above-mentioned first execution mode, forming step, soldered ball through diaphragm seal, to form step and scribe step acquisition structure shown in figure 11 be a plurality of semiconductor devices that the last outer surface of columnar electrode 11 is coated with diaphragm seal 14.
In thus obtained semiconductor device; The last outer surface of columnar electrode 11 and the upper surface diaphragm seal of being processed by fluid-tight epoxy resin 14 that is coated with shown in figure 11 that also has the cylindrical part of electromigration prevention film 12 thus make anti-damp reliability be improved.In this case, when diaphragm seal 14 is processed by the epoxy resin that comprises the filler that silica for example processes, also can improve anti-damp reliability.
(the 3rd execution mode)
Figure 14 representes the cutaway view as the semiconductor device of the 3rd execution mode of the present invention.This semiconductor device is called as CSP, and comprises silicon substrate (Semiconductor substrate) 1.The integrated circuit (not shown) is arranged on the upper surface of silicon substrate 1, and is arranged on the peripheral part of the upper surface of silicon substrate 1 by a plurality of connection pads 2 of processing of metal (for example aluminium based metal), makes these connection pads link to each other with integrated circuit.
By comprising on the upper surface that first inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride 16 is arranged on the connection pads 2 except the center of connection pads 2 and on the upper surface of silicon substrate 1.Expose through the opening 4 that is arranged on first inorganic insulating membrane 16 at the center of connection pads 2.The organic protective film of being processed by organic material (for example polyimide resin or epoxy resin) (organic insulating film) 40 is arranged on the upper surface of first inorganic insulating membrane 16.Opening 6 is arranged in opening 4 corresponding parts organic protective film 40 and first inorganic insulating membrane 16.
The foundation metal layer 9 that is become by for example copper is arranged on the upper surface of organic protective film 40.The upper electrode layer 10 that is made of copper is arranged on the entire upper surface of foundation metal layer 9, and these layers constitute wiring 8.An end that comprises foundation metal layer 9 of wiring 8 is electrically connected with connection pads 2 through the opening 4,6 of first inorganic insulating membrane 16 and organic protective film 40.By comprising on the upper surface that second inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride 19 is arranged on wiring 8 and organic protective film 40.Opening 20 be formed on second inorganic insulating membrane 19 with wiring 8 the corresponding part of connection pads part in.
The outer embrane of being processed by organic material (polyimide resin or epoxy resin) 29 is arranged on the upper surface of second inorganic insulating membrane 19.Opening 30 be formed on outer embrane 29 with wiring 8 the corresponding part of connection pads part in.The foundation metal layer of being processed by metal (for example copper) 37 is arranged on the connection pads upper surface partly that the opening 20,12 that pass through second inorganic insulating membrane 19 and outer embrane 29 of wiring 8 exposes, on the inner wall surface of the opening 20 of second inorganic insulating membrane 19, on the inner wall surface of the opening 30 of outer embrane 29 and outer embrane 29 on the upper surface of the part of the opening 30 of outer embrane 29.The columnar electrode 11 that is made of copper is arranged on the entire upper surface of foundation metal layer 37.
Each columnar electrode 11 is all divided 11a and is arranged on down the column electrode part and divides on upper surface and the perimembranous of 11a and the last column electrode part on the outer embrane 29 is divided 11b by the following column electrode part in the opening 20,12 that is arranged on second inorganic insulating membrane 19 and outer embrane 29.The following column electrode part of columnar electrode 11 divides 11a partly to be electrically connected with the corresponding connection pads of wiring 8 through the part in the opening 20,12 that is arranged on second inorganic insulating membrane 19 and outer embrane 29 of foundation metal layer 37.Soldered ball 15 is arranged on the outer circumferential side surface of the neighboring on the upper surface of being located at outer embrane 29 of foundation metal layer 37 and the last column electrode part of columnar electrode 11 is divided on the surface of 11b.
Below, with an instance describing the method for making this semiconductor device.At first; Shown in figure 15; Prepare such assembly, wherein: the connection pads part of processing by for example aluminium based metal 2, by comprising first inorganic insulating membrane 16 processed as the inorganic material of the silica of main component or silicon nitride and being formed on the upper surface of the silicon substrate (hereinafter referred to as semiconductor wafer 21) that is in wafer state by the organic protective film 40 that organic material (for example polyimide resin or epoxy resin) is processed; And expose through the opening 4,6 that is formed on first inorganic insulating membrane 16 and the organic protective film 40 at the center of connection pads 2.
In this case, the integrated circuit (not shown) with predetermined function is formed on the upper surface of semiconductor wafer 21 and forms in the zone of semiconductor device, and connection pads 2 is electrically connected with integrated circuit in being formed on appropriate section.In Figure 15, corresponding with line by the zone of Reference numeral 22 expressions.
Then; Shown in figure 16; The layer (hereinafter simply is called foundation metal layer 9 in order to simplify) that is used to form foundation metal layer 9 is formed on the entire upper surface of passing through the part that first inorganic insulating membrane 16 and opening 4,6 on the organic protective film 40 expose of connection pads 2 and on the entire upper surface of organic protective film 40.In this case, foundation metal layer 9 can be merely the copper layer that forms through electroless plating, can be merely the copper layer that forms through sputter, perhaps can be through on thin layer (titanium layer that for example forms through sputter), carrying out the copper layer that sputter forms.
Then, electroplate etchant resist 23 patterned/be formed on the upper surface of foundation metal layer 9.In this case, opening 24 be formed on electroplate etchant resist 23 with the regional corresponding part that forms wiring 8 (upper electrode layers 10) in.Afterwards; Utilize foundation metal layer 9 to implement to have the metallide of copper as the electroplating current path; Be formed for forming the layer (hereinafter simply is called metal level in order to simplify) of the last metal level of wiring 8 thus, it is formed on the upper surface in the opening 24 that foundation metal layer 9 is in plating etchant resist 23.Subsequently, separate to electroplate etchant resist 23, afterwards the foundation metal layer in the zone that is not in the metal level below 9 is utilized and gone up metal level and carry out etching and removal as mask, foundation metal layer 9 only is retained in below the metal level thus, and is shown in figure 17.
Then, shown in figure 18, by comprising that second inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride 19 is formed on the upper surface of wiring 8 and organic protective film 40 through plasma CVD method.In this case, the technological temperature that forms second inorganic insulating membrane 19 is preferably 250 ℃ or lower, makes the organic protective film of being processed by organic material (for example polyimide resin) 40 that has formed not receive fire damage.
For example, if adopt Si (OH
2H
5)
4(TEOS), can be the SiO of 500nm-1000nm then in 10-20 minute, forming thickness under about 120 ℃ technological temperature as process gas
2Film.If adopt SiH (OCH
3)
3(TMS), can be the SiO of 500nm-1000nm then in 10-20 minute, forming thickness under about 80 ℃ technological temperature as process gas
2Film.
Then, shown in figure 19, on the upper surface of second inorganic insulating membrane 19, form the outer embrane of processing by organic material (for example polyimide resin or epoxy resin) 29 through for example whirl coating.Afterwards, utilize the photomask (not shown) through photoetching process outside mantle 29 with wiring 8 the corresponding appropriate section of connection pads part in form opening 30.
Then, shown in figure 20, the positive etchant resist processed by for example phenolic resins is 39 patterned/be formed on the upper surface of outer embrane 29.In this case, opening 26 is formed in opening 30 corresponding parts etchant resist 39 and outer embrane 29 (just connect up 8 connection pads part).
Then, second inorganic insulating membrane 19 utilizes etchant resist 39 to bear dry etching in opening 30 corresponding parts second inorganic insulating membrane 19 and outer embrane 29 (just connect up 8 connection pads part), to form opening 20 as mask, and is shown in figure 21.In this case, dry etching can be for example general reactive ion etching (RIE) or can be the high-density plasma dry etching that hereinafter is described.
Then, separate etchant resist 39.In addition, can utilize outer embrane 29 to need not to adopt etchant resist 39 to implement dry etching as mask.Equally in this case, dry etching can be for example general reactive ion etching (RIE), perhaps can be the high-density plasma dry etching that hereinafter is described.
Then, shown in figure 22, through the sputter formation foundation metal layer 37 on the entire upper surface of mantle 29 on the upper surface of the connection pads part that the opening 20,12 that pass through second inorganic insulating membrane 19 and outer embrane 29 of wiring 8 exposes and outside of copper for example.Afterwards, electroplate etchant resist 27 patterned/be formed on the upper surface of foundation metal layer 37.In this case, be formed on than the opening 30 bigger openings 28 of outer embrane 29 and electroplate dividing in the regional corresponding part of 11b of etchant resist 27 with its last column electrode part that goes up formation columnar electrode 11.
Then; Utilize foundation metal layer 37 metallide that enforcement has copper as the electroplating current path with opening 20 at second inorganic insulating membrane 19 and outer embrane 29; Form down the column electrode part on 12 the foundation metal layer 37 and divide 11a, and in the opening 28 of electroplating etchant resist 27, divide on the 11a and divide 11b forming the column electrode part on the upper surface of foundation metal layer 37 subsequently in column electrode part down.
In this case, owing to electroplate the opening 30 that the opening 28 of etchant resist 27 is slightly larger than outer embrane 29, so plated metal isotropically is deposited in the opening 28 of electroplating etchant resist 27.Like this, the last column electrode part that is formed in the opening 28 of electroplating etchant resist 27 divides 11b to have the protrusion shape.Thereby, form the columnar electrode 11 that divides 11a and last column electrode part to divide 11b to form by following column electrode part.
Then, separate and electroplate etchant resist 27, utilize columnar electrode 11 as the part that is not in the zone of columnar electrode 11 belows on mask etching and the removal foundation metal layer 37 subsequently, foundation metal layer 37 only is retained in columnar electrode 11 belows thus, and is shown in figure 23.Subsequently, through silk screen print method the last column electrode part that the solder flux (not shown) is applied to columnar electrode 11 is divided on the upper surface of 11b, and the soldered ball (not shown) is installed on the upper surface of solder flux subsequently.
Then; After reflux course; Be installed in the soldered ball fusing on the upper surface of solder flux; Obtain corners and curing through surface tension subsequently, the last column electrode part that makes soldered ball 15 be formed on columnar electrode 11 is divided on the surface of the foundation metal layer 37 on the upper surface that is formed at outer embrane 29 comprising of 11b, and is shown in figure 24.Afterwards, shown in figure 25, along line 22 cutting semiconductor chips 21, first inorganic insulating membrane 16, organic protective film 40, second inorganic insulating membrane 19 and outer embrane 29, obtain a plurality of semiconductor devices shown in figure 14 thus.
At this; In above-mentioned manufacturing method for semiconductor device; Second inorganic insulating membrane 19 that has opening 20 in the corresponding part of connection pads part with wiring 8 is formed on the organic protective film 40 that comprises wiring 8; And the outer embrane 29 that has opening 30 in the corresponding part of connection pads part with wiring 8 is formed on second inorganic insulating membrane 19, and the connection pads through the wiring 8 of metallide in the opening 20,12 of second inorganic insulating membrane 19 and outer embrane 29 partly goes up formation columnar electrode 11 afterwards; Shown in figure 22, making no longer needs specific process of lapping.
In addition; In the semiconductor device that obtains through above-mentioned manufacturing approach; Surperficial shown in figure 14 except connection pads part of wiring 8 is coated with second inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride by comprising 19, feasible can suppress to connect up between 8 and connect up 8 and columnar electrode 11 between electromigratory generation.
(the 4th execution mode)
Figure 26 is the cutaway view as the semiconductor device of four embodiment of the invention.The difference of this semiconductor device and semiconductor device shown in Figure 14 is that second inorganic insulating membrane 19 with opening 20 only is arranged on the surface that comprises foundation metal layer 9 of wiring 8, and the 3rd inorganic insulating membrane 38 is arranged on the inner wall surface of opening 20 of second inorganic insulating membrane 19, on the inner wall surface of the opening 30 of outer embrane 29 and the getting around on mouthfuls 30 the upper surface of outer embrane 29.
Below, with an instance describing the method for making this semiconductor device.In this case, after step shown in Figure 180, by for example phenolic resins process positive etchant resist 31 patterned/be formed on the upper surface of second inorganic insulating membrane 19, shown in figure 27.In this case, first opening 32 be formed on etchant resist 31 with wiring 8 the corresponding part of connection pads part in.And second opening 33 is formed on and covers on the corresponding etchant resist 31 of part between second inorganic insulating membrane 19 of wiring 8 end face.
Then; Second inorganic insulating membrane 19 utilizes etchant resist 31 to bear dry ecthing in first opening, 32 corresponding parts second inorganic insulating membrane 19 and etchant resist 31 (just connect up 8 connection pads part), to form opening 20 and to remove second opening, 33 corresponding parts second inorganic insulating membrane 19 and etchant resist 31 as mask, and is shown in figure 28.
In this case, dry ecthing can be for example general reactive ion etching (RIE) or can be the high-density plasma dry ecthing that hereinafter is described.And in this state, second inorganic insulating membrane 19 with opening 20 only is formed on the surface that comprises foundation metal layer 9 of wiring 8.Afterwards, separate etchant resist 31.
Then, shown in figure 29, the outer embrane processed by organic material (for example polyimide resin or epoxy resin) is 29 patterned/be formed on the upper surface that comprises second inorganic insulating membrane 19 of organic protective film 40.In this case, utilize the photomask (not shown) to pass through the photoetching process corresponding appropriate section formation of the connection pads part with wiring 8 opening 30 of mantle 29 outside.
Then; Shown in figure 30; Through plasma CVD method on the entire upper surface of mantle 29 on the upper surface of the connection pads part that the opening 20,12 that pass through second inorganic insulating membrane 19 and outer embrane 29 of wiring 8 exposes and outside formation by comprising the 3rd inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride 38.Equally in this case, the technological temperature that forms the 3rd inorganic insulating membrane 38 is preferably 250 ℃ or lower, makes the organic protective film of being processed by organic material (for example polyimide resin) 40 that has formed can not receive fire damage with outer embrane 29.
Then, the positive etchant resist processed by for example phenolic resins is 34 patterned/is formed on the upper surface of the 3rd inorganic insulating membrane 38.In this case, positive etchant resist 34 only be formed on the upper surface on the inner wall surface of the opening that is formed at outer embrane 29 30 of the 3rd inorganic insulating membrane 38 and the upper surface that gets around mouthful of the 3rd inorganic insulating membrane 38 on.
Then, the 3rd inorganic insulating membrane 38 utilizes positive etchant resist 34 to bear dry ecthing as mask, makes the 3rd inorganic insulating membrane 38 only be retained in positive etchant resist 34 belows, and is shown in figure 31.Just, the 3rd inorganic insulating membrane 38 be formed on the inner wall surface of opening 20 of second inorganic insulating membrane 19, on the inner wall surface of pallial opening 30 and the getting around on mouthfuls 30 the upper surface of outer embrane 29.In this state, the connection pads of wiring 8 part is exposed through the opening 17 that is formed on the 3rd inorganic insulating membrane 38.Afterwards, separate etchant resist 34.
At this; Dry etching in this case preferably should be the high-density plasma dry etching; It makes and changes into isoionic gas and have longer mean free path; So that the etching of the 3rd inorganic insulating membrane 38 on the inner wall surface of the opening 20,12 that especially is formed on second inorganic insulating membrane 19 and outer embrane 29 is reduced to minimum.
For example, helicon (whistler wave) Etaching device can produce high-density plasma under high vacuum, and is preferred.In this case, if adopt CF
4As process gas, to the OH that wherein adds total amount 5%-10%
2, then can improve etching efficiency.And, can adopt the inductively coupled plasma Etaching device that can produce high-density plasma.
Then; Shown in figure 32, through copper for example on the upper surface of the connection pads part that the opening that passes through the 3rd inorganic insulating membrane 38 17 of wiring 8 exposes, on the 3rd inorganic insulating membrane 38 and the sputter on the entire upper surface of outer embrane 29 form foundation metal layer 37.Afterwards, electroplate etchant resist 35 patterned/be formed on the upper surface of foundation metal layer 37.In this case, be formed on than the opening 17 bigger openings 36 of the 3rd inorganic insulating membrane 38 and electroplate dividing in the regional corresponding part of 11b of etchant resist 35 with its last column electrode part that goes up formation columnar electrode 11.
Then, utilize foundation metal layer 37 implements to have copper as the electroplating current path metallide with on the foundation metal layer 37 of the opening 17 of the 3rd inorganic insulating membrane 38, form down the column electrode part divide 11a and subsequently the following column electrode part in the opening 36 of plating etchant resist 35 divide on the 11a and divide 11b forming the column electrode part on the upper surface of foundation metal layer 37.
Equally in this case, owing to electroplate the opening 17 that the opening 36 of etchant resist 35 is slightly larger than the 3rd inorganic insulating membrane 38, so plated metal isotropically is deposited in the opening 36 of electroplating etchant resist 35.Like this, the last column electrolysis section 11b that is formed in the opening 36 of electroplating etchant resist 35 has the protrusion shape.Thereby, form the columnar electrode 11 that divides 11a and last column electrode part to divide 11b to form by following column electrode part.
Then; Separate and electroplate etchant resist 35; And utilize columnar electrode 11 foundation metal layer in the zone that is not in columnar electrode 11 belows 37 to be carried out etching and removal subsequently as mask, foundation metal layer 37 only is retained in the below of columnar electrode 11 thus, and is shown in figure 33.Subsequently, the same with manufacturing approach in above-mentioned the 3rd execution mode, through solder flux apply step, soldered ball forms step and scribe step obtains a plurality of semiconductor devices shown in Figure 26.
In the semiconductor device of thus obtained the 4th execution mode; The surface coverage except connection pads part of wiring 8 has second inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride by comprising 19, and the following column electrode part of columnar electrode 11 divides the outer surface of 11a to be coated with the 3rd inorganic insulating membrane of processing as the inorganic material of the silica of main component or silicon nitride by comprising 38.Thereby, can be suppressed at the wiring 8 between, between the columnar electrode 11 and connect up 8 and columnar electrode 11 between produce electromigration.
(the 5th execution mode)
Figure 34 is the cutaway view as the semiconductor device of fifth embodiment of the invention.The difference of this semiconductor device and semiconductor device shown in Figure 26 is that second inorganic insulating membrane 19 with opening 20 not only is arranged in the wiring 8, and it is arranged on the entire upper surface of organic protective film 40.In an instance of the method for making this semiconductor device, can after step shown in Figure 21, implement the step shown in Figure 30 that is not shown specifically.
Claims (3)
1. manufacturing method for semiconductor device comprises:
Above Semiconductor substrate, form diaphragm;
Formation is arranged on a plurality of wirings on the diaphragm;
On the connection pads part of wiring, form columnar electrode;
On the surface of wiring, on the surface at columnar electrode and on diaphragm, form electromigration prevention film;
On electromigration prevention film, form the diaphragm seal that comprises silicon dioxide; And
Grinding is included in upper surface one side of diaphragm seal of the electromigration prevention film that forms on the upper surface of columnar electrode with its removal; Upper surface with the electromigration prevention film on upper surface that exposes columnar electrode and the outer surface that is formed on columnar electrode makes the upper surface of columnar electrode and the upper surface of diaphragm seal be in a plane basically.
2. manufacturing method for semiconductor device as claimed in claim 1 is characterized in that, processes wiring by the metal that comprises copper, and is made of copper columnar electrode.
3. manufacturing method for semiconductor device as claimed in claim 1 is characterized in that, electromigration prevention film is made up of polyimide resin or PBO resin, and diaphragm seal is made up of epoxy resin.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP014533/2007 | 2007-01-25 | ||
| JP2007014533A JP4765947B2 (en) | 2007-01-25 | 2007-01-25 | Semiconductor device and manufacturing method thereof |
| JP086418/2007 | 2007-03-29 | ||
| JP2007086418A JP2008244383A (en) | 2007-03-29 | 2007-03-29 | Semiconductor device and its manufacturing method |
| PCT/JP2008/051594 WO2008091023A1 (en) | 2007-01-25 | 2008-01-24 | Semiconductor device comprising electromigration prevention film and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101589467A CN101589467A (en) | 2009-11-25 |
| CN101589467B true CN101589467B (en) | 2012-05-30 |
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| CN200880002910.6A Expired - Fee Related CN101589467B (en) | 2007-01-25 | 2008-01-24 | Semiconductor device comprising electromigration prevention film and manufacturing method thereof |
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| CN (1) | CN101589467B (en) |
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| JP5277788B2 (en) * | 2008-08-14 | 2013-08-28 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| JP5296590B2 (en) * | 2009-03-30 | 2013-09-25 | 新光電気工業株式会社 | Manufacturing method of semiconductor package |
| US9024431B2 (en) | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| CN102201389A (en) * | 2010-03-23 | 2011-09-28 | 卡西欧计算机株式会社 | Semiconductor device provided with tin diffusion inhibiting layer and manufacturing method of the same |
| CN102867758B (en) * | 2011-07-08 | 2015-12-02 | 颀邦科技股份有限公司 | Bumping manufacturing process and structure thereof |
| US9190348B2 (en) | 2012-05-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| JP5633095B2 (en) * | 2013-02-08 | 2014-12-03 | 新光電気工業株式会社 | Semiconductor package manufacturing method and semiconductor package |
| JP6365106B2 (en) * | 2014-08-18 | 2018-08-01 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US10651201B2 (en) * | 2017-04-05 | 2020-05-12 | Samsung Electronics Co., Ltd. | Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5391397A (en) * | 1994-04-05 | 1995-02-21 | Motorola, Inc. | Method of adhesion to a polyimide surface by formation of covalent bonds |
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| JP3905032B2 (en) * | 2002-12-20 | 2007-04-18 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| JP4307296B2 (en) * | 2004-03-12 | 2009-08-05 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP2006147810A (en) * | 2004-11-19 | 2006-06-08 | Casio Comput Co Ltd | Semiconductor device and method of manufacturing the same |
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| US5391397A (en) * | 1994-04-05 | 1995-02-21 | Motorola, Inc. | Method of adhesion to a polyimide surface by formation of covalent bonds |
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| JP4765947B2 (en) | 2011-09-07 |
| JP2008182059A (en) | 2008-08-07 |
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