CN101540303B - 抗磨损和晶须的涂覆系统和方法 - Google Patents

抗磨损和晶须的涂覆系统和方法 Download PDF

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CN101540303B
CN101540303B CN2009101181164A CN200910118116A CN101540303B CN 101540303 B CN101540303 B CN 101540303B CN 2009101181164 A CN2009101181164 A CN 2009101181164A CN 200910118116 A CN200910118116 A CN 200910118116A CN 101540303 B CN101540303 B CN 101540303B
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tin
layer
silver
copper
substrate
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CN101540303A (zh
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斯祖凯恩·F·陈
尼科尔·A·拉修克
约翰·E·吉芬
彼得·W·罗宾逊
埃彼德·A·卡恩
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Global Pioneer Metals Corp
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GBC Metals LLC
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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Abstract

一种有涂层的导电衬底(26)，包括多根密集地间隔开的导线(10)，并且锡晶须可形成短路。衬底(26)包括引线框、接线脚和电路迹线。导电衬底(26)具有以距离(14)隔开的多根导线(16)，距离(14)能够被锡晶须搭接；覆盖至少一个表面的银或银基合金层(28)；直接覆盖银层的精细颗粒锡或锡基合金层(30)。另一种有涂层的导电衬底(26)比如在接插件中具有特殊性能，其中摩擦磨损产生的碎片氧化而使衬底的电阻率增大。在导电衬底(26)上沉积隔离层(32)。随后沉积的层包括沉积在隔离层(32)上用于和锡形成金属间化合物的牺牲层(34)、低电阻率氧化物金属层(40)和锡或锡基合金的最外层(36)。隔离层(32)优选为镍或镍基合金，低电阻率氧化物金属层(40)优选为银或银基合金。

Description

抗磨损和晶须的涂覆系统和方法
本申请是于2004年10月13日提交的申请号为200480033610.6的标题为“抗磨损和晶须的涂覆系统和方法”的专利申请的分案申请。 
技术领域
本发明涉及用于涂覆导电衬底的系统和方法，特别是涉及用于涂覆导电衬底的多层系统和方法。 
背景技术
在本专利申请中，用于限定某种合金的“基”是指该合金至少含有重量百分比为50％的所限定元素，例如，“铜基合金”是指在这种合金中铜的重量百分比大于50％。在电气与电子工业中，铜和铜基合金(在下文中统称为铜)被广泛用于制作接线器、电线、印刷电路板、球栅阵列(ball gridarrays)、引线框(leadframe)、多芯片组件等等。虽然铜具有良好的导电性，但是当铜被暴露在高温、潮湿或化学环境中时，极易被氧化和生锈。铜的氧化和生锈通常会使铜的接触电阻升高，因此会降低电学器件的性能。另外，铜的氧化和生锈也会降低焊接可湿性，使焊接过程出现问题。 
避免或减少铜的氧化和生锈的方法之一是在铜衬底上镀上锡或锡基合金(以下统称为锡)涂层。这种锡涂层起到防止或减少铜氧化的作用，因此可以保持铜衬底的电学性能。然而，用锡作为导电衬底的涂层仍然存在很多问题。在室温下(通常为25℃)，锡涂层和铜衬底会互相扩散而生成铜-锡金属间化合物(IMC)。这些铜-锡金属间化合物使锡涂层厚度减小，导致铜衬底接触电阻升高，焊接性降低，并且锡涂层与铜衬底之间的这种扩散的速度在高温下会更快。 
示例性的热变化过程包括，在引线接合或封装在聚合物中的过程需要在250℃持续几秒钟，回流处理需要在300℃持续几秒钟，为了降低摩擦而控制锡涂层厚度减小，需要在150℃下持续8到168小时。 
一种用于降低铜-锡金属间化合物形成的效应、并保持低接触电阻的方法是增加锡涂层的厚度。然而，这种方法不仅会增加部件的成本，也会对功能造成影响。当在电连接器使用锡涂层时，厚的软锡涂层会使摩擦增大，进而增大连接器插入时所需要的力，使电连接器的插拔变得困难。对于电子器件而言，既然其发展趋势是超薄化和超小化，那么厚的锡或锡合金涂层也是不理想的。另外，在电子器件的导线(lead)上使用锡涂层的情况下，厚的锡涂层会使导线的共面和粗细的界定出现问题。 
另一种降低铜-锡金属间化合物形成的效应的方法是在铜衬底和锡涂层之间增加过渡隔离层，以阻止铜-锡金属间化合物的形成。例如，美国专利No.4,441,118报道了使用镍的含量在15％至30％之间的铜-镍合金衬底，可以实现铜-锡金属间化合物低速率形成。 
在另一个实例中，P.J.Kay和C.A.Mackay讨论了各种金属作为过渡隔离层的用途，该文章发表在1979年的“Transactions of the Institute of MetalFinishing”的第51期，169页。文章的一个实施例描述了一种厚度为1微米的银隔离层。然而，这个例子被证明是不理想的，因为银过渡隔离层不能够真正降低铜和锡之间的扩散速度。Schatzberg的美国专利No.4,756,467公开了一种可焊接连接器，该连接器包括铜衬底、薄银层、银-锡合金层以及最外面的锡层。其中，银-锡合金层通过扩散退火形成。Furukawa电气有限公司的日本专利No.2670348(出版号为02-301573)公开了一种铜衬底，该铜衬底上涂覆镍或钴的隔离层，隔离层上面是银层，银层上是锡或锡合金的熔化-固化(melt-solidified)层。 
本申请人所拥有的、于2004年10月31号递交的序列号为10/930,316的美国专利申请，是序列号为09/657,794的美国专利申请的延续，该申请公开了一种设置在铜衬底和锡涂层之间的薄的抗锈蚀层。所公开的可以作为抗锈蚀层的金属有锌、铬、铟、磷、锰、硼、铊、钙、银、金、铂、钯以及这 些金属的组合物和合金。 
本申请人所拥有的Fister等的美国专利No.5,780,172和5,916,695还公开了其它隔离层。 
利用锡作为导电衬底的涂层会引起的另外一个问题是锡易于产生摩擦腐蚀。摩擦腐蚀是接触面的氧化，这种氧化是由两个匹配接触面之间的相对移动(摩擦)引起的。这种摩擦引起的氧化可能会导致接触电阻的不可接受的增大。某些金属，比如银，已知具有极好的抗摩擦腐蚀性。然而，由于空气中存在二氧化硫，银在空气中容易产生锈蚀，在银表面生成银硫化物。这种锈蚀不仅在审美方面是不可接受的，也可能会降低银的电接触性能。 
利用锡或者其它金属，比如锌、铟、锑或钙，作为导电衬底的涂层还存在另一个问题是，锡或者上述的其它金属易于产生晶须。随着锡老化，会形成晶须，并且在锡或锡/金属间化合物(IMC)的界面上开始产生应力。晶须形成的另外一个原因是由于电镀过程中产生的内应力。为了释放这些应力，锡单晶从表面成核，形成晶须。每一个晶须持续生长直到内应力被全部释放掉。晶须可能会引起许多不同的问题，包括缩短相邻电接触表面的距离。减少晶须生长的通用方式是在锡涂层中增加少量的铅(Pb)，形成合金。然而，考虑到健康和环境的原因，许多工业生产中被要求减少或者禁止使用铅。 
这样，发明一种在摩擦和热暴露后仍然能够保持低的接触电阻和良好的焊接性的涂覆系统是必要的，同时这种涂覆系统还具备更低的摩擦系数和/或减少锡晶须生长的特性。 
发明内容
依据本发明的第一具体实施方式，本发明提供一种具有特殊性能的涂覆的导电衬底，这种衬底具有多个密集地间隔开的部件和易于形成短路的锡晶须。这种衬底包括引线框、接线脚、在印刷电路板和软电路上的电路迹线(circuit trace)，所述部件包括导线、线路和电路迹线。这种导电衬底具有多根以一定距离隔开的导线，这个距离能够被锡晶须搭接，导电衬底还具有 覆盖这多根导线中至少一根的至少一个表面的银或银基合金层，直接覆盖在所述银层上的精细颗粒锡或锡基合金层。 
根据本发明的第二具体实施方式，本发明提供一种一种具有特殊性能的有涂层的导电衬底，这种衬底专门用于摩擦磨损碎片氧化和电阻率增大的地方，比如在接插件中。这种导电衬底上沉积有隔离层，用于阻止衬底向多个后续沉积的层扩散。这些后续沉积的层包括牺牲层，用于和锡生成金属间化合物；沉积在所述牺牲层上、能够生成低电阻率氧化物的金属层(这里称为低电阻率氧化物金属层)；直接沉积在低电阻率氧化物金属层上的锡或锡基合金最外侧。 
在第二个具体实施方式中，隔离层优选是镍或镍基合金，低电阻率氧化物金属层优选是银或银基合金。 
当第二个具体实施方式中所述有涂层的衬底被加热时，会生成一种特殊的结构，该结构具有铜或铜合金衬底，由包括铜和锡的金属混合物形成的中介层，以及由包含相和富银相的铜锡金属间化合物的混合物形成的最外层。 
富银相被认为可以使摩擦磨损碎片氧化而引起电阻率的增大达到最小。 
在以下的附图和详细说明中给出了本发明的一个或多个具体实施方式的具体描述。本发明的其它特性、目的以及有益效果将在具体描述、附图以及权利要求中给出。 
附图说明
从下面对于本发明的详细描述以及附图中，可以对本发明有更加全面的了解。在附图中，相同的元件用相同的标号表示，其中， 
图1为根据本发明第一具体实施方式的引线框在封装和涂覆前的俯视平面图； 
图2为根据本发明第一具体实施方式的图1所示引线框在封装后和涂覆前的侧面平面图； 
图3为根据本发明第一具体实施方式的图1所示引线框在封装和涂覆后 的横截面图； 
图4为根据本发明的第二具体实施方式涂覆的导电条的横截面图； 
图5为图4所示导电条被构成为接插件后的横截面图； 
图6为图5所示接插件中用于说明摩擦碎片效应的部分的横截面放大图； 
图7为制作本发明第一实施方式的流程示意图； 
图8为制作本发明第二实施方式的流程示意图； 
图9为由不同层组合而涂覆的衬底各层间的互扩散的说明图； 
图10为本发明的涂覆的衬底在150℃下加热一周的表面的显微照片； 
图11为图10所示的涂覆的衬底的横截面显微照片。 
具体实施方式
参见图1，引线框包括多根导线10，这些导线由导电金属，比如铜或铜基合金形成。多根导线10中的每根导线都在导线内侧尾端12终止，形成中央窗口，芯片焊盘(die paddle)14占用该窗口。通常，在导线内侧尾端12和芯片焊盘14上涂覆薄的贵重金属层，比如银，以增强芯片附着和引线接合。当用银作为涂层金属时，该薄层典型的厚度为3微米到6微米，并且利用电沉积法进行沉积。然后，将一个或多个集成电路(IC)器件16，通常称为半导体芯片，比如通过低温金属焊料或者热导聚合物粘合剂，附着在芯片焊盘14上。细金属线18，或者导电金属箔窄条，将集成电路器件16的电活性面上的电路与导线内侧尾端12连接起来。然后，利用成型树脂一般沿着由虚线20表示的周边来封装芯片焊盘14、集成电路器件16、导线内侧尾端12以及导线中间部分21。 
图2是图1所示组件的侧面图，从图中可以看到导线10从成型树脂22中延伸出来。从成型树脂中延伸出来的导线的外侧部分23通常被焊接到外部电路，比如印刷电路板上的迹线上。为了获得最佳的导电性，导线通常由铜或铜合金形成，但也可以使用诸如铁-镍和铁-镍-钴之类的非铜金属。铜和 铜合金易于被氧化，在表面形成的氧化物会影响铜和铜合金的焊接性。 
为了阻止氧化物的生成，通常的办法是在铜导线上沉积一层抗锈蚀层。这种作为抗锈蚀层的易于焊接的材料为锡或锡基合金。但是，当铜和锡被暴露在室温或更高的温度下时，铜和锡之间会存在扩散。当铜-锡金属间化合物在层表面形成时，这种结构的抗锈蚀特性和焊接性都会降低。为了降低铜锡之间的扩散速度以及减少金属间化合物的生成，常用的方法是在衬底和抗锈蚀层之间设置隔离层，比如镍。 
锡晶须化是锡的一种特性，指通过细的锡丝的生长释放内应力。回去参见图1，导线10密集地间隔开，锡晶须可以在相邻导线之间的间隙24搭接，形成电路短路。通常，当两根导线之间的距离为1毫米或更短时，锡晶须在两根导线之间形成搭接的可能性将很大。虽然已经提出很多种阻止锡晶须形成的方法，但是这些方法仍然存在局限性。众所周知，将锡和另一种金属，比如铅形成合金，可以减少晶须的生成，但是铅有毒。另一种已知的方法是将锡加热到它的熔点以上，经过已知的回流过程来减少晶须的生成。但是，控制液态锡的流动是困难的，而且在回流过程中，经常会在导线之间形成搭接。 
根据本发明的第一个具体实施方式并参见图3，锡晶须可以通过在衬底26上形成导线10来减少，衬底26上涂覆有银或银基合金层28，然后在银或银基合金层28上直接沉积锡精细颗粒层30。“直接”沉积的意思是紧接银或银基合金层28沉积，没有任何其它材料的中介层。如果衬底26由铜或铜基合金以外的金属形成，则在沉积银层28之前，可以在衬底上沉积一薄层铜，其厚度在0.025到0.51微米(即1-20微英寸)之间。银层28可以用银基合金层代替，锡层可以用锡基合金层代替。 
两种金属接触面的强度比金属自身强度小。因此，导线10被成型树脂封装的部分优选不覆盖银层和锡层，这些层仅仅涂覆在导线的从成型树脂延伸出来的部分上。银层28的厚度范围为0.025微米到3.05微米(1-120微英寸)。当厚度小于0.025微米(1微英寸)，锡晶须不足以被抑止。当厚 度超过3.05微米(即120微英寸)，将会增加成本。优选的银层厚度是在0.05微米到1.02微米之间，即2-40微英寸，最优选的银层厚度范围是0.13微米到0.51微米，即5-20微英寸。 
锡层30的厚度在0.00025微米到10.2微米之间，即0.01-400微英寸。当厚度小于0.00025微米，即0.01微英寸时，抗腐蚀性和可焊接性都下降。当厚度超过10.2微米，即400微英寸时，相邻导线间容易形成搭接。优选的锡层厚度是从0.51微米到3.8微米，即20-150微英寸。最优选的锡层厚度范围为0.51微米到2.03微米，即20-80微英寸。 
通过电沉积的方式获得的锡是精细颗粒，与之相对的，通过下面所述的回流过程获得的锡是粗糙颗粒。典型的颗粒平均尺寸是在0.1微米到100微米之间，优选尺寸是在0.5微米到5微米之间，而与之相对的，回流后的标准颗粒的尺寸是毫米量级的。精细颗粒通常具有更好的延展性使导线可以大角度弯曲而不会造成涂层的破裂。虽然精细颗粒锡被认为更易于产生锡晶须，但是本具体实施方式中的银底层允许使用精细颗粒的锡。 
虽然本发明第一实施方式是以具有多根密集地间隔开的导线的引线框为例来描述的，但是本发明的这种无锡晶须涂层也可以应用于其他结构中，比如接线脚，印刷电路板和软电路，在这些结构中包含密集地间隔开的其他器件，比如导线和电路迹线。 
本发明的第二实施方式被应用到接插件中。与引线框不同，大部分接插件是不受锡晶须影响的，因为相邻的连接器通常具有足够远的距离以避免锡晶须造成的短路现象。另外，因为连接器不像引线框中的导线那样紧密排布，回流过程就可以减少锡涂层中的内应力。而且，铜锡之间的扩散经常被用于减小游离锡(free tin)的厚度，因此就可以减小摩擦力和探头插入插座所需的力。 
接插件通常会由于摩擦碎片使电阻率增大。摩擦磨损现象发生在两个表面小幅度相对振动过程中。摩擦磨损会在相互接触的表面上产生可去除的小颗粒。然后这些小颗粒被氧化，氧化物碎片聚集在接插件的交界面。由于在 室温下锡的电阻率大约为0.12微欧姆米(μΩ·m)，而锡氧化物的室温电阻率约为1微欧姆米，因此摩擦磨损会使接插件的电学性能变差。 
根据本发明第二具体实施方式形成的接插件可以减少摩擦磨损。参见图4，衬底26通常是铜或铜基合金，但也可以使用其他的导电金属。在使用其他导电金属中的任何一种作为衬底时，如上所述，该衬底上沉积薄的铜层。在铜合金的衬底上也可以沉积薄的铜层，这样可以提供纯的铜表面，以方便后面各个层的沉积和粘附。 
在铜或铜基合金衬底或薄铜层上沉积的是隔离层32。该隔离层可以是任何一种阻止铜和其他构成衬底成分之间扩散的金属，优选是过渡金属，比如镍、钴、铁、锰、铬、钼或者它们的合金。该隔离层的厚度在0.051微米到2.03微米之间，即2-80微英寸。如果隔离层的厚度小于0.051微米(2微英寸)，它不能有效阻止扩散。如果隔离层的厚度超过2.03微米(80微英寸)，接插件的电学和机械性能将会受到不良影响。优选隔离层的厚度为0.1微米到1.02微米，即4-40微英寸。更优选的是，隔离层的厚度范围为0.1微米到0.51微米，即4-20微英寸。 
在隔离层32上沉积的是牺牲层34。牺牲层34是一种金属，这种金属与银和锡结合构成合金或金属间化合物。为了减小摩擦，最外层36的游离锡厚度被减小。这种厚度减小，可以通过加热这种组件来实现，通过加热组件使牺牲层与最外层的内侧部分相结合形成硬度较高的金属间化合物。牺牲层的优选材料是厚度在0.051微米到1.52微米(2-60微英寸)之间的铜或铜基合金。牺牲层厚度的大小可选为，当牺牲层被消耗时，在最外层36的外表面38上至少保留0.051微米量级的游离锡。在最外层的厚度开始在1.02微米到2.03微米之间时，铜牺牲层的最优选厚度范围为0.13微米到0.51微米，即5-20微英寸。 
在牺牲层34和最外层36之间沉积的是低电阻率氧化物金属层40。这种低电阻率氧化物金属是在接插件预期操作温度下形成氧化物的金属，这种金属氧化物的电阻率比锡氧化物的电阻率低。银或银基合金是低电阻率氧化 物金属层40的较佳选择。虽然锡氧化物的电阻率在室温下约为1微欧姆米，但是银氧化物的电阻率在室温下约为0.14微欧姆米。通过将银氧化物加入到摩擦碎片中，摩擦磨损对接插件电阻率的影响会显著减小。低电阻率氧化物金属层的厚度在0.025微米到3.05微米之间，即1-120微英寸。如果厚度小于1微英寸时，银氧化物不足以影响接插件的电阻率。如果厚度超过3.05微米(120微英寸)，则成本将会增加。优选这种低电阻率氧化物金属层的厚度在0.05微米到1.02微米之间，即2-40微英寸，更优选的厚度在0.13微米到0.51微米，即5-20微英寸。 
图4所示的导电条被形成在接插件中，图5给出了这种接插件的横截面示意图。这种接插件包括插座42和探头(probe)44。插座通常被弯曲成能够与探头形成有效点接触的形状，而探头的形状要保证在插座内产生一个内应力从而有效提供一个正压力使探头和插座在点46保持电接触。 
图6是图5中虚线圈所定义的点接触的放大示意图。由于振动，点46在第一接触点48和第二接触点50之间振荡。这种磨损产生金属氧化物磨损碎片52。磨损碎片的一部分54覆盖振荡轨迹，并影响点46和探头44之间的电流流动。 
低电阻率氧化物金属层的金属应该是其氧化物的电阻率比锡氧化物的电阻率(1微欧姆米)低，或者是比银更难形成氧化物的贵重金属，如金、铂、钯。表1列出了许多基底金属氧化物，并且给出了他们作为低电阻金属氧化物的适用性。在表1中，“O”代表适用，“X”代表不适用。铟、铁、铌、铼、钌、钒、金、铂、钯和锌以及这些金属中的四种的混合物都可以作为银的替代物。 
表1 
Figure G2009101181164D00101
图7是制造图3所示的涂覆衬底的方法的流程示意图，该方法用于只涉及锡晶须而不涉及锡回流以释放内应力的应用。这些应用包括引线框、密集地间隔开的接线脚(如接脚栅格阵列电子封装器件上所含有的接线脚)，和印刷电路板或软电路上密集地间隔开的电路迹线。如图7所示，前三个步骤是引线框和一些具体实施方式中的接线脚设备中特有的。剩余三个步骤是所有上述产品种类通用的。 
引线框可以在衬底上压制而成，或者也可以在衬底上通过化学刻蚀制备，典型的衬底是铜或铜基合金。引线框包括中央设置的芯片焊盘和至少从 芯片焊盘一个侧面延伸出来的多根导线，这些导线通常是从芯片焊盘四个侧面延伸出来。引线框制作完成后需对其进行去污清洁处理，如使用商用去污剂，碱性电净剂，如Hubbard-Hall E-9354电净剂(这种电净剂可以从美国康奈提格州沃特伯里市的Hubbard-Hall购买)。碱性混合物与阳极/阴极电净法同时使用可以产生氧气或氢气气泡，以去除衬底上残留的大部分杂质。电净法通常是在20摄氏度到55摄氏度下通电，时间约为1分钟，电流密度范围在93-465安培每平方分米，即10-50安培每平方英寸。 
然后，在芯片焊盘和导线内侧部分上涂覆56可以增强焊接性和引线接合的金属，比如厚度在3微米到6微米之间的银。优选是只在导线的最里侧用于引线接合和卷带式自动接合技术(TAB)的部分涂覆银。这是因为在紧接着的封装步骤58中，要求成型树脂直接与铜衬底接触，为粘合破坏和湿气排放提供单一界面。次优选的方式是让成型树脂与银层接触，银层与铜衬底接触，形成两个界面。涂覆银的过程56可以采用任何一种适用的方法，比如电沉积、无电沉积、浸涂、化学汽相沉积或等离子沉积。 
然后集成电路器件通过传统的芯片连接方法60粘合在芯片焊盘上，传统的焊接法包括利用低温焊料焊接，例如金/锡共晶，或者粘合剂连接，如掺金属环氧树脂。引线接合是使用小直径导线或金属薄片窄条将集成电路与引线框的导线内侧部分电连接起来。在芯片附着和引线接合之后，芯片焊盘、集成电路器件、引线接头和引线框导线的内侧部分被封装在热固的成型树脂中，如环氧树脂。然后导线的外侧部分被弯曲成可以与印刷电路板或其他外部电路连接的形状。 
然后在导线的外侧部分涂覆一层银或银合金62，可以采用如电镀、无电镀、浸镀、物理汽相沉积、化学汽相沉积、等离子沉积或金属溅射等方法。银镀层的厚度在0.025微米到3.05微米之间，即1-120微英寸，最优选的厚度范围为0.051微米到0.51微米，即2-20微英寸。 
优选的镀银方法是用31-56克每升氰化银、50-78克每升氰化钾、15-90克每升碳酸钾的水溶液和抛光剂进行电镀。电镀的温度是在20摄氏度 到28摄氏度、电流密度是在46.5安培每平方分米到139安培每平方分米，即5-15安培每平方英寸。另一种可选的镀银方法是使用无氰化物浸镀，如康奈提格州沃特伯里市的MacDermid有限公司的MacDermid SterlingTM的银。 
然后在镀银的外侧导线上再涂覆一层锡64，使得锡的厚度为0.00015微米到10.2微米，即0.006-400微英寸，优选的厚度为0.5微米到2.03微米，即20-80微英寸。优选的镀锡方法是使用包含甲烷磺酸基锡电镀液的溶液，如Rohm and Haas SolderonTM ST200(美国宾夕法尼亚州费城的Rohm andHaas Company，Philadelphia，PA，USA)AMAT的雾锡、MacDermid SterlingTMAMAT的光亮锡。上述电解液的典型使用条件是温度在25摄氏度到35摄氏度之间，电流密度为46.5安培每平方分米到465安培每平方分米，即5-50安培每平方英寸。 
然后将镀锡的外部导线与印刷电路板或其他的外部电路焊接66在一起，比如通过使用锡/铅合金焊料或合适的无铅焊料进行焊接。所选择的焊料和焊接过程应保证焊料融合到锡层上而不使锡层熔化。避免锡层的熔化是为了防止液态焊料使导线搭接。 
图8是用于制造图4所示的涂覆的衬底的方法的流程示意图，在应用这种方法时考虑了氧化的摩擦碎片降低电阻率的效应，如在电接插件中。如图7所示，当衬底材料不是铜，或是具有高合金含量的铜合金，如重量百分比超过2％时，可以在涂覆下一层前在衬底表面上沉积68一薄层铜。该薄铜层可以最小化不同金属对后续层沉积的影响，从而使许多不同的衬底材料达到更一致的产品性能。 
铜层的最小厚度为0.13微米，即5微英寸，典型厚度为0.51微米到1.02微米之间，即20-40微英寸。虽然下面所述的铜层及随后各层可以通过任一适当的方法沉积，优选的铜层沉积68方法是使用包含20到70克每升的铜离子和50到200克每升的硫酸的水溶液进行电镀。操作条件：温度范围在40到60摄氏度之间，电流密度为186到929安培每平方分米，即20- 100安培每平方英寸。 
接下来沉积阻挡层70。合适的阻挡层材料包括镍、钴、铬、钼、铁和锰以及它们的合金或者混合物，沉积的厚度范围在0.05微米到1.02微米之间，即2-40微英寸，优选的厚度范围为0.1微米到0.51微米，即4-20微英寸。优选的沉积镍层70的方法是使用标称包含300克每升氨基磺酸镍，6克每升氯化镍和30克每升硼酸的水溶液进行电镀。操作条件：温度在28到60摄氏度之间，pH值在3.5到4.2之间，电流密度范围为18.5到279安培每平方分米，即2-30安培每平方英寸。 
下面可使用铜为材料沉积牺牲层72到一定厚度，使其在可控的热偏移下与一部分锡有效连接形成铜/锡金属间化合物，如Cu3Sn、Cu6Sn5和(Cu合金)xSny，而在表面上保留基本上为纯锡(称作游离锡)层。游离锡层的厚度在0.051微米到3.05微米之间，即2-120微英寸，以提供可焊接、且抗锈蚀的层。通过减少软游离锡层的厚度，金属间化合物层可用来减小摩擦。对于接插件来说，减小摩擦可以降低所需的插拔力。 
在沉积完牺牲层72之后，再沉积形成了低电阻率氧化物，如银的金属74。牺牲层的沉积厚度在0.025微米到3.05微米，即1-120微英寸，优选的厚度在0.13微米到0.51微米，即5-20微英寸。优选的沉积银牺牲层的方法是使用包含氰化银的水溶液进行电镀，或者如前面所述使用纯氰化物溶液进行浸镀。除了银、铟、铁、铌、铼、钌、钒、金、铂、钯和锌之外，在表1中列出的这些金属的混合物也可以作为低电阻率氧化物金属层的材料。 
沉积完牺牲层74之后，再沉积最外层金属76，这种金属的熔点应低于衬底、阻挡层、牺牲层和低电阻率氧化物金属层中任何一层的熔点。优选将锡或锡基合金用作最外层。在大部分应用中，铅具有毒性而避免使用，但是含铅的锡基合金在某些应用中是适合使用的。沉积最外层76可以使用前面描述的任何一种方法，或者使用锡沉积的特殊方法，如HALT方法(即热空气整平锡镀法)和机械擦除法。最外层可以根据要求进行光亮精整或糙面(matte)精整。糙面精整可以在锡浴中电镀锡，对于准备此精整类型而言，这在本领域中是已知的。合适的电解液包括前面提到的SolderonTM ST200和StanTekTM AMAT。
然后进行锡回流78，比如通过将锡加热到其熔点232℃以上使锡回流。优选的热处理方式是在300℃下，在空气中或保护气氛，如氮气中加热1～10秒钟。然后将熔化的锡淬火，形成有光泽的锡表面。 
在进行回流处理前或后，将涂覆的衬底制作成80需要的部件，比如接插件的一部分。涂覆的衬底也可以在锡的熔点以下，在空气或氮气中加热约1到168个小时，加热的温度可以从150℃到200℃，目的是增加金属间化合物的含量，同时将游离锡的厚度减小到需要的厚度，典型的厚度在0.051微米到0.51微米，即2微英寸到20微英寸。 
图9A到图9D说明了本发明用于改进涂层的机理。图9A所示的是利用现有技术制作的涂覆锡的衬底26。衬底26被涂覆上铜的牺牲层34，最外面是锡层36。在暴露在比如150摄氏度的高温下一个星期之后，牺牲层34和最外层36之间发生相互扩散和结合，在衬底26附近形成Cu3Sn金属间化合物层82，该金属间化合物层向上扩散到最外层的表面84。经过高温辐照之后，最外层是Cu3Sn金属间化合物和Cu6Sn5金属间化合物的混合物86。这两种铜的金属间化合物易于氧化，导致变色和电阻率的升高。 
图9B说明了根据本发明，当衬底26被涂覆上牺牲层34、银层28和最外侧的锡涂层36并在150摄氏度下加热一星期后，衬底26被涂覆上中介层88，该中介层是铜和锡的混合物，而最外层是包含银的Cu3Sn金属间化合物90和富银相92的混合物。富银意味着包含超过50％原子百分比的银。Cu3SnAgx金属间化合物提供了坚硬的表面，以减少插拔力和减小摩擦磨损。富银相提供了耐蚀性，并且降低了由摩擦磨损碎片的腐蚀引起的电阻率的增加。 
图9C说明了根据本发明，当衬底26被涂覆上阻挡层32、牺牲层34、银层28和最外侧的锡涂层36，并在150摄氏度下加热一星期后，衬底26被涂覆中介层96，该中介层是镍、铜和锡的混合物。与层96相邻的层是第二层98，该层是镍、铜、银和锡的混合物。最外层是由第一组分为Cu6Sn5金属间化合物、多余的锡、少许银和第二组分为富银相92组成的混合物。 
图10是图9C中在150℃下加热一周后的涂覆衬底的最外层表面84的放大2000倍的显微镜照片。该表面是铜-银-锡相98和富银相92的混合物，显微镜照片中的暗区为铜-银-锡相98，亮区为富银相92。图11是图9C和图10所示的涂覆结构的放大20000倍的显微镜照片。 
图9D说明了当衬底26被涂覆隔离层32、银层28和最外面的锡层36，并在150℃下加热一星期后，衬底26被涂覆第一中介层100，该第一中介层是镍、铜、锡以及少量银的混合物。在第一中介层100上涂覆的是第二层102，第二层102是镍、铜、锡和银的混合物。第二层102延伸到最外层的表面，最外层主要是富银相92。 
下面给出的实施例将清楚地说明本发明提供的涂覆系统的优点。以下实施例可以用来说明本发明，但并不限制本发明的范围。 
实施例 
实施例1-锡晶须化 
从铜合金C194条上切下51毫米×12.7毫米×0.25毫米，即2英寸×0.5英寸×0.010英寸，大小的样品。铜合金C194的组分按重量百分比为2.1％-2.6％的铁，0.05％-0.20％的锌，0.015％-0.15％的磷，剩余的都是铜。在50摄氏度下，将样品放入商用碱性清洁液中通电一分钟进行清洁，所使用的阴极电流密度为139安培每平方分米，即15安培每平方英寸。 
参照表2，通过电镀沉积镍层。镍电镀液是包含大约60到75克每升的镍，如氨基磺酸镍，大约6到8克每升的NiCl2和pH值在3.5和4.2之间的大约38到53克每升的53摄氏度硼酸的水溶液。镍电镀条件是用电流密度279安培每平方分米，即30安培每平方英寸，的电流通电约60秒。 
当通过电镀沉积铜时，使用的水溶液包含大约20到70克每升的铜，大约50到200克每升40到60摄氏度的H2SO4。电镀条件是用电流密度372 安培每平方分米，即40安培每平方英寸，的电流通电约40秒。 
当通过电镀沉积银层时，使用的水溶液包含31到56克每升的氰化银，50到78克每升的氰化钾，15到90克每升碳酸钾和光亮剂。操作条件是温度在20到28摄氏度之间，电流密度在46到139安培每平方分米，即5到15安培每平方英寸。 
通过电镀沉积锡层时，糙面锡沉积物是使用MacDermid StanTekTMAMAT溶液产生的，光亮锡沉积物是使用MacDermid StanTekTMStellite(钨铬钴合金)100溶液产生的。电镀条件是在25到40摄氏度下，用电流密度为279安培每平方分米，即30安培每平方英寸，的电流通电约50到400秒。 
在半径为76毫米，即3英寸，的圆形沟槽中弯曲和约束的样品上进行加速锡晶须测试。通过这种方式，可以在锡涂层上产生恒定的弯曲应力，促使锡晶须形成。可以定期在500X的光学显微镜下观察示例性的和可比较的样品的压缩边(凹面)的锡晶须的形成。 
Figure G2009101181164D00171
从表2可以看出，无论最外层涂覆的是糙面锡还是光亮锡，直接与锡涂层接触的银层的内含物都可以基本上消除锡晶须的形成。对于最外层涂覆糙面锡的情况，可以比较样品2、样品3、样品4和样品5的结果。为了便于比较，样品1采用商品厚锡产品。对于最外层涂覆光亮锡的情况，可以比较样品20和样品21。 
实施例2-摩擦磨损对接触电阻的影响 
样品使用表三中列出的铜合金C194和C7025、整块熟锡和整块熟银制作而成，尺寸为152毫米×31.8毫米×0.13毫米，即6英寸×1.25英寸×0.005英寸。C7025的组分按重量百分比为2.2％到4.2％的镍，0.25％到1.2％的硅，0.05％到0.3％的镁，剩余的全是铜。 
铜合金样品上如实施例1那样涂覆了中介层和糙面锡，但银层是使用MacDermid SterlingTM的银溶液浸镀沉积的，锡是使用含有20到80克每升的锡离子的SnSO4，50到200克每升的硫酸和有机添加剂的硫酸盐溶液沉积而成。 
摩擦磨损对接触电阻的影响是通过在要测试的接触表面上沿20微米长的圆圈，以5赫兹的频率转动直径为6.4毫米，即0.25英寸，的凸块来确定的，转动的圈数可达到20000圈。在凸块上加100g的法向力，并且在凸块运动的过程中采集接触电阻的数据。记录的数值是获得确定的接触电阻所需的圈数。圈数越高表明样品的抗磨损性越好。 
表3 
  样品   衬底   中介层   表面层   表面层厚  度(微  英寸)   10毫欧接  触电阻对  应的圈数   10欧姆接  触电阻对  应的圈数
  1   C194   镍/铜   糙面锡   0.51微米  (20)   61   3269
  2   C194   镍/铜/0.13  微米(5微  英寸)银   糙面锡   0.51微米  (20)   79   4400
             
  3   C194   无   糙面锡   1.02微米  (40)   116   2269
  4   C194   0.13微米(5  微英寸)银   糙面锡   1.07微米  (42)   490   ＞5000*
             
  5   熟锡   无   无   N/A   253   6530
  6   熟锡   无   无   N/A   ＞20000   ＞20000
*表示测试在5000圈后终止 
比较样品1和采用本发明制作的样品2可以看出样品2上涂覆的0.13微米(即5微英寸)的银层能够有效地降低摩擦磨损在衬底上产生的电阻，与样品1相比，样品2达到10毫欧姆接触电阻所需的圈数约增加了30％，达到10欧姆接触电阻所需的圈数约增加了35％。 
比较样品3和采用本发明制作的样品4可以看出样品4上涂覆的0.13微米(即5微英寸)的银层能够有效地降低摩擦磨损在衬底上产生的电阻，与样品3相比，样品4达到10毫欧姆接触电阻所需的圈数约增加了322％，达到10欧姆接触电阻所需的圈数增加了超过120％。 
整块熟银(即样品6)的性能比任何一种具有涂覆的铜衬底样品都好，但是由于成本和易生锈的原因不适用于电连接器的制作。整块熟锡(即样品5)可能由于含有大量的游离锡或由旋转产生的硬度的增加，而具有较好的抗磨损性，但是由于强度很低也不适用于连接器的制作。 
实施例3-摩擦系数 
尺寸为152毫米×31.8毫米×0.13毫米(即6英寸×1.25英寸×0.005英寸)的铜合金C194样品，与前面所述的样品一样，涂覆有中介层和糙面锡。将该样品在空气中加热到350摄氏度并在水中淬火后，形成回流锡表面。 
摩擦系数用直径6.4毫米(即0.25英寸)的凸块在涂覆锡的平坦表面上以3毫米每秒的速度转10圈所产生的阻力与法向力的比值，即R/N，来测定。法向力为所加载的静重量，并且在涂覆锡的平面与凸块之间没有使用润滑剂。阻力是随着凸块在样品平坦平面上的相对滑行来测量的。所记录的值是所有10圈的平均值。R/N越低说明摩擦系数越小。表4列出了凸块转10圈测量到的平均值。 
表4 
Figure G2009101181164D00201
随着R/N减小，探头插入插座所需的插力随之减小。将样品3与样品1和2比较可以看出，涂覆5微米的银层能够使外层糙面锡的R/N值降低14％。比较样品3和样品4可以发现，进一步增加银层厚度不仅不能对摩擦系数产生明显的有益影响，而且会使成本增加。 
样品5和样品6的比较说明当用回流锡作为最外面的涂层时，能够达到 更好的效果，R/N可以降低大约45％。 
实施例4-层间相互扩散 
表5到表8列出了图9A到图9D所示结构的组分测量值，用于说明在根据本发明涂覆的衬底最外层表面上富银相的形成。使用XRF(即x射线荧光光谱仪)，测量在加热一周，温度达到150摄氏度之前的样品的厚度，单位为微英寸。加热后样品的组分和原子百分比通过EDX(即能量色散x射线荧光光谱仪)确定。 
表5(图9A) 
  图9A中的  参考标号   组分   厚度微米  (微英寸)     图9A中的  参考标号   组分   原子百分比
             
  26   C194   N.A.     26   C194   N.A.
  34   铜   0.51-1.02  (20-40)     82   铜  锡   75％  25％
  36   锡   1.02-2.03  (40-80)     86   铜  锡   56％  44％
表6(图9B) 
  图9B中的  参考标号   组分   厚度微米  (微英寸)     图9B中的  参考标号   组分   原子百分比
             
  26   C194   N.A.     26   C194   N.A.
  34   铜   0.51-1.02  (20-40)     88   铜  锡   79％  21％
  28   银   0.13-0.25  (5-10)     90   铜  锡  银   74％  23％  3％
  36   锡   1.02-2.03  (40-80)     92   银  锡  铜   56％  25％  19％
表7(图9C) 
  图9C中的  参考标号   组分   厚度微米  (微英寸)     图9C中的  参考标号   组分   原子百分比
             
  26   C194   N.A.     26   C194   N.A.
  32   镍   0.13-0.51  (5-20)     96   铜  镍   锡   42％  32％   26％
  34   铜   0.18-0.46  (7-18)     98   铜  锡  镍  银   50％  41％  7％  2％
  28   银   0.13-0.25  (5-10)     94   锡  铜  银   77％  17％  6％
  36   锡   1.02-2.03  (40-80)     92   银  锡  铜   56％  31％  13％
表8(图9D) 
  图9D中的  参考标号   组分   厚度微米  (微英寸)     图9D中的  参考标号   组分   原子百分比
             
  26   C194   N.A.     26   C194   N.A.
  32   镍   0.13-0.51  (5-20)     100   锡  镍  铜  银   41％  34％  24％  1％
  28   银   0.13-0.25  (5-10)     102   锡  银  铜  镍   35％  27％  23％  15％
  36   锡   1.02-2.03  (40-80)     92   银  锡  铜   64％  26％  10％
需要注意的是由于x射线的展宽和穿透的厚度，EDX分析结果可能有几个百分比的偏离。然而，以比较为目的，上述结果可以有效地区分所述样品。 
虽然本发明是利用所示出的具体实施方式进行显示和描述的，但应理解，可以在形式及其细节方面进行前述和各种其它修改、省略和增加，而没有脱离如权利要求所界定的本发明的精神和范围。 

Claims (4)

1.一种复合物结构，包括：
铜或铜基合金衬底(26)；
形成在所述铜或铜基合金衬底上的中介层(88、98、100)，该中介层由包括铜和锡的金属混合物形成；以及
形成在所述中介层上的最外层，该最外层是包含铜-锡金属间化合物(90、94、102)的相和富银相(92)的混合物。
2.如权利要求1所述的复合物结构，其中所述包含铜-锡金属间化合物(90、94、102)的相进一步包含银。
3.如权利要求2所述的复合物结构，其中所述富银相(92)进一步包含铜和锡。
4.如权利要求3所述的复合物结构，其中游离锡或游离锡基合金薄层覆盖在所述最外层上面。
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US7391116B2 (en) 2008-06-24
US20050106408A1 (en) 2005-05-19
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US20090017327A1 (en) 2009-01-15
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