CN101521187A - 具有顶部及底部侧电连接的晶片级集成电路封装 - Google Patents

具有顶部及底部侧电连接的晶片级集成电路封装 Download PDF

Info

Publication number
CN101521187A
CN101521187A CN200910126015A CN200910126015A CN101521187A CN 101521187 A CN101521187 A CN 101521187A CN 200910126015 A CN200910126015 A CN 200910126015A CN 200910126015 A CN200910126015 A CN 200910126015A CN 101521187 A CN101521187 A CN 101521187A
Authority
CN
China
Prior art keywords
wafer
closing line
exposed
integrated circuit
coating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200910126015A
Other languages
English (en)
Inventor
肯·兰姆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of CN101521187A publication Critical patent/CN101521187A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45157—Cobalt (Co) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45166—Titanium (Ti) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45184—Tungsten (W) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本文揭示一种具有顶部及底部侧电连接两者的晶片级批量处理的裸片大小的集成电路(IC)封装。在一个方面中，若干接合线可附加到IC晶片的所述顶部侧(有源电路侧)上的接合垫。沟槽可在划线区处形成于所述晶片中且所述接合线可延伸穿过所述沟槽。所述沟槽可填充有涂覆材料。所述接合线可部分地暴露于所述晶片的所述顶部及/或底部侧上以将来自所述接合垫的电连接分布到所述晶片的所述顶部及/或底部侧。

Description

具有顶部及底部侧电连接的晶片级集成电路封装
技术领域
此标的物通常涉及集成电路(IC)晶片处理。
背景技术
晶片级芯片尺寸级封装(WLCSP)技术经常用于便携式计算装置、移动手机、图像传感器等的高密度组件封装。WLCSP技术可包含封装、测试、及在将晶片单个化为个别IC芯片之前执行老化操作。在单个化期间，切割机沿划线锯割晶片以分离出个别IC芯片。在单个化IC芯片之后，可将所述IC芯片安装在印刷电路板(PCB)上。
典型的WLSCP IC芯片使用金属(例如，焊料)而非电线或引脚来安装到PCB上。通常，沿IC芯片的顶部或电路侧上的边缘设计并制造线接合垫。在大多数情况下，所述线接合垫具有小的几何形状且对于WLCSP大小的焊料球形成来说彼此也太靠近。再分布层(RDL)包含金属迹线，其与线接合垫接触且将信号重定位到IC芯片内较大底材面提供用于形成较大附加垫的所需位置。所述较大附加垫可用于放置较大直径的焊料球。可将焊料球沉积到新的位置处以促进到PCB或其它IC装置上的组装。
因为焊料球仅形成于晶片的顶部或电路侧上，因此由于在晶片的电连接到顶部侧的底部侧上缺少连接垫所致WLCSP不能用于装置堆叠应用。顶部或有源电路侧上I/O垫的存在可由于I/O特征对传感器元件的物理阻挡而使得WLCSP对于某些传感器应用不可行。
当前，通过形成穿过核心硅或衬底的传导“通孔”来在WLCSP中实现顶部到底部侧的电连接来解决这些问题。例如，通过使用铝掩模，可使用大气下游等离子(ADP)工艺在IC晶片的核心硅中蚀刻空穴。将介电材料及金属导体沉积到所述“空穴”的“侧壁”上。然后，用聚合物填充所述空穴。硅晶片经“薄化”以暴露晶片另一侧上的导体金属。在另一实例中，贯穿晶片互连(TWI)工艺形成穿过硅核心材料的通孔、绝缘所述侧壁且然后用导体填充所述通孔以实现从IC晶片的一个侧到另一侧的电连接性。一些封装组装承包商也正在开发类似的贯通硅通孔技术以实现“顶部-底部”电连接性。
发明内容
本文揭示一种具有顶部及底部侧电连接两者的晶片级批量处理的裸片大小的IC封装。在一个方面中，若干接合线可附加到IC晶片的顶部侧(有源电路侧)上的接合垫。在划线区处沟槽可形成于所述晶片中且所述接合线可经布置以延伸穿过所述沟槽到达所述晶片的底部侧。所述沟槽可填充有涂覆材料。所述接合线可部分地暴露在晶片的顶部及/或底部侧上以电连接晶片的顶部及/或底部侧上的垫位点。
所揭示的WLCSP技术通过利用标准线接合技术来实现晶片级处IC裸片的顶部与底部侧之间的电连接性来提供对常规技术的优点。所揭示的实施方案不需要可包含复杂的通孔特征设计、工具、设备及工艺的复杂TSV处理。TSV工艺昂贵且需要高级工艺开发工作。
所揭示的WLCSP所提供的另一优点是可使用允许将电路元件直接放置在线接合垫下面的标准IC设计规则。在常规TSV处理中，通孔不得不退出晶片的顶部及底部侧两者，且不能将电路放置在通孔处。因此，TSV可导致对IC裸片的需要比所揭示的WLCSP技术来得更大。
附图说明
图1A-1D图解说明具有顶部及底部侧电连接的实例半导体晶片。
图2A-2J是图解说明用于制造具有顶部及底部侧电连接的WLCSP的实例工艺的剖视图。
图3A-3B是图解说明传感器应用中使用的具有底部侧电连接的实例晶片的剖视图。
具体实施方式
WLCSP实例
图1A-1D图解说明具有顶部及底部侧电连接的实例半导体晶片100。在某些实施方案中，晶片100可使用参照图2所述的制造工艺来制造。
图1A是包含由划线区106分离的两个IC裸片101、103的晶片100的剖视图。实际上，典型的晶片可持有多于两个的IC裸片。接合线102在一个端处连接到接合垫104。接合线102穿过形成于划线区106中的沟槽从晶片100的顶部或有源电路侧布线到晶片100的底部侧。接合线102可由铜、金、铝或任何其它适合金属制成。接合线102允许到接合垫104提供的电连接的通路。接合线102可用于穿过顶部暴露区域(例如，晶片100顶部处的划线区106)及底部暴露区域(例如，晶片100底部处的划线区106)的电连接。焊料球108可附加到晶片100的底部以用于使经单个化的IC裸片101、103配合到PCB或其它IC装置。
图1B是晶片100的俯视(电路侧)平面图。在所示配置中，已暴露的接合线102使用再分布层(RDL)从划线区106的顶部暴露区域布线到晶片100内的电连接垫位点112。个别RDL金属迹线将电信号从划线区106的顶部暴露区域连接到连接垫位点112。RDL迹线可(例如)使用交替的有机或无机钝化层及敷金属层或采用电镀技术形成。可选地，有机层(例如，焊料掩模)可应用于RDL迹线以保护所暴露的金属。
图1C是晶片100的仰视图。在所示配置中，晶片100中的所暴露的接合线102已暴露在划线区106的底部暴露区域内。例如，晶片100的底部侧可涂覆有有机或无机介电层(例如，氧化硅、氮化硅、聚酰亚胺、苯并环丁烯(BCB)、环氧树脂、环氧树脂模制化合物)。然后，接合线102区内的介电层可经图案化以暴露接合线102。
从划线区106，所暴露的接合线102所提供的电连接可使用RDL迹线布线到电连接垫位点122。可选地，焊料球108可应用于电连接垫位点122。焊料球108可有助于将经单个化的IC裸片101、103连接到PCB或其它IC装置以用于堆叠式裸片封装解决方案。
如图1D中所示，在制造工艺完成之后，可沿划线区106将晶片100分离(锯割)成第一IC裸片130及第二IC裸片132。
制造工艺实例
图2A-2J是图解说明用于制造WLCSP的实例工艺的剖视图。图2A图解说明包含安置于硅核心材料(衬底)上且分布于划线区204的相对侧上的接合垫202的半导体晶片200。划线区204分离两个或两个以上邻近IC裸片。
图2B图解说明形成于划线区204内的沟槽206。在某些实例中，沟槽206可使用锯割技术(例如，金刚石锯割)或蚀刻技术形成。在某些实施方案中，沟槽206可具有在安置于晶片200内的“最低”电路元件下面约两微米的深度。例如，如果将电路元件安置于晶片200内在晶片200的顶部侧下面约两微米处，那么沟槽206可经锯割或蚀刻达到在IC晶片200的顶部侧下面约四微米的深度。
如图2C中所示，在沟槽206已形成之后，可将一光致抗蚀剂层208应用于晶片200的顶部侧。在一个实例中，可使用毯覆式涂覆工艺将均匀的光致抗蚀剂材料层208(例如，UV-敏感光致抗蚀剂、负性光致抗蚀剂、正性光致抗蚀剂)应用于晶片200的顶部侧及沟槽206的凹陷。沟槽206区内的光致抗蚀剂材料208可经曝光且显影出来，如图2D中所示。此步骤留下晶片200顶部侧上的光致抗蚀剂材料208的沉积。
图2E图解说明沉积在晶片200的顶部侧上(包含在沟槽206的凹陷内)的线可接合金属层201(例如，铝、钛钨金合金或还可附加到硅材料的用于线接合的其它适合冶金)。在某些实施方案中，可使用真空沉积技术来将线可接合金属层210沉积到晶片200的顶部侧上。如图2F中所示，在剥离掉光致抗蚀剂材料层208之后，仅残留内衬于沟槽206内的线可接合金属210。
可将一对接合线212添加到晶片200，如图2G中所示，从而将接合垫202连接到沟槽206内的线可接合金属层210。例如，标准线接合技术可用来将接合线212从接合垫202附加到沟槽206的基底。在某些实例中，接合线212可由金、铜、铝或其它适合金属制成。还可使用经涂覆或绝缘的接合线212。
如图2H中所示，可用有机材料214层涂覆晶片200。有机材料214覆盖接合线212。有机材料214可经薄化(如图2I中所示)以暴露接合线212。例如，使用碾磨机，可将有机材料214碾碎以暴露接合线212。类似地，晶片200的底部侧可如图2J中所示经薄化以暴露沟槽206的基底处的接合线212。
实施方案实例
图3A是图解说明具有底部侧电连接的实例半导体晶片300的剖视图。某些WLCSP应用需要晶片顶部侧上的暴露电路。例如，用于图像或指纹传感器电路(例如，用于相机的光电二极管、用于安全鉴定的生物测定芯片、CMOS图像传感器)的WLCSP可使用图2的工艺来形成以提供晶片300的顶部及/或底部侧上的暴露有源电路区域。
晶片300具有两个暴露的电路区域302。晶片300的顶部侧表面的剩余部分用有机涂层304(例如，环氧树脂、环氧树脂模制化合物、苯并环丁烯(BCB)、聚酰亚胺)覆盖。在某些实例中，可使用包覆模制、自动分配或旋涂制造方法来施加有机涂层304。有机涂层304覆盖接合线306。接合线306附加到接合垫308。接合线306穿过划线区310布线到晶片300的底部侧，如先前参照图2A-2J所述。
来自接合线306的电连接可使用RDL 312沿晶片300的底部侧布线。焊料块314可附加到RDL 312以允许来自接合垫308的电连接配合到PCB或其它IC装置。
图3B图解说明第一经单个化IC裸片320及第二经单个化IC裸片330。可通过沿划线区310(虚线所指示)分离(例如，锯割)晶片300来产生经单个化的IC裸片320、330。在单个化之后，例如，可使用焊料块314将经单个化的IC裸片320、330安装到其它电路。
尽管此文档含有许多具体的实施方案细节，但不应将其视为对可主张的范围的限制，而应视为对特定实施例而言可能是具体的特征的描述。此发明可能的一个实施方案是堆叠式裸片封装。例如，可将形成于第一WLCSP底部表面上的例如焊料球108(如图1A中所示)的焊料球附加到形成于第二WLCSP的顶部(例如，电路侧)表面上的例如连接垫112(如图1B中所示)的连接垫。堆叠式裸片封装可通过以此方式将底部安装的焊料球附加到顶部形成的连接垫来形成。可重复此步骤以形成多个裸片的堆叠式裸片封装。在此说明书中在单独实施例的背景中描述的某些特征还可以组合形式实施于单个实施例中。相反地，在单个实施例的背景中描述的各种特征也可分开地或以任何适合子组合形式实施于多个实施例中。而且，尽管上文可将特征描述为以某些组合形式起作用且甚至最初主张如此，但来自一所主张组合的一个或一个以上特征在一些情况下可从所述组合去除，且所述所主张组合可针对一子组合或一子组合的变化形式。
类似地，尽管在图式中以特定次序对操作进行描绘，但不应将此理解为需要以所示特定次序或顺序次序执行此类操作，或执行所有所图解说明的操作以实现期望结果。在某些情况下，多任务及并行处理可是有利的。而且，不应将在上文所述的实施例中各种系统组件的分离理解为在所有实施例中均需要此分离，且应理解，通常可将所述的程序组件及系统集成在一起于单个软件产品中或封装成多个软件产品。
本文已描述若干实施方案。然而，应理解，可进行各种修改。例如，可组合、删除、修改一个或一个以上工艺的步骤，或对其进行补充以形成其它工艺。作为又一实例，图中所描绘的工艺步骤不需要所示的特定次序来实现期望结果。另外，可提供其它步骤，或可从所述工艺消除某些步骤，且可向所述工艺添加或从所述工艺去除其它材料。因此，其它实施方案也在所附权利要求书范围内。

Claims (24)

1、一种集成电路晶片，其包括：
第一侧及第二侧；
涂覆材料，其形成于所述第一侧上；
沟槽，其在划线区处形成于所述晶片中，所述沟槽从所述第一侧延伸到所述第二侧且填充有所述涂覆材料；
若干接合垫，其形成于所述第一侧上且分布于所述沟槽的相对侧上；及
若干接合线，其连接到所述接合垫，所述接合线延伸穿过所述沟槽且至少部分地暴露于所述第一或第二侧上。
2、如权利要求1所述的晶片，其中所述涂覆材料是有机涂覆材料。
3、如权利要求1所述的晶片，其进一步包括：
形成于所述第二侧上的介电层。
4、如权利要求1所述的晶片，其进一步包括：
若干垫位点，其安置于所述第一或第二侧上以用于与已暴露的接合线连接。
5、如权利要求4所述的晶片，其中所述垫位点通过形成于所述第一或第二侧上的再分布层中的金属迹线连接到已暴露的接合线。
6、如权利要求4所述的晶片，其中所述垫位点连接到焊料球。
7、如权利要求1所述的晶片，其中所述接合线是经涂覆或绝缘的。
8、一种集成电路装置，其包括：
衬底，其具有第一侧和第二侧；
涂覆材料，其形成于所述衬底的所述第一侧及边缘上，所述涂覆材料沿所述边缘从所述第一侧延伸到所述第二侧；
若干接合垫，其形成于所述第一侧上；及
若干接合线，其连接到所述接合垫，所述接合线延伸穿过形成于所述边缘上的所述涂覆材料，所述接合线至少部分地暴露于所述第一及第二侧上；及
集成电路，其安置于所述第一侧上且电连接到所述接合垫。
9、如权利要求8所述的装置，其中所述涂覆材料是有机涂覆材料。
10、如权利要求8所述的装置，其进一步包括：
形成于所述第二侧上的介电层。
11、如权利要求8所述的装置，其进一步包括：
若干垫位点，其安置于所述第一或第二侧上以用于与已暴露的接合线连接。
12、如权利要求11所述的装置，其中所述垫位点通过形成于所述第一或第二侧上的再分布层中的金属迹线连接到所述已暴露的接合线。
13、如权利要求11所述的装置，其中所述垫位点连接到焊料球。
14、如权利要求8所述的装置，其中所述接合线是经涂覆或绝缘的。
15、一种制造晶片级集成电路封装的方法，其包括：
在集成电路晶片的划线区处形成沟槽区，所述晶片具有第一侧及第二侧，其中将若干线接合垫安置于所述第一侧上及所述划线区的相对侧上；
用光致抗蚀剂涂覆所述第一侧；
曝光并显影所述沟槽区中的所述光致抗蚀剂；
在所述第一侧上沉积金属层；
从所述晶片剥离包含所述光致抗蚀剂上的所述金属层的所述光致抗蚀剂，所述剥离留下所述沟槽区中的所述金属层；
将接合线从所述线接合垫连接到所述沟槽区的基底；
用有机材料涂覆所述第一侧；及
图案化所述有机涂层以至少部分地暴露所述第一侧上的所述接合线。
16、如权利要求15所述的方法，其进一步包括：
图案化所述晶片以至少部分地暴露所述第二侧上的所述接合线。
17、如权利要求15所述的方法，其中使用锯割或蚀刻形成所述沟槽区。
18、如权利要求15所述的方法，其中所述沟槽区的深度在安置于所述第一侧上的最低电路元件以下至少约2微米。
19、如权利要求15所述的方法，其中使用真空沉积技术沉积所述金属层。
20、如权利要求15所述的方法，其中所述有机涂层是选自由以下构成的有机涂层群组中的一者：环氧树脂、环氧树脂模制化合物、聚酰亚胺及苯并环丁烯(BCB)。
21、如权利要求15所述的方法，其中所述接合线由选自由以下构成的金属群组中的金属制成：铜、铝、钨、氮化钛、硅化物、硅化钛、硅化钴、硅化镍及金。
22、如权利要求15所述的方法，其中所述接合线是经涂覆或绝缘的。
23、如权利要求15所述的方法，其进一步包括：
暴露所述第一侧上的有源电路区域。
24、如权利要求23所述的方法，其进一步包括：
在所述划线区处锯割所述晶片以形成经单个化的封装。
CN200910126015A 2008-02-28 2009-02-27 具有顶部及底部侧电连接的晶片级集成电路封装 Pending CN101521187A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/039,335 2008-02-28
US12/039,335 US8018065B2 (en) 2008-02-28 2008-02-28 Wafer-level integrated circuit package with top and bottom side electrical connections

Publications (1)

Publication Number Publication Date
CN101521187A true CN101521187A (zh) 2009-09-02

Family

ID=41012550

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910126015A Pending CN101521187A (zh) 2008-02-28 2009-02-27 具有顶部及底部侧电连接的晶片级集成电路封装

Country Status (3)

Country Link
US (1) US8018065B2 (zh)
CN (1) CN101521187A (zh)
TW (1) TW200952139A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915354A (zh) * 2013-01-03 2014-07-09 台湾积体电路制造股份有限公司 用于bot层压封装件的改进的焊料掩模形状
CN104134645B (zh) * 2014-06-30 2017-06-27 厦门润晶光电集团有限公司 一种封装导线材料结构及其加工方法

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8447077B2 (en) 2006-09-11 2013-05-21 Validity Sensors, Inc. Method and apparatus for fingerprint motion tracking using an in-line array
WO2006041780A1 (en) 2004-10-04 2006-04-20 Validity Sensors, Inc. Fingerprint sensing assemblies comprising a substrate
US8116540B2 (en) 2008-04-04 2012-02-14 Validity Sensors, Inc. Apparatus and method for reducing noise in fingerprint sensing circuits
EP2321764A4 (en) 2008-07-22 2012-10-10 Validity Sensors Inc SYSTEM, DEVICE AND METHOD FOR SECURING A DEVICE COMPONENT
US8168458B2 (en) * 2008-12-08 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices
WO2010079803A1 (ja) * 2009-01-07 2010-07-15 株式会社大真空 圧電振動デバイスの製造方法
US8278946B2 (en) 2009-01-15 2012-10-02 Validity Sensors, Inc. Apparatus and method for detecting finger activity on a fingerprint sensor
US8600122B2 (en) 2009-01-15 2013-12-03 Validity Sensors, Inc. Apparatus and method for culling substantially redundant data in fingerprint sensing circuits
US8374407B2 (en) * 2009-01-28 2013-02-12 Validity Sensors, Inc. Live finger detection
TWM362572U (en) * 2009-04-13 2009-08-01 Phytrex Technology Corp Signal convertor
US9336428B2 (en) * 2009-10-30 2016-05-10 Synaptics Incorporated Integrated fingerprint sensor and display
US9666635B2 (en) 2010-02-19 2017-05-30 Synaptics Incorporated Fingerprint sensing circuit
US8716613B2 (en) 2010-03-02 2014-05-06 Synaptics Incoporated Apparatus and method for electrostatic discharge protection
US9001040B2 (en) 2010-06-02 2015-04-07 Synaptics Incorporated Integrated fingerprint sensor and navigation device
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8538097B2 (en) 2011-01-26 2013-09-17 Validity Sensors, Inc. User input utilizing dual line scanner apparatus and method
US8594393B2 (en) 2011-01-26 2013-11-26 Validity Sensors System for and method of image reconstruction with dual line scanner using line counts
GB2489100A (en) * 2011-03-16 2012-09-19 Validity Sensors Inc Wafer-level packaging for a fingerprint sensor
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9195877B2 (en) 2011-12-23 2015-11-24 Synaptics Incorporated Methods and devices for capacitive image sensing
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9137438B2 (en) 2012-03-27 2015-09-15 Synaptics Incorporated Biometric object sensor and method
US9251329B2 (en) 2012-03-27 2016-02-02 Synaptics Incorporated Button depress wakeup and wakeup strategy
US9600709B2 (en) 2012-03-28 2017-03-21 Synaptics Incorporated Methods and systems for enrolling biometric data
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9651513B2 (en) 2012-10-14 2017-05-16 Synaptics Incorporated Fingerprint sensor and button combinations and methods of making same
US9665762B2 (en) 2013-01-11 2017-05-30 Synaptics Incorporated Tiered wakeup strategy
US11826636B2 (en) * 2013-07-12 2023-11-28 Chris Argiro Depth sensing module and mobile device including the same
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
CN104051367A (zh) * 2014-07-01 2014-09-17 苏州晶方半导体科技股份有限公司 指纹识别芯片封装结构和封装方法
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10055631B1 (en) 2015-11-03 2018-08-21 Synaptics Incorporated Semiconductor package for sensor applications
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10784121B2 (en) * 2016-08-15 2020-09-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (SSI) technology integration
US9996725B2 (en) * 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly
US10115579B2 (en) * 2016-11-30 2018-10-30 Asm Technology Singapore Pte Ltd Method for manufacturing wafer-level semiconductor packages
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
TWI672779B (zh) * 2016-12-28 2019-09-21 曦威科技股份有限公司 指紋辨識裝置、使用其之行動裝置以及指紋辨識裝置的製造方法
US11282776B2 (en) * 2018-02-22 2022-03-22 Xilinx, Inc. High density routing for heterogeneous package integration
US10811382B1 (en) * 2019-05-07 2020-10-20 Nanya Technology Corporation Method of manufacturing semiconductor device
EP3780092B1 (en) * 2019-06-14 2023-03-01 Shenzhen Goodix Technology Co., Ltd. Chip packaging structure and electronic device
EP3780095A1 (en) * 2019-06-14 2021-02-17 Shenzhen Goodix Technology Co., Ltd. Chip encapsulation structure and electronic device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926723B1 (en) 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US7109842B1 (en) 1998-12-07 2006-09-19 Honeywell International Inc. Robust fluid flow and property microsensor made of optimal material
US6541301B1 (en) 1999-02-12 2003-04-01 Brook David Raymond Low RF loss direct die attach process and apparatus
US7211877B1 (en) 1999-09-13 2007-05-01 Vishay-Siliconix Chip scale surface mount package for semiconductor device and process of fabricating the same
WO2002079853A1 (en) 2001-03-16 2002-10-10 Corning Intellisense Corporation Electrostatically actuated micro-electro-mechanical devices and method of manufacture
US6910268B2 (en) 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6836020B2 (en) 2003-01-22 2004-12-28 The Board Of Trustees Of The Leland Stanford Junior University Electrical through wafer interconnects
US6768189B1 (en) 2003-06-04 2004-07-27 Northrop Grumman Corporation High power chip scale package
US7005388B1 (en) 2003-12-04 2006-02-28 National Semiconductor Corporation Method of forming through-the-wafer metal interconnect structures
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7495462B2 (en) 2005-03-24 2009-02-24 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
SE1050461A1 (sv) 2006-02-01 2010-05-10 Silex Microsystems Ab Metoder för tillverkning av en startsubstratskiva för halvledartillverkning, med skivgenomgående anslutningar

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915354A (zh) * 2013-01-03 2014-07-09 台湾积体电路制造股份有限公司 用于bot层压封装件的改进的焊料掩模形状
CN103915354B (zh) * 2013-01-03 2017-04-26 台湾积体电路制造股份有限公司 用于bot层压封装件的改进的焊料掩模形状
CN104134645B (zh) * 2014-06-30 2017-06-27 厦门润晶光电集团有限公司 一种封装导线材料结构及其加工方法

Also Published As

Publication number Publication date
TW200952139A (en) 2009-12-16
US8018065B2 (en) 2011-09-13
US20090218698A1 (en) 2009-09-03

Similar Documents

Publication Publication Date Title
CN101521187A (zh) 具有顶部及底部侧电连接的晶片级集成电路封装
TWI718606B (zh) 半導體元件及其形成方法
US9418969B2 (en) Packaged semiconductor devices and packaging methods
US9418970B2 (en) Redistribution layers for microfeature workpieces, and associated systems and methods
TWI543332B (zh) 半導體晶粒封裝與封裝上封裝裝置
TWI579966B (zh) 半導體封裝系統及方法
TWI511253B (zh) 晶片封裝體
CN104347528B (zh) 半导体封装件及其制法
CN102969305B (zh) 用于半导体结构的管芯对管芯间隙控制及其方法
TWI604570B (zh) 一種晶片尺寸等級的感測晶片封裝體及其製造方法
TWI551199B (zh) 具電性連接結構之基板及其製法
CN108122784A (zh) 封装单体化的方法
US20190385975A1 (en) Integrated fan-out package and manufacturing method thereof
TW201347122A (zh) 晶片封裝體及其形成方法
CN107665819A (zh) 半导体管芯切割及由此形成的结构
TW201917863A (zh) 半導體裝置封裝
US9355979B2 (en) Alignment structures and methods of forming same
CN107134413A (zh) 半导体装置以及制造的方法
US20220359429A1 (en) Extended Seal Ring Structure on Wafer-Stacking
TW201633476A (zh) 在緩衝層中具有開口的積體扇出結構
US20220093498A1 (en) Hybrid Dielectric Scheme in Packages
TW201909343A (zh) 封裝結構及其製造方法
CN105633053A (zh) 基板结构及其制法
CN205810806U (zh) 晶片级芯片尺寸封装体
CN118335695A (zh) 半导体结构及其形成方法、封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20090902