CN101515472A - Method for accessing memory chip - Google Patents
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- CN101515472A CN101515472A CNA200810080477XA CN200810080477A CN101515472A CN 101515472 A CN101515472 A CN 101515472A CN A200810080477X A CNA200810080477X A CN A200810080477XA CN 200810080477 A CN200810080477 A CN 200810080477A CN 101515472 A CN101515472 A CN 101515472A
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Abstract
The invention provides a method for accessing a memory chip, which comprises the following steps that: a plurality of first input pins and a plurality of second output pins are arranged on the memory chip; a plurality of column address strobes are input into the plurality of first input pins respectively, wherein a length of a column address command packet of each column address strobe is multiple frequency periods of a frequency signal, and the column address command packet comprises a plurality of column input commands; and a plurality of row address strobes are input to the plurality of second input pins respectively, wherein a length of a row address command packet of each row address strobe is multiple frequency periods of the frequency signal, and the row address command packet comprises a plurality of row input commands.
Description
Technical field
The present invention relates to a kind of method of accessing memory chip, particularly relate to and a kind ofly can reduce dynamic RAM (Dynamic Random Access Memory, DRAM) method of input pin count purpose accessing memory chip.
Background technology
At existing double data rate (Double Data Rate, DDR) under Synchronous Dynamic Random Access Memory (Synchronous DRAM) framework, Synchronous Dynamic Random Access Memory has following input signal: two frenquency signal CLK and #CLK, 16 storage address input signal A0～A15, four thesaurus address input signal BA0～BA3, one chip is selected signal CS, one column address strobe (rowaddress strobe) signal RAS, one row address strobe (column address strobe) signal CAS, one writes activation (Write Enable, WE) signal, one synchronous signal CKE, an one calibration signal ZQ and a replacement signal RESET.The length of an input command of above-mentioned each input signal is a frequency period of a frenquency signal, and each input signal all need be come in the input store chip by an exclusive pin, and therefore existing Synchronous Dynamic Random Access Memory can be provided with 29 input pins.
Please refer to Fig. 1, Fig. 1 is existing biserial pin memory module (Dual In-line MemoryModule, DIMM) 100 synoptic diagram.As shown in Figure 1, biserial pin memory module 100 includes eight memory chip 110_1～110_8, and wherein each memory chip all includes 29 input pins.In the operation of biserial pin memory module 100,29 input signals are to input to memory chip 110_1 by a controller 120, transfer in proper order afterwards memory chip 110_2,110_3 ..., 110_8, therefore two adjacent memory chips all have 29 circuits to be connected to each other.Generally speaking, the input pin is many more, the spacing of signal wire also can diminish and increase the degree of difficulty of wiring on circuit, and signal wire also is interfered than being easier to each other, therefore the layout of circuit can be comparatively difficult on the biserial pin memory module 100, in addition, when the storage core built-in testing, the cost of mould also can reduce than the quantity of higher and the memory chip that measurement platform once can be tested.
Summary of the invention
Therefore one of purpose of the present invention is to provide a kind of method that can reduce the accessing memory chip of storer input pin count, with signal line densities and the cost cost of storer in test that reduces biserial pin memory module.
According to one embodiment of the invention, it discloses a kind of method of access one memory chip.This method includes: in this memory chip a plurality of first input pins and a plurality of second input pin are set; A plurality of column address signals are imported this a plurality of first input pins respectively, and wherein the length of a column address command packet of each column address signal is a plurality of frequency periods of a frenquency signal, and this column address command packet includes a plurality of row input commands; And with a plurality of row address signals input to respectively this a plurality of second the input pins, wherein the length of delegation's address command grouping of each row address signal is a plurality of frequency periods of this frenquency signal, and this row address command packet includes a plurality of capable input commands.
According to the method for accessing memory chip provided by the present invention, can not influence the input pin that reduces storer under the storer usefulness, and then promote the easness of biserial pin memory module on configuration, and reduce the cost in the test.
Description of drawings
Fig. 1 is the synoptic diagram of existing biserial pin memory module
Fig. 2 is the synoptic diagram of an embodiment of memory chip of the present invention.
Fig. 3 is the synoptic diagram of six column address signals of the embodiment of the invention.
Fig. 4 is the synoptic diagram of five row address signals of the embodiment of the invention.
Fig. 5 is the synoptic diagram of an example operation of access of the present invention memory chip shown in Figure 2.
The reference numeral explanation
| 100 | Biserial pin memory module |
| 110_1～110_8 | |
| 120 | |
| 200 | Memory chip |
| PIN_CLK | The frequency pin |
| PIN_R0～PIN_R5 | Column address signal pin |
| PIN_C0～PIN_C4 | Row address signal pin |
| PIN_CSR | First chip is selected the signal pin |
| PIN_CSC | Second chip is selected the signal pin |
| CLK | Frenquency signal |
| RowAdr0、RowAdr1、RowAdr2、 RowAdr3、RowAdr4、RowAdr5、 | The column address signal |
| A0、A1、A2、A3、A4、A5、A6、 A7、A8、A9、A10、A11、A12、A13、 A14、A15 | The set information of storage address |
| BA0、BA1、BA2、BA3 | The set information of thesaurus address |
| CMD0、CMD1、CMD2、CMD3 | The set information of storer control command |
| ColAdr0、ColAdr1、ColAdr2、 ColAdr3、ColAdr4 | The column address signal |
| WE | Write the activation input command |
| AP | The auto-precharge input command |
| BC4/BL8 | Burst interruption/burst-length input command |
| CSR | The column address chip is selected signal |
| CSC | The row address chip is selected signal |
Embodiment
Under existing double data rate Synchronous Dynamic Random Access Memory framework, the length of an input command of each input signal is a frequency period of a frenquency signal, and each input signal comes in the input store chip by an exclusive pin, and therefore always meeting together needs 29 pins.In order to reduce the quantity of pin, the present invention has used the notion of " command packet ", that is pin is used for importing a command packet and each command packet comprises four input commands, so just can reduce the quantity of memory chip pin, yet, because it is a frequency period that each command packet comprises the length of four input commands and an input command, therefore the length of a command packet is four frequency periods, in the operation of storer, because in same thesaurus, can not carry out input of column address signal and the input of row address signal simultaneously, if therefore only using length is the command packet of four frequency periods, in same thesaurus, must wait until that the column address signal imports back four frequency periods, the row address signal just can be imported, and so will seriously reduce the usefulness of storer.
Therefore, the present invention proposes a kind of method that can reduce the input pin of storer and more can not reduce storer usefulness, details are as follows for relevant running details.
See also Fig. 2, Fig. 2 is the synoptic diagram of an embodiment of memory chip 200 of the present invention.As shown in the figure, memory chip 200 includes a frequency pin PIN_CLK, six row (row) address signal pin PIN_R0～PIN_R5, five row (column) address signal pin PIN_C0～PIN_C4, one first chip selection signal (the column address chip is selected signal) pin PIN_CSR and one second chip selection signal (the row address chip is selected signal) pin PIN_CSC.In the present embodiment, frequency pin PIN_CLK is used for receiving a frenquency signal CLK, column address signal pin PIN_R0～PIN_R5 is used for receiving respectively six column address signal RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5, row address signal pin PIN_C0～PIN_C4 is used for receiving respectively five row address signal ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4, first chip is selected signal (the column address chip is selected signal) pin PIN_CSR to be used for receiving one first chip to select signal (the column address chip is selected signal) CSR selecting using memory chip 200 to receive this a plurality of column address signals, and second chip is selected signal (the row address chip is selected signal) pin PIN_CSC to be used for receiving one second chip to select signal (the row address chip is selected signal) CSC to select using this memory chip to receive this a plurality of row address signals.Please note, the configuration of the pin of memory chip 200 shown in Figure 2 is only as the usefulness of example explanation, and do not influencing under the technology of the present invention disclosure, only demonstrate a part of pin relevant among Fig. 2 with follow-up explanation of the present invention, in fact, the present invention does not limit memory chip 200 and only has pin shown in Figure 2 configuration.The accessing operation of memory chip 200 of the present invention will be described in detail in the following.
Please refer to Fig. 3, Fig. 3 is the synoptic diagram of six row (row) address signal of the embodiment of the invention.In the present invention, six column address signal RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5 is via six first input pins (that is column address signal pin PIN_R0 shown in Figure 2～PIN_R5) input in the memory chip, as shown in Figure 3, (length of the column address command packet (row address commandpackage) of RowAdr0～RowAdr5) is four frequency periods of a frenquency signal CLK to each column address signal, and the column address command packet includes four row input commands, therefore, six of six column address signals column address command packet include 24 row input commands altogether.In the present embodiment, these 24 row input commands include the set information BA0～BA3 of four thesaurus addresses, set information A0～the A15 of 16 storage addresss and the set information CMD0～CMD3 of four storer control commands, wherein the set information BA0～BA3 of four thesaurus addresses equals the thesaurus address input signal BA0～BA3 under the existing double data rate Synchronous Dynamic Random Access Memory framework, and the set information A0～A15 of 16 storage addresss equals the storage address input signal A0～A15 under the existing double data rate Synchronous Dynamic Random Access Memory framework.In addition, set information CMD0～the CMD3 of four storer control commands is via decoding to produce the control command in a plurality of storer control commands, wherein these a plurality of storer control commands can include startup (Active), precharge (Precharge), upgrade (Refresh), temporary (the mode register set that sets of pattern, MRS), self (self-refresh entry, SRE), enter low-power consumption (power down entry), long calibration/weak point calibration (ZQ calibrationlong/ZQ calibration short, ZQCL/ZQCS) ... or the like.
Please refer to Fig. 4, Fig. 4 is the synoptic diagram of five row (column) address signal of the embodiment of the invention.In the present invention, these five row address signal ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4 is via five second input pins (that is row address signal pin PIN_C0 shown in Figure 2～PIN_C4) input in the memory chip, as shown in Figure 4, (length of delegation's address command grouping (column address command package) of ColAdr0～ColAdr4) is four frequency periods of a frenquency signal CLK to each row address signal, and the row address command packet includes four capable input commands, therefore, five column address command packet of five row address signals include 20 capable input commands altogether, these 20 capable input commands include the set information BA0～BA3 of four thesaurus addresses, set information A0～the A12 of 13 storage addresss, one writes activation (Write Enable, WE) input command, one auto-precharge (Auto Pre-charge, AP) 4/ burst-length 8 (Burst Chop 4/Burst Length 8 is interrupted in an input command and a burst, BC4/BL8) input command, wherein the set information BA0～BA3 of four thesaurus addresses equals the thesaurus address input signal BA0～BA3 under the existing double data rate Synchronous Dynamic Random Access Memory framework, and the set information A0～A12 of 13 storage addresss equals the storage address input signal A0～A12 under the existing double data rate Synchronous Dynamic Random Access Memory framework.
Be noted that the input command that six column address command packet of six column address signals shown in Figure 3 are comprised respectively only as the usefulness of example explanation, on real the work, can exchange arbitrarily by 24 row input commands shown in Figure 3; In like manner, memory bank operation of the present invention also can be exchanged and not influence to 20 capable input commands shown in Figure 4 arbitrarily.In addition, above-mentioned column address signal (RowAdr0～RowAdr5), ((quantity of BA0～BA3) is also only as the usefulness of example explanation for the ColAdr0～ColAdr4) and the set information of thesaurus address for the row address signal, on real the work, if want the capacity of extended storage, that is increase the set information of storage address or increase thesaurus quantity, then the column address signal can for seven or above and row address signal can for six or more than, for example, memory chip 200 can increase a column address signal pin PIN_R6 and the address signal pin PIN_C5 of delegation, wherein column address signal pin PIN_R6 is used for receiving a column address signal RowAdr6, and the column address command packet of column address signal RowAdr6 includes the set information BA4 of two thesaurus addresses, BA5, and the set information A16 of two storage addresss, A17; And row address signal pin PIN_C5 is used for receiving the address signal ColAdr5 of delegation, and the row address command packet of row address signal ColAdr5 includes set information BA4, the BA5 of two thesaurus addresses, and set information A13, the A14 of two storage addresss.As mentioned above, because the grouping of row of the present invention (OK) address command includes four row (OK) input command, therefore for the set information and the thesaurus quantity of extended storage address, only need a column address signal pin of increase and a row address signal pin just can increase the set information of four thesaurus addresses or the set information of storage address, therefore can significantly reduce the testing cost of memory chip.
As mentioned above, six column address signals and five row address signals all include the set information (A0, A1, A3...) of storage address, so can carry out different operations to different thesauruss at one time.Fig. 5 is the synoptic diagram of an example operation of access of the present invention memory chip shown in Figure 2.As shown in Figure 5, for example, in time T 1, six column address command packet of six column address signal RowAdr0～RowAdr5 are used for starting one first thesaurus in (active) memory chip 200, and at one time, five column address command packet of five row address signal ColAdr0～ColAdr4 can be used to write one second thesaurus in (write) memory chip 200 (if this second thesaurus started); In time T 2, six column address command packet of six column address signal RowAdr0～RowAdr5 are used for starting one the 3rd thesaurus; In time T 3, five column address command packet of five row address signal ColAdr0～ColAdr4 can be used to read (read) this first thesaurus.Thus, just can slow down because use length is the influence that the command packet of four frequency periods causes storer usefulness to reduce.
Under double data rate Synchronous Dynamic Random Access Memory framework, have many parameters that the numerical value of regulation is all arranged, for example column address to column address time delay (RAS to RAS delay time) tRRD, column address precharge time (RAS pre-charge time) tRP, column address to row address time delay (RAS to CAS delay time) tRCD, row (Row cycle time) tRC... cycle length or the like.If the cycle of memory frequency signal is 1.25 how second (nano-second), how second the column address command packet then proposed by the invention and the length of row address command packet then are 5, all can suitably use at above-mentioned double data rate Synchronous Dynamic Random Access Memory and without prejudice to relevant parameter regulation.For example, how second column address tRP precharge time needs 10 at least, then be the length of two column address command packet in the present invention, that is the interval of a column address command packet can be arranged when same thesaurus carried out precharge and start-up operation, therefore can image to the usefulness of storer.
In addition, under existing double data rate Synchronous Dynamic Random Access Memory framework, there is a chip that is used for activation one chip to select signal.In the present invention, because six column address signals and five row address signals all include the set information of storage address, therefore the present invention has added one first chip selection signal (the column address chip is selected signal) CSR in addition to select using this memory chip to receive this a plurality of column address signals, and one second chip select signal (the row address chip is selected signal) CSC to select using this memory chip to receive this a plurality of row address signals, wherein the column address chip selects signal CSR and row address chip to select signal CSC to input in the memory chip via one the 3rd input pin (that is first chip shown in Figure 1 is selected signal (the column address chip is selected signal) pin PIN_CSR) and one the 4th input pin (that is second chip shown in Figure 2 is selected signal (the row address chip is selected signal) pin PIN_CSC) respectively.As shown in Figure 5, when the column address chip selected signal CSR or row address chip to select signal CSC activation, this memory chip just can receive column address signal or row address signal.
The simple method of concluding above-mentioned accessing memory chip, in input signal of the present invention, the length of six column address command packet of six column address signals is four frequency periods, and each column address command packet includes four row input commands; And the length of five row address command packet of five row address signals is four frequency periods, and each row address command packet includes four capable input commands.Aforesaid 11 address input signals, add two frenquency signal CLK and #CLK, the column address chip is selected signal CSR, the row address chip is selected signal CSC, one internal interrupt resistance signal (on-die termination) ODT, sync signal CKE, calibration signal ZQ and replacement signal RESET, access method of storage proposed by the invention needs the nineteen input signal altogether, that is memory chip only needs the nineteen pin, two nineteen pins compared to the existing memory chip, the present invention can reduce the input pin of storer really, and then promote the easness of biserial pin memory module on configuration, and reduce the cost in the test.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. the method for access one memory chip, it includes:
In this memory chip a plurality of first input pins and a plurality of second input pin are set;
A plurality of column address signals are imported this a plurality of first input pins respectively, and wherein the length of a column address command packet of each column address signal is a plurality of frequency periods of a frenquency signal; And
A plurality of row address signals are inputed to this a plurality of second input pins respectively, and wherein the length of delegation's address command grouping of each row address signal is a plurality of frequency periods of this frenquency signal.
2. the method for claim 1, wherein this column address command packet includes a plurality of row input commands, and this row address command packet includes a plurality of capable input commands.
3. method as claimed in claim 2, wherein the length of this column address command packet is four frequency periods, and this column address command packet includes four row input commands, wherein pin count of these a plurality of first input pins is six.
4. method as claimed in claim 3, wherein a plurality of row input commands in six column address command packet being transmitted of these a plurality of column address signals include the set information of the set information of four thesaurus addresses, 16 storage addresss and the set information of four storer control commands.
5. method as claimed in claim 4 also includes:
The set information of deciphering these four storer control commands is to produce a storer control command.
6. method as claimed in claim 3, wherein the length of this row address command packet is four frequency periods, and this row address command packet includes four capable input commands.
7. method as claimed in claim 6, wherein the pin count of these a plurality of second input pins is five.
8. method as claimed in claim 7, wherein a plurality of capable input command in five row address command packet being transmitted of these a plurality of row address signals includes the set information of at least four thesaurus addresses and the set information of 13 storage addresss.
9. method as claimed in claim 7, wherein a plurality of capable input command in five row address command packet being transmitted of these a plurality of row address signals includes at least one activation input command, an auto-precharge input command and burst interruption/burst-length input command of writing.
10. the method for claim 1 also includes:
In this memory chip one the 3rd input pin and one the 4th input pin are set;
Select signal to input to the 3rd input pin one first chip, to select using this memory chip to receive this a plurality of column address signals; And
Select signal to input to the 4th input pin one second chip, to select using this memory chip to receive this a plurality of row address signals.
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| CN200810080477XA CN101515472B (en) | 2008-02-19 | 2008-02-19 | Method for accessing memory chip |
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| CN200810080477XA CN101515472B (en) | 2008-02-19 | 2008-02-19 | Method for accessing memory chip |
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| CN101515472B CN101515472B (en) | 2012-05-02 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9898400B2 (en) * | 2009-08-20 | 2018-02-20 | Rambus Inc. | Single command, multiple column-operation memory device |
| CN109933283A (en) * | 2017-12-19 | 2019-06-25 | 西部数据技术公司 | Direct host accesses storage device memory space |
| US11720283B2 (en) | 2017-12-19 | 2023-08-08 | Western Digital Technologies, Inc. | Coherent access to persistent memory region range |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4253097B2 (en) * | 1999-12-28 | 2009-04-08 | 東芝マイクロエレクトロニクス株式会社 | Semiconductor memory device and data read method thereof |
| US7073014B1 (en) * | 2000-07-28 | 2006-07-04 | Micron Technology, Inc. | Synchronous non-volatile memory system |
| US20050135180A1 (en) * | 2000-06-30 | 2005-06-23 | Micron Technology, Inc. | Interface command architecture for synchronous flash memory |
| KR100699810B1 (en) * | 2000-08-05 | 2007-03-27 | 삼성전자주식회사 | Semiconductor memory device and memory system for improving bus efficiency |
| CN1702768A (en) * | 2004-05-26 | 2005-11-30 | 恩益禧电子股份有限公司 | Semiconductor storage device |
| US20060294295A1 (en) * | 2005-06-24 | 2006-12-28 | Yukio Fukuzo | DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device |
| US20070189084A1 (en) * | 2006-02-15 | 2007-08-16 | Broadcom Corporation | Reduced pin count synchronous dynamic random access memory interface |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9898400B2 (en) * | 2009-08-20 | 2018-02-20 | Rambus Inc. | Single command, multiple column-operation memory device |
| US10552310B2 (en) | 2009-08-20 | 2020-02-04 | Rambus Inc. | Single command, multiple column-operation memory device |
| US11204863B2 (en) | 2009-08-20 | 2021-12-21 | Rambus Inc. | Memory component that performs data write from pre-programmed register |
| US11720485B2 (en) | 2009-08-20 | 2023-08-08 | Rambus Inc. | DRAM with command-differentiated storage of internally and externally sourced data |
| US11748252B2 (en) | 2009-08-20 | 2023-09-05 | Rambus Inc. | Data write from pre-programmed register |
| CN109933283A (en) * | 2017-12-19 | 2019-06-25 | 西部数据技术公司 | Direct host accesses storage device memory space |
| CN109933283B (en) * | 2017-12-19 | 2022-06-28 | 西部数据技术公司 | Direct host access storage device storage space |
| US11681634B2 (en) | 2017-12-19 | 2023-06-20 | Western Digital Technologies, Inc. | Direct host access to storage device memory space |
| US11720283B2 (en) | 2017-12-19 | 2023-08-08 | Western Digital Technologies, Inc. | Coherent access to persistent memory region range |
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| CN101515472B (en) | 2012-05-02 |
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