CN101075654A - Process for reversing pure-golden Au alloy bonding LED - Google Patents
Process for reversing pure-golden Au alloy bonding LED Download PDFInfo
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- CN101075654A CN101075654A CNA2006101244494A CN200610124449A CN101075654A CN 101075654 A CN101075654 A CN 101075654A CN A2006101244494 A CNA2006101244494 A CN A2006101244494A CN 200610124449 A CN200610124449 A CN 200610124449A CN 101075654 A CN101075654 A CN 101075654A
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Abstract
This is a process method of a pure Au and alloy LED. It is composed by a P-N expending slice, pure Au filling layer, alloy filling layer and a silicon underlay of reflection layer. The P-N expending slice includes a sapphirine underlay, a N-GaN layer on the underlay, a P-GaN layer on the N-GaN layer and a reflection layer in between. A metal layer which is good for current diffusion is deposited on the P-GaN layer. A P/N electrode is led from the P-GaN layer and the N-GaN layer separately. An isolation layer is formed in between the P/N electrode. An electric insulation layer is formed on a silicon underlay, to the top formed a metal reflection layer. The P-N expending slice is heat jointed with the silicon underlay by filling in pure Au and alloy.
Description
Technical field
The present invention relates to a kind of production process of semiconductor device method, particularly relate to the preparation method of the alloy bonding LED flip-chip (Flip-Chip) of a kind of proof gold Au.
Background technology
The LED technical development by now, the raising of unit light flux makes it can enter lighting field to be called semiconductor lighting that semiconductor lighting is the real revolution of lighting technology in the last hundred years.Because semi-conducting material is converted into light with electric energy, can not produce heat so semiconductor lighting has with different its light that are of traditional lighting light source maximum.Yet, being accompanied by the technical bottleneck of heat radiation aspect in the raising process of great power LED luminous flux, whether success directly has influence on the optical parametric of semiconductor lighting and the index of aging of product to radiating treatment.
At present, traditional Sapphire Substrate GaN high-power chip, electrode is positioned on the exiting surface of chip.About 30% light is absorbed by the P electrode, and because the limited conductivity of P-GaN layer, requirement precipitates the metal level of one deck electric current diffusion again at the P-GaN laminar surface.This current-diffusion layer can cover a part of light, thereby reduces the light extraction efficiency of chip.Therefore this P type contact structures have restricted the operating power of led chip.The heat of simultaneously this structure pn knot is derived by Sapphire Substrate and is gone, and thermally conductive pathways is longer.Because sapphire thermal conductivity coefficient is than metal low (35W/mK), therefore, the led chip thermal resistance of this structure can be bigger.In addition, the P electrode of this structure and lead-in wire also can block part light and enter device package, and are coated with last layer epoxy resin usually above the positive assembling structure, and the epoxy resin capacity of heat transmission is very poor, causes the difficult problem of heat radiation, influences the performance parameter and the reliability of device.So this packed LED chip all constitutes considerable influence from device architecture itself to aspects such as device power, light extraction efficiency and hot propertys.In order to overcome these deficiencies of positive cartridge chip, the PbSn flip-chip has been invented by U.S. Lumileds company.Galliumnitride base LED chip tips upside down on the silicon, and two routing pads are arranged on the silicon, beats gold thread during encapsulation and extraneous power supply joins.Back-off solder technology technology comprises that technologies such as plating corresponding BUMP on several BUMP (PbSn) that weld on the electrode and silicon substrate welds together by eutectic, silicon substrate is by adhesives and device inside is heat sink bonds together, and light takes out from Sapphire Substrate.With respect to positive assembling structure, this inverted structure has the more excellent characteristics in aspect such as electricity, light, heat.
But in the above-mentioned flip chip structure, the minimum spacing of silicon substrate and chip chamber is approximately 25-40 μ m, and the contact area of chip and electrode and silicon chip is limited, and stability, reliability and the conductivity of heat of electrode and the formed ohmic contact of silicon chip still have limitation.Adopt the Pb metal in addition, technical process and not environmental protection of product.In flip-chip manufacturing process, how to improve the forward voltage of chip, the indirect chip cooling problem of improving improves the quality and the rate of finished products of flip-chip, adopts the technology and the material of environmental protection, is a several main difficult problem that faces in the device manufacturing process.The voltage height of high-power chip, principal element are the resistance height, high resistance and extension itself, electrode design and making, and upside-down mounting welding manufacture craft is closely related.Under nominal working conditions, the heat that the resistance height can make LED produce is excessive, so cause the junction temperature of device too high, the light extraction efficiency of device descends, reliability reduces.
Summary of the invention
1, the technical problem that will solve
Technical problem to be solved by this invention provides the preparation method of the alloy bonding LED flip-chip of a kind of proof gold Au, the all complete compliance with environmental protection requirements of technical process and product, make high power LED flip-chip reduce voltage simultaneously, the heat that LED is produced reduces, and improves the reliability of flip-chip.
2, technical scheme
Technical problem to be solved by this invention provides the alloy bonding LED flip-chip of a kind of proof gold Au, and it can effectively improve the heat-sinking capability and the rate of finished products of LED flip-chip, and reduces the voltage of flip-chip; The present invention also will provide a kind of process of making this chip for this reason.
For solving the problems of the technologies described above, high power LED flip-chip of the present invention is made up of separator (passivation layer) of growing between P-N electrode epitaxial wafer, proof gold packed layer, alloy packed layer, the P-N electrode and the silicon substrate that has the reflector;
P-N electrode epitaxial wafer comprises Sapphire Substrate, the N-GaN layer that on Sapphire Substrate, forms, at P-GaN layer that forms on the N-GaN layer and luminescent layer (luminescent layer is between N-GaN layer and P-GaN layer), the metal level that helps the electric current diffusion that forms in P-GaN laminar surface deposition is a transparency conducting layer, by the P-N electrode that P-GaN layer and N-GaN layer are drawn respectively, the separator of between the P-N electrode, growing (passivation layer);
The described silicon substrate that has the reflector is included in the electric isolation layer that forms on the intrinsic semiconductor silicon substrate, forms metallic reflector on this electric isolation layer;
Fill proof gold by pure heating between described P-N electrode epitaxial wafer and the silicon substrate and carry out upside-down mounting welding, bonding power LED flip-chip with other alloy;
Described alloy can be combination of compounds such as Au, Al, Sn, In;
When described P-N electrode epitaxial wafer and silicon substrate bonding, the distance between P-GaN layer and the silicon substrate reflector is 2-15 μ m.
The alloy bonding LED flip-chip process for making of proof gold Au of the present invention comprises the steps:
At first make P-N electrode epitaxial wafer, comprise the steps: on Sapphire Substrate, to adopt ICP (coupling ion etching) or RIE (reactive ion etching) equipment utilization chloride ion and argon ion to carry out dry etching, form P-GaN layer and luminescent layer, and P-GaN layer and luminescent layer and the N-GaN layer below it are formed electrically contact, during etching with photoresist or SiO
2Make mask; The metal level that adopts vacuum electronic beam evaporation formation one deck to help the electric current diffusion on the surface of P-GaN layer is a transparency conducting layer; Adopt magnetron sputtering or electron beam evaporation to form the P-N electrode of drawing respectively by P-GaN layer and N-GaN layer; Between the P-N electrode, adopt the SiO of PECVD (plasma-reinforced chemical vapour deposition) growth one deck 70nm-120nm
2Passivation layer;
Make the silicon substrate that has the reflector then, comprise the steps: to utilize the electric isolation layer of PECVD deposition one deck P-N electrode on the intrinsic semiconductor silicon substrate, this electric isolation layer is SiO
2Or Si
3N
4Insulating barrier, thickness are 50nm-100nm, are the metallic reflector of 200nm-300nm with magnetron sputtering or electron beam evaporation one layer thickness then, and this metallic reflector adopts TiAl (titanium aluminium) or TiAg (titanium silver);
At last, the P-N electrode epitaxial wafer of making is divided into the device of 1000 μ m * 1000 μ m, the silicon substrate in the band reflector made is divided into the device of 1500 μ m * 1500 μ m, both are carried out flip chip bonding and be connected together by filling proof gold and the pure heating bonding of other alloy.
In the alloy bonding LED flip-chip of proof gold Au of the present invention, because upside-down mounting welding, during bonding, employing has the proof gold and the Au of high-heat conductive efficency, Al, Cu, Pb, Sn, combination of compounds alloys such as In are as packing material, can realize the upside-down mounting welding by pure heating, reduce P, distance between N-GaN layer and silicon substrate, distance between P-GaN layer and the silicon substrate reflector is controlled in the little spacing of 2-15 μ m, high thermal conductivity and low resistance make the heat of led chip joint to conduct quickly and to distribute, the stability and the rate of finished products of upside-down mounting welding have been improved, reduce the voltage of LED, improved the heat-sinking capability of high power LED flip-chip, stability, rate of finished products.Therefore, adopt method of the present invention can reduce the voltage of big merit LED flip-chip, optimized heat radiation simultaneously, improved the stability and the rate of finished products of chip.
3, beneficial effect
In a word, this method is carried out upside-down mounting welding, bonding power LED flip-chip by fill proof gold by pure heating between P-N electrode epitaxial wafer and silicon substrate with other alloy, very improve heat-sinking capability, reliability and the rate of finished products of high power LED flip-chip effectively, thereby greatly improved the quality of chip and the performance of device.This method is the highly effective process of making high power LED flip-chip and improving device quality and performance
Description of drawings
The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:
Fig. 1 is institute's invention technology flip chip structure schematic diagram.
Fig. 2 is under different welding temperatures, flip-chip voltage and weld time graph of relation;
Fig. 3 is the rate of finished products of flip-chip;
Fig. 4 is the distribution map of flip-chip voltage;
Embodiment
The alloy bonding LED flip-chip of proof gold Au of the present invention is made up of separator (passivation layer) of growing between P-N electrode epitaxial wafer, proof gold packed layer, alloy packed layer, the P-N electrode and the silicon substrate that has the reflector;
P-N electrode epitaxial wafer comprises Sapphire Substrate, the N-GaN layer that on Sapphire Substrate, forms, at P-GaN layer that forms on the N-GaN layer and luminescent layer (luminescent layer is between N-GaN layer and P-GaN layer), being formed with the metal level that is beneficial to the electric current diffusion in P-GaN laminar surface deposition is transparency conducting layer, by the P-N electrode that P-GaN layer and N-GaN layer are drawn respectively, the separator of between the P-N electrode, growing (passivation layer);
The described silicon substrate that has the reflector is included in the electric isolation layer that forms on the intrinsic semiconductor silicon substrate, forms metallic reflector on this electric isolation layer;
Fill proof gold by pure heating between described P-N electrode epitaxial wafer and the silicon substrate and carry out upside-down mounting welding, bonding power LED flip-chip with other alloy.
For general flip-chip, the back-off welding is by utilization kind of ball machine, selects the gold thread of suitable dimension and suitable kind bulb temperature for use, and the size of control Wire-Bond ball (ultrasonic spun gold ball) then utilizes Die-Bond (upside-down mounting welding) machine ultrasonic wave to weld.BUMP corresponding on several BUMP (gold goal) that weld on the electrode and the silicon substrate welds together by eutectic.The welding procedure complexity, the contact area of gold goal and P, N-GaN layer and silicon substrate limited and be difficult to control, distance between P, N-GaN layer and silicon substrate is bigger, bigger between P-GaN layer silicon substrate, if handle bad, make voltage and the thermal resistance of LED excessive easily, cause the poor stability of LED and rate of finished products low.
As shown in Figure 1, in the alloy bonding LED flip-chip of proof gold Au, because upside-down mounting welding, during bonding, employing has the proof gold and the Au of high-heat conductive efficency, Al, Cu, Pb, Sn, combination of compounds alloys such as In are as packing material, can realize the upside-down mounting welding by pure heating, reduce P, distance between N-GaN layer and silicon substrate, distance between P-GaN layer and the silicon substrate reflector is controlled in the little spacing of 2-15 μ m, high thermal conductivity and low resistance make the heat of led chip to conduct quickly and to distribute, the stability and the rate of finished products of upside-down mounting welding have been improved, reduce the voltage of LED, improved the heat-sinking capability of high power LED flip-chip, stability, rate of finished products.
Below in conjunction with an embodiment high power LED flip-chip process for making of the present invention is described:
For preparing the alloy bonding LED flip-chip of above-mentioned proof gold Au, preparation method of the present invention may further comprise the steps:
At first, utilization MOCVD (metal organic chemical vapor deposition) equipment epitaxial growth GaN based high-power LED structure extension sheet, substrate is sapphire (Al
3O
2).Stroke road of etching N face step and chip size exposes the N-GaN table top, so that make N electrode and weld pad then.N type table top reactive ion etching equipment RIE etching, reacting gas is Cl: Ar=10: 3.
Adopt ICP (coupled plasma etching) or RIE (reactive ion etching) equipment utilization chloride ion and argon ion to carry out dry etching, the P-GaN layer and the luminescent layer that form, and P-GaN layer and luminescent layer and the N-GaN layer below it are formed electrically contact, during etching with photoresist or SiO
2Make mask.
Evaporation one layer thickness is the transparent conductive film ITO of 200nm-300nm on the P-GaN layer afterwards, as transparency conducting layer.
The metallic combination (nickel/gold) of adopting magnetron sputtering or electron beam evaporation difference evaporation to form with Ni/Au by P-GaN layer and N-GaN layer is the P-N electrode and the weld pad of metallic combination.Electrode size is 90 μ m～120 μ m (when P-N electrode epitaxial wafer is of a size of 1000 μ m * 1000 μ m).
Between the P-N electrode, adopt the SiO of PECVD (plasma-enhanced chemical vapor deposition) growth one deck 80nm
2Passivation layer.Use chemico-mechanical polishing (CMP) equipment that sapphire is thinned to 90 μ m～150 μ m by 350 μ m～450 μ m then.
Utilize the electric isolation layer of PECVD (plasma-enhanced chemical vapor deposition) deposition one deck P-N electrode on 2 inches intrinsic semiconductor silicon substrates, this electric isolation layer is SiO
2Or Si
3N
4Insulating barrier, thickness are 50nm-100nm, are the metallic reflector of 200nm-300nm with magnetron sputtering or electron beam evaporation one layer thickness then, and this metallic reflector adopts TiAl (titanium aluminium) or TiAg (titanium silver).
At last, the P-N electrode epitaxial wafer of making is divided into the device of 1000 μ m * 1000 μ m, the silicon substrate in the band reflector made is divided into the device of 1500 μ m * 1500 μ m with cutting machine.The P-N electrode epitaxial wafer that performs electrode is divided into the device of 1000 μ m * 1000 μ m with laser scribing means.Both are carried out flip chip bonding by filling proof gold and the pure heating bonding of other alloy is connected together.
Embodiment one, regulates welding temperature and time.
The described technological parameter that LED wafer and silicon substrate are welded together is as follows:
The heating bonding temperature is controlled at 200 ℃～350 ℃, regulates weld time, and scope is 50ms～250ms.As seen from Figure 2 under the prerequisite of welding temperature parameter constant, the crystal grain V that records by regulating weld time
FThe mutual difference DELTA V of (forward voltage)
FWherein, when welding temperature is 200 ℃, difference DELTA V
FOnly be 0.2V.When welding temperature increases, difference DELTA V
FIncrease, and it is bigger to work as welding temperature, when being 350 ℃, difference DELTA V
FObviously increase with the increase of weld time.
Fig. 3 is the comparison of institute's invention technology flip-chip (filling is arranged) with the rate of finished products of prior art flip-chip (do not have and fill).Scheme as seen thus, the rate of finished products of institute's invention technology flip-chip has improved 2 times with respect to prior art.Fig. 4 is the distribution map of institute's invention technology flip-chip (filling is arranged) with the forward voltage of prior art flip-chip (do not have and fill).The forward voltage of the flip-chip that institute's invention fabrication techniques goes out is distributed in a very narrow scope, and the consistency of the forward voltage of chip is better, has improved 2 times with respect to prior art.Reducing weld time, reducing the welding temperature purpose is the damaged condition that reduces in manufacturing process core intragranular bilge construction, controls the volume resistance of conductor itself well.If do not control volume resistance well, can cause conductor itself to produce a large amount of heats, accelerate the duplet lattice collisions.Can reduce electronics and hole-recombination probability like this, influence the light extraction efficiency and the life-span of core grain.Therefore by regulate weld time, technological parameter such as welding temperature can reduce high-power chip voltage, improves light extraction efficiency and reliability.
Claims (4)
1, the alloy bonding LED flip-chip of proof gold Au is characterised in that: be made up of separator (passivation layer) of growing between P-N electrode epitaxial wafer, proof gold packed layer, alloy packed layer, the P-N electrode and the silicon substrate that has the reflector;
P-N electrode epitaxial wafer comprises Sapphire Substrate, the N-GaN layer that on Sapphire Substrate, forms, at P-GaN layer that forms on the N-GaN layer and luminescent layer (luminescent layer is between N-GaN layer and P-GaN layer), the metal level that helps the electric current diffusion that forms in the deposit of P-GaN laminar surface is a transparency conducting layer, by the P-N electrode that P-GaN layer and N-GaN layer are drawn respectively, the passivation layer of between the P-N electrode, growing;
The described silicon substrate that has the reflector is included in the electric isolation layer that forms on the intrinsic semiconductor silicon substrate, the metallic reflector that forms on this electric isolation layer;
Described P-N electrode epitaxial wafer carries out upside-down mounting welding formation LED flip-chip with the silicon substrate that has the reflector by filling proof gold and the pure heating bonding of other alloy.
2, the preparation method who contains the alloy bonding LED flip-chip of proof gold Au as claimed in claim 1, it is characterized in that the technological parameter that described large scale led chip and silicon substrate weld together: the heating bonding temperature is controlled at 200 ℃～350 ℃, regulate weld time, scope is 50ms～250ms.
3, the preparation method of LED flip-chip as claimed in claim 1 is characterized in that: the packing material between P-N electrode epitaxial wafer and the silicon substrate is proof gold and Au, Al, Cu, Pb, combination of compounds such as Sn, In.
4, the preparation method of LED flip-chip as claimed in claim 1 is characterized in that: when P-N electrode epitaxial wafer and silicon substrate bonding, the distance between P-GaN layer and the silicon substrate reflector is 2～10 μ m.
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| CN102185073A (en) * | 2011-04-01 | 2011-09-14 | 厦门市三安光电科技有限公司 | Flip light-emitting diode and manufacturing method thereof |
| CN102347434A (en) * | 2010-08-03 | 2012-02-08 | 上海蓝光科技有限公司 | Light-emitting diode (LED) chip with flip chip structure and manufacturing method thereof |
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| CN102185073A (en) * | 2011-04-01 | 2011-09-14 | 厦门市三安光电科技有限公司 | Flip light-emitting diode and manufacturing method thereof |
| CN102185073B (en) * | 2011-04-01 | 2012-09-19 | 厦门市三安光电科技有限公司 | Flip light-emitting diode and manufacturing method thereof |
| WO2014032487A1 (en) * | 2012-08-30 | 2014-03-06 | 厦门市三安光电科技有限公司 | Inverted light emitting diode and manufacturing method thereof |
| WO2016011606A1 (en) * | 2014-07-23 | 2016-01-28 | 深圳市国源铭光电科技有限公司 | Manufacturing method for led light source, and batch manufacturing method |
| CN113424315A (en) * | 2019-02-14 | 2021-09-21 | 首尔伟傲世有限公司 | Display light-emitting element transfer method and display device |
| CN112701205A (en) * | 2021-03-23 | 2021-04-23 | 山东元旭光电股份有限公司 | All-inorganic packaging preparation method of deep ultraviolet chip and deep ultraviolet chip |
| CN113422291A (en) * | 2021-06-21 | 2021-09-21 | 常州纵慧芯光半导体科技有限公司 | Laser device and manufacturing method and application thereof |
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Address after: 430000 No. 227, Optics Valley Road, East Lake Development Zone, Hubei, Wuhan, China Patentee after: AQUALITE OPTOELECTRONICS CO., LTD. Address before: 430074 building, No. 18, Huaguang Avenue, Kanto science and Technology Industrial Zone, East Lake District, Hubei, Wuhan, 12 Patentee before: Diyuan Photoelectric Science & Technology Co., Ltd., Wuhan |
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Date of cancellation: 20150430 Granted publication date: 20090610 Pledgee: Bank of Hankou Limited by Share Ltd Optics Valley branch Pledgor: AQUALITE OPTOELECTRONICS CO., LTD. Registration number: 2013990000147 |
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| PM01 | Change of the registration of the contract for pledge of patent right |
Change date: 20150430 Registration number: 2013990000147 Pledgor after: AQUALITE OPTOELECTRONICS CO., LTD. Pledgor before: Diyuan Photoelectric Science & Technology Co., Ltd., Wuhan |
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Granted publication date: 20090610 Termination date: 20150905 |
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