CN100590875C - Polysilicon concatenating diode - Google Patents
Polysilicon concatenating diode Download PDFInfo
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- CN100590875C CN100590875C CN 200810062062 CN200810062062A CN100590875C CN 100590875 C CN100590875 C CN 100590875C CN 200810062062 CN200810062062 CN 200810062062 CN 200810062062 A CN200810062062 A CN 200810062062A CN 100590875 C CN100590875 C CN 100590875C
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- active area
- diode
- diffusion active
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 55
- 229920005591 polysilicon Polymers 0.000 title claims description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 229910052710 silicon Inorganic materials 0.000 abstract description 20
- 239000010703 silicon Substances 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract 8
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 9
- 230000003068 static effect Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
The invention discloses a multi-crystal silicon cascade diode which includes a P substrate. N traps are equipped at two ends of the P substrate, two deep N traps which bottom are connected into a whole are arranged in each N trap, a P trap are equipped between the two deep N traps, N+ diffusion active regions are respectively arranged on each deep N trap, a P+ diffusion active region and a N+ diffusion active region are arranged on the P trap, all of the diffusion active regions are insulated by a shallow groove insulated layer, a plurality of P+ intrinsic multi-crystal silicon and a pluralityof N+ intrinsic multi-crystal silicon which have same quantity with the P+ intrinsic multi-crystal silicon are equipped on the shallow groove insulated layer between the two N traps, the P+ intrinsicmulti-crystal silicon and the N+ intrinsic multi-crystal silicon are distributed at an interval and connected by a intrinsic multi-crystal silicon. In the multi-crystal silicon cascade diode, the P+diffusion active regions on each of the P traps and the N+ diffusion active regions between the two deep N traps are connected which are equivalent to that a emitter electrode and a base electrode ina parasitical triode of the cascade diode are connected, thereby inhibiting darlington effect.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate in particular to a kind of polysilicon concatenating diode.
Background technology
Static discharge (ESD, Electron Static Discharge) is when the pin suspension joint of an integrated circuit, and a large amount of electrostatic charges pour into the instantaneous process of integrated circuit, the about 100ns consuming time of whole process from outside to inside.When the static discharge of integrated circuit, can produce the high pressure of hundreds if not thousands of volts, with the gate oxide breakdown of input stage in the integrated circuit.Along with the progress of integrated circuit technology, the characteristic size of metal-oxide-semiconductor is more and more littler, and the thickness of gate oxide is also more and more thinner, under this trend, use high performance ESD protective device release electrostatic charge with the protection grid oxic horizon seem very important.
The model of ESD phenomenon mainly contains four kinds: human body discharging model (HBM), mechanical discharging model (MM), device charge model (CDM) and electric field induction model (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharging model, the test of mechanical discharging model and device charge model.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.Resist the purpose that static hits in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested, such as diode, and the NMOS of grounded-grid pipe; generally acknowledge that wherein the reasonable protective device of effect is controllable silicon (SCR, SiliconControlled Rectifier).But the trigger voltage of traditional silicon-controlled electrostatic discharge (ESD) protective device is very high.Along with dwindling of the characteristic size of device, the operating voltage of circuit also constantly descends, for the trigger voltage with the silicon-controlled electrostatic discharge (ESD) protective device is reduced in the considerable magnitude of voltage, people have proposed the silicon-controlled electrostatic discharge (ESD) protective device that a kind of utilization triggers based on concatenating diode.
Fig. 1 is the three kind connectivity scenarios of concatenating diode in the silicon-controlled electrostatic discharge (ESD) protective device.Concatenating diode silicon-controlled electrostatic discharge (ESD) protective device is the grid that after utilizing the low-voltage of concatenating diode to trigger electric current is poured into silicon-controlled device, makes the silicon-controlled electrostatic discharge (ESD) protective device open fast.But the difficult point of concatenating diode silicon-controlled electrostatic discharge (ESD) protective device is the design of diode in the CMOS technology, because Darlington effect (Darlington Effect) easily causes the direct current electric leakage of concatenating diode very big.
As shown in Figure 2, a kind of traditional concatenating diode, comprise P type substrate, P type substrate is provided with 4 N traps, each trap N is provided with P+ diffusion active area and N+ diffusion active area, all spread between active areas all by shallow groove isolation layer (STI, Shallow Trench Isolation) isolates (M.D.Ker, Y.W.Hsiao, and W.L.Wu, " ESD-Protection Design With ExtraLow-Leakage-Current Diode String for RF Circuits in SiGe BiCMOSProcess; " IEEE Transactions on Device and Materials Reliability, vol.6, pp.517-527,2006.).
The most submarginal P+ diffusion active area connects electrical anode (Anode) on this concatenating diode, and the most submarginal N+ diffusion active area connects electrical cathode (Cathode), but the electric leakage of the direct current of this concatenating diode is bigger, has limited its range of application.
Summary of the invention
The invention provides the little polysilicon concatenating diode of a kind of direct current electric leakage.
A kind of polysilicon concatenating diode comprises the P substrate, and P substrate one end is provided with the first dark N trap and the second dark N trap that a N trap and bottom fuse, and is provided with a P trap between the first dark N trap and the second dark N trap, and the side is surrounded by a N trap; The P substrate other end is provided with the 3rd dark N trap and the 4th dark N trap that the 2nd N trap and bottom fuse, and is provided with the 2nd P trap between the 3rd dark N trap and the 4th dark N trap, and the side is surrounded by the 2nd N trap; The first dark N trap, the second dark N trap, the 3rd dark N trap, be respectively equipped with N+ diffusion active area on the 4th dark N trap, the 2nd N+ spreads active area, the 3rd N+ spreads active area, the 4th N+ spreads active area, ecto-entad, the one P trap is provided with P+ diffusion active area and the 5th N+ diffusion active area, the 2nd P trap is provided with the 6th N+ diffusion active area and the 2nd P+ diffusion active area, all diffusion active areas are all isolated by shallow groove isolation layer, be covered with some P+ doped polycrystalline silicon and the N+ doped polycrystalline silicon identical with P+ doped polycrystalline silicon quantity on the shallow groove isolation layer between the one N trap and the 2nd N trap, the P+ doped polycrystalline silicon distributes with N+ doped polycrystalline silicon space and is connected by intrinsic polysilicon.
When above-mentioned concatenating diode was applied in the controllable silicon, its circuit connecting mode was as follows:
P+ on each P trap diffusion active area with and two dark N traps of both sides on N+ diffusion active area connect by lead, in the P+ doped polycrystalline silicon or N+ doped polycrystalline silicon on the shallow groove isolation layer between the one N trap and the 2nd N trap, except that the P+ doped polycrystalline silicon or N+ doped polycrystalline silicon of end, two ends, one deck P+ doped polycrystalline silicon is connected by lead with one deck N+ doped polycrystalline silicon in remaining P+ doped polycrystalline silicon or the N+ doped polycrystalline silicon, P+ diffusion active area on the one P trap connects electrical anode, the 5th N+ diffusion active area connects the P+ doped polycrystalline silicon that is positioned at end on the shallow groove isolation layer between a N trap and the 2nd N trap, the 6th N+ on the 2nd P trap diffusion active area connects electrical cathode, and the 2nd P+ diffusion active area connects the N+ doped polycrystalline silicon that is positioned at end on the shallow groove isolation layer between a N trap and the 2nd N trap.
P+ diffusion active area in the said structure on the P trap and N+ diffusion active area are equivalent to the anode and the negative electrode of diode, P+ doped polycrystalline silicon and N+ doped polycrystalline silicon are equivalent to a diode, as can be seen, said structure is equivalent to the concatenating diode be made up of at least 3 diodes polyphone.
P+ diffusion active area on each P trap of polysilicon concatenating diode of the present invention and the N+ diffusion active area on the dark N trap in both sides are connected, the emitter that promptly is equivalent to parasitic triode in the above-mentioned cascade diode links to each other with base stage, make the Darlington effect be inhibited, and electric current flows through from polysilicon diode, thereby reduced substrate current greatly, reached the little and low double effects of trigger voltage of direct current electric leakage.
Description of drawings
Fig. 1 is applied to the circuit theory diagrams of three kinds of connected modes in the controllable silicon for concatenating diode;
Fig. 2 is the cross-sectional view of existing cascade diode;
Fig. 3 is the cross-sectional view of polysilicon concatenating diode of the present invention;
Fig. 4 is the vertical view of polysilicon concatenating diode shown in Figure 3.
Embodiment
As shown in the figure, a kind of polysilicon concatenating diode comprises P substrate 1, and P substrate 1 one ends are provided with the first dark N trap 51 and the second dark N trap 52 that a N trap 21 and bottom fuse, be provided with a P trap 31 between the first dark N trap 51 and the second dark N trap 52, the side is surrounded by a N trap 21; P substrate 1 other end is provided with between the 3rd dark N trap 53 that the 2nd N trap 22 and bottom fuse and the 4th dark N trap 54, the three dark N traps 53 and the 4th dark N trap 54 and is provided with the 2nd P trap 32, and the side is surrounded by the 2nd N trap 22.
Be respectively equipped with N+ diffusion active area 81, the 2nd N+ diffusion active area 82, the 3rd N+ diffusion active area 83, the 4th N+ on first dark N trap 51, second dark N trap the 52, the 3rd dark N trap the 53, the 4th dark N trap 54 and spread active area 84, ecto-entad, the one P trap 31 is provided with P+ diffusion active area 61 and the 5th N+ diffusion active area 85, the 2nd P trap 32 is provided with the 6th N+ and spreads 86 active areas and the 2nd P+ diffusion active area 62, and all diffusion active areas are all isolated by shallow groove isolation layer 4.
Be covered with 2 P+ doped polycrystalline silicon 91 and 2 N+ doped polycrystalline silicon 92 on the shallow groove isolation layer 4 between the one N trap 21 and the 2nd N trap 22, P+ doped polycrystalline silicon 91 distributes with N+ doped polycrystalline silicon 92 spaces and is connected by intrinsic polysilicon 9.
N trap on the above-mentioned polysilicon diode, P trap, dark N trap, P+ diffusion active area and N+ diffusion active area obtain by carry out the ion injection on the P substrate.
P+ doped polycrystalline silicon 91 also is to obtain by the ion injection on intrinsic polysilicon 9 with N+ doped polycrystalline silicon 92.
When above-mentioned polysilicon concatenating diode was applied to controllable silicon, circuit connecting mode was as follows:
P+ on each P trap diffusion active area with and two dark N traps of both sides on N+ diffusion active area connect by lead, in the P+ doped polycrystalline silicon 91 or N+ doped polycrystalline silicon 92 on the shallow groove isolation layer 4 between the one N trap 21 and the 2nd N trap 22, except that the P+ doped polycrystalline silicon 91 or N+ doped polycrystalline silicon 92 of end, two ends, one deck P+ doped polycrystalline silicon 91 and one deck N+ doped polycrystalline silicon 92 are connected by lead in remaining P+ doped polycrystalline silicon 91 or the N+ doped polycrystalline silicon 92.
P+ diffusion active area 61 on the one P trap 21 connects electrical anode, the 5th N+ diffusion active area 85 connects shallow trench isolation between N traps 21 and the 2nd N trap 22 is positioned at end on 4 layers P+ doped polycrystalline silicon 91, the 6th N+ on the 2nd P trap 22 diffusion active area 86 connects electrical cathode, is positioned at the N+ doped polycrystalline silicon 92 of end on the shallow groove isolation layer 4 that the 2nd P+ diffusion active area 62 connects between N traps 21 and the 2nd N trap 22.
Claims (1)
1. polysilicon concatenating diode, comprise P substrate (1), it is characterized in that: P substrate (1) one end is provided with the first dark N trap (51) and the second dark N trap (52) that a N trap (21) and bottom fuse, be provided with a P trap (31) between the first dark N trap (51) and the second dark N trap (52), the side is surrounded by a N trap (21); P substrate (1) other end is provided with the 3rd dark N trap (53) and the 4th dark N trap (54) that the 2nd N trap (22) and bottom fuse, and is provided with the 2nd P trap (32) between the 3rd dark N trap (53) and the 4th dark N trap (54), and the side is surrounded by the 2nd N trap (22); The first dark N trap (51), the second dark N trap (52), the 3rd dark N trap (53), be respectively equipped with N+ diffusion active area (81) on the 4th dark N trap (54), the 2nd N+ spreads active area (82), the 3rd N+ spreads active area (83), the 4th N+ spreads active area (84), ecto-entad, the one P trap (31) is provided with P+ diffusion active area (61) and the 5th N+ diffusion active area (85), the 2nd P trap (32) is provided with the 6th N+ diffusion active area (86) and the 2nd P+ diffusion active area (62), all diffusion active areas are all isolated by shallow groove isolation layer (4), be covered with some P+ doped polycrystalline silicon (91) and the N+ doped polycrystalline silicon (92) identical with P+ doped polycrystalline silicon (91) quantity on the shallow groove isolation layer (4) between the one N trap (21) and the 2nd N trap (22), P+ doped polycrystalline silicon (91) distributes with N+ doped polycrystalline silicon (92) space and is connected by intrinsic polysilicon (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810062062 CN100590875C (en) | 2008-05-28 | 2008-05-28 | Polysilicon concatenating diode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810062062 CN100590875C (en) | 2008-05-28 | 2008-05-28 | Polysilicon concatenating diode |
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| CN101281910A CN101281910A (en) | 2008-10-08 |
| CN100590875C true CN100590875C (en) | 2010-02-17 |
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| CN 200810062062 Expired - Fee Related CN100590875C (en) | 2008-05-28 | 2008-05-28 | Polysilicon concatenating diode |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5546191B2 (en) * | 2009-09-25 | 2014-07-09 | セイコーインスツル株式会社 | Semiconductor device |
| CN102623453B (en) * | 2011-01-27 | 2014-10-29 | 无锡华润华晶微电子有限公司 | Power device, preparation method and energy-saving electronic lighting circuit using the same |
| CN102254911B (en) * | 2011-07-13 | 2013-04-17 | 浙江大学 | Controlled silicon device provided with secondary conductive path and triggered with help of diodes |
| CN102543998A (en) * | 2012-02-20 | 2012-07-04 | 中国科学院微电子研究所 | Polycrystalline silicon series diode string and manufacturing method thereof |
| CN102544068B (en) * | 2012-03-09 | 2014-01-15 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes |
| CN102593125A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Groove type MOS (metal oxide semiconductor) electrostatic discharge structure and integrated circuit |
| CN103972172B (en) * | 2013-02-01 | 2016-10-05 | 厦门博佳琴电子科技有限公司 | A kind of diode selecting element arrays structure and manufacture method |
| CN105702674B (en) * | 2016-03-18 | 2019-01-04 | 江苏艾伦摩尔微电子科技有限公司 | A kind of electrostatic discharge protective device |
| CN111816650B (en) * | 2019-04-12 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection structure and forming method thereof |
| CN111725305B (en) * | 2020-07-31 | 2022-08-16 | 华虹半导体(无锡)有限公司 | Semiconductor device and method for manufacturing the same |
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