BR102015016843A2 - implantable medical device - Google Patents

Abstract

"Implantable medical device" implantable medical device having a clock generation circuit configured to generate a clock signal at a clock generation circuit frequency and having a clock period. A self-timer central processing unit is configured to process computing instructions and generates a complete processing signal upon completion of processing each of the computing instructions. a self-timer memory is operatively coupled to the central processing unit and is configured to store information for the implantable medical device and provides a full access signal upon completion of at least one of the read operation and the store operation. the clock signal, the complete processing signal from the central processing unit, the full memory access signal are used to synchronize data transmission within the implantable medical device. a dimming state machine is configured to develop timing signals independent of the self-timer central processing unit to coordinate a sensing circuit and an output circuit.

Description

“IMPLANTABLE MEDICAL DEVICE” FIELD

The present invention relates generally to implantable medical devices, and more particularly to implantable medical devices having multiple timing devices.

GROUNDS

Most implantable medical devices are complex electronic devices typically containing a microprocessor to control operations. The microprocessor is usually coupled with at least one memory or memory unit for storing and retrieving data and information related to the operation of implantable physicians and additional components such as detection circuits or modules and output circuits or modules.

The various functions of implanted medical devices are typically performed in a step-by-step manner under control of a clock circuit to generate a clock signal that the implantable components use for time and sequence their activities. Such watches are well known in the art. The regular clock signal, for example generated by an oscillator is generally sought to be quite regular ensuring the stable and predictable operating characteristics of the implantable medical device. A stable oscillator is often generated and controlled by a crystal creating a crystal oscillator.

In order to perform a general operation within the implantable medical device, for example in a store or a reading from memory, several different steps typically have to be performed in sequence. In order to perform the general operation within a desired time period, it may be necessary to have a clock signal that is much faster than the desired time period since several or many individual steps need to be performed in sequence. . Thus, it is often desirable to have a clock signal that is not only stable and consistent but also relatively fast compared to the overall performance of the implantable medical device.

However, relatively fast, high precision crystal oscillators are not only relatively expensive, but, more importantly, consume a relatively larger amount of power. Higher power consumption not only generates more heat, but, more importantly, shortens battery life because most implantable medical devices are battery powered. Shorter battery life either means more frequent recharging or more frequent explanation for battery replacement.

SUMMARY

Instead of timing all or most of the components of a highly stable, relatively fast crystal oscillator, the present invention utilizes a single, relatively inexpensive, low frequency, low power oscillator. This single low power oscillator watches and synchronizes the central processing unit. Other units or modules within the implantable medical device are usually synchronized with this low frequency oscillator, but then maintain individual operations through self-timing. Thus, for example, once a store stops or reads from the memory module the low frequency oscillator timing starts, the memory then uses self-timing to generate the sequence and individual time steps required to carry the store to or read from operation. Likewise, the implantable medical output device device may be a regulating motor that can generate therapeutic output signals autonomously through a multitude of self-timed steps. As another example, a telemetry unit may communicate with an external device under local control without being controlled step by step by the low frequency oscillator. In one embodiment, the central processing unit is intended to complete single instruction processing within one or two low frequency clock periods, while other components of the implantable medical device cooperate by performing detailed tasks autonomously.

[007] The combination of a single, relatively low power, low frequency oscillator and one or more components of the implantable medical device being self-timed allows for a low cost and low implantable power consumption yet a high performance and versatility.

In one embodiment, an implantable medical device has a clock generation circuit configured to generate a clock signal with a clock generation circuit frequency and a clock period. A central self-timer processing unit is configured to process computation instructions and generates a complete processing signal upon completion of the processing of each computation instruction. A self-timer memory is operatively coupled to the central processing unit and is configured to store information for the implantable medical device and provides a full access signal upon completion of at least one of the read operation and the store operation. The clock signal, the full processing signal from the central processing unit, the full memory access signal are used to synchronize data transmission within the implantable medical device. A sensing circuit is configured to detect cardiac events for the operation of the implantable medical device. An output circuit is configured to generate output signals dependent, at least in part, on processing computing instructions. A regulating state machine is configured to develop timing signals independent of the self-timer central processing unit to coordinate the sensing circuit and the implantable medical output device circuit.

In one embodiment, the central self-timer processing unit processes each of the computing instructions within a single clock period of the clock generation circuit.

In one embodiment, the central processing unit processes each of the computing instructions within no more than three of the clock periods of the clock generation circuit.

In one embodiment, the memory performs a read operation or a storage operation within a memory period and wherein the clock period of the clock generation circuit is greater than the memory period.

In one embodiment, the dimming state machine is configured by written data, for example, definition signals, from the central processing unit.

In one embodiment, each of the computing instructions is processed by the central processing unit that begins with a start signal, for example, a clock transition signal from the clock generation circuit.

In one embodiment, the regulating state machine controls the output circuit to provide the output signals without interaction with the central processing unit.

In one embodiment, the dimming state machine is updated by the central processing unit to change a configuration of the output signals.

In one embodiment, a delay element is operably coupled to the clock generation circuit and provides a delayed version of the clock signal that is used in conjunction with the clock signal, with the signal processed from the central clock unit. processing, with the full access signal from memory to synchronize data transmission within the implantable medical device.

In one embodiment, the clock generation circuit is a low frequency oscillator.

In one embodiment, the implantable medical device is a cardiac pacemaker, and wherein the signals comprise cardiac regulation output signals.

In one embodiment, a self-timer telemetry module is configured to communicate externally to the implantable medical device via telemetry signals.

In one embodiment, the central processing unit and the regulating state machine operated in parallel.

In one embodiment, the clock generation circuit is configured to generate a single frequency clock signal having the clock generation circuit and having a clock period.

FIGURES

Figure 1 is a general block diagram of an implantable medical device of the present invention;

Figure 2 is a block diagram illustrating how the clock divider and a synchronization circuit generate delayed versions of the master clock signal;

Figure 3 is a detailed block diagram of the implantable medical device setting state machine of Figure 1;

Figure 4 is a detailed block diagram of the control block of the implantable medical device central processing unit of Figure 1;

[0026] Figure 5 is a timing diagram illustrating events that occur within a single master clock cycle for a general read / write and calculation instruction;

[0027] Figure 6 is a detailed diagram of signal timing that occurs during the timing diagram illustrated in Figure 5;

Figure 7 is a timing diagram illustrating events that occur within a single master clock cycle for storage from a register for instruction RAM;

Figure 8 is a timing diagram illustrating events occurring within two master clock cycles for an instruction read from one RAM location and stored to another RAM location;

Figure 9 is a simplified view of one embodiment of the implantable medical device; and Figure 10 shows a connector module and a hermetically sealed implantable medical device enclosure located near the human or mammalian heart.

DESCRIPTION

The implantable medical device architecture 8 is enabled by a single low-cost, low-frequency, low-power oscillator that synchronizes all signals, timing, and functions of the implantable medical device, for example, a pacemaker. single or multi-camera. A combination of self-timer asynchronous circuits and low power delay elements can perform multiple tasks in parallel and in series within a single period of the low power oscillator clock signal.

Figure 1 is a block diagram of the implantable medical device 8 driven by the single master clock 10 and a clock divider and a synchronization circuit 11, collectively clock circuits 10 and 11, which generate or coordinate the timing and signals. 13 for other implantable medical device components 8. Central processing unit 14 has timing steps initiated by clock signal 12 of master clock 10, but then performs several steps to complete processing of an instruction and to perform other tasks. Similarly, memory 16 operatively coupled to central processing unit 14 via bus 15 also has steps initiated by clock signal 12 of timing master clock 10, but then performs several steps to perform operations storage and reading and perform other tasks. Clock circuits 10 and 12 also start and synchronize regulating state machine 20, a self-timer state machine, which in turn provides control information for module 22 and output module 24. Sensing 22 receives external signals, for example electrical signals from the heart, to which implantable medical device 08 can respond. Output module 24, for example, a therapeutic regulation signal module, provides a therapeutic output to a patient, for example, heart regulation signals. The sensing module 22 and the output module 24 are functionally coupled to other components of the implantable medical device 8 via bus 18. The telemetry module 26, also operably coupled to bus 18, provides wireless communication to and from from external devices such as doctors or patient programmers.

In one embodiment, master clock 10 uses a crystal to generate a single low frequency clock signal 12. Other well known and simple low frequency clock signals may also be used. Central processing unit 14 uses self-timer circuits that allow central processing unit 14 to initiate and complete instruction processing within one or two periods of low master clock frequency 10. Sub-components in a central processing unit 14 provide event completion signals to indicate that the individual task such as sub-component processing has been completed. The clock splitter and circuit synchronization 11 is used to generate delayed versions of the clock signal 12, which has a period of 30.5 microseconds, and to capture and synchronize data transmission within the implantable medical device 8 and between sub-components of central processing unit 14, between central processing unit 14 and memory 14 and between central processing unit 14 and sensing module 22, output module 24 and telemetry module 26. Memory 16 provides ready data signals 17 indicating that memory access is complete and data is available in the case of an operation read, or that memory storage is complete and memory 16 is available for another operation. Regulating state machine 20 receives control or configuration information from central processing unit 14 and then independently generates timing signals to coordinate sensing with sensing module 22 and regulating with output module 24. The state machine regulator 20 can perform basic output therapeutic functions such as regulating without interaction with central processing unit 14. Being alone, regulating state machine 20 can provide specific regulation and autonomously sensing settings until updated by the unit processing center 14 with updated settings or modes of operation.

Figure 2 is a block diagram illustrating how the clock divider and a synchronization circuit 11 generate delayed versions of clock signal 12. Both clock signal edges 12 are delayed by delay element 4. Signal delayed clock signal is used to generate additional clock synchronization edges within device 8. Clock divider block 6 splits clock signal 12 to generate low frequency clock signals also used on device 8. Typical split clock signals have a period of eight times, sixteen times, thirty-two times, one hundred and twenty-eight times, two hundred and fifty-six times and five hundred and twelve times of clock signal 12. These slower clock signals are used in device 8 which runs at a slower pace than clock signal 12. Some circuits within device 8 use several slow clocks in addition to clock signal 12. transmitted and divided, in addition to the original clock signal 12, collectively represent the timing and synchronization of signals 13.

To illustrate how components of implantable medical device 08 can operate on a self-timer basis when being synchronized by master clock 10, reference may be made to Figure 3 illustrating a state-of-the-machine state block diagram 20. A regulating state machine 20 operates almost independently of central processing unit 14 and can, in fact, operate while central processing unit 14 is in a power off or power save mode. Basic regulation formats are programmed in programmed logic matrix 32, while specific regulation modes and associated parameters are downloaded from central processing unit 14. Programmable logic matrix 32 controls the internal operation of regulation state machine 20 Sensing module 30, central processing module 14, if available, and programmable logic matrix inputs 32 are used to generate output control signals 56 and 58. The programmed medical information module is loaded from the control unit. central processing 14 and mode information is used for determining the sequence of operations performed by matrix logic 32. Programmed timing sequences are generated when programmable logic matrix output 32 is decoded to decode the timer and clock multiplexer block 34. Timers 36, 38, 40, 42, 44 and 46 help the sequence of the regulating state machine 20 from state to state. Timeout / timeout counter 48 signals feed the programmable logic matrix 32, where they are used to control the state sequence and produce suitable output control signals. Self-timer synchronization of dimming state machine 20 with other components within implantable memory device 8, such as central processing unit 14, is performed with event completion signals indicating that dimming state machine 20 has completed a task. assigned and is ready for an additional task or ready to accept the additional input. Memory 50 stores configuration information for set state machine 32.

Interrupts are generated by regulation state machine 32 for specific event timing and sequencing that can be used by central processing unit 14 to monitor regulation operation and interact with output module 24. Output 28 also generates interrupt requests to telemetry module 26, which can be used to transmit telemetry information in the event of specific events.

The power at reset 52 is active during power under the condition. Logical marker block 54 is used to communicate with telemetry module 26. Atrial regulation signal 56 and ventricular regulation signal 58 communicate with output module 28.

A central processing unit control unit block 14 is illustrated in Figure 4 is exemplary of self-timing other components of implantable medical device 8, such as memory 16 and regulating state machine 20, and is presented here to illustrate as such other components of the self-timer exercise with respect to master clock 10.

The timing control between master clock 10 and the various self-timer components of the implantable medical device 8 can be illustrated by the functional block diagram of Figure 4, which performs time and management control for the central processing unit. 14. The read-only memory 16 operation code parts are available via bus 15 and captured in the operation code lock 60. The locked operation codes are directed to instruction decoding matrix 62, a data matrix. programmable logic, where the operation code is decoded. Instruction decoding matrix 62 is divided into two blocks, AND 64 matrix and OR 64 matrix. AND 64 matrix uses the locked operation codes and condition register code flags 68, as well as state information from the lock state 70 to determine three things: (1) the instruction corresponding to the operation code; (2) the type of random access memory addressing or input / output addressing; and (3) whether or not a branch condition has been met. Or matrix 66 uses output 64 from matrix 64 and to generate control signals 74 (which can be closed at seal control 78) to execute the instruction that is sent to the arithmetic and logic unit of central processing unit 14 (not shown). ) and the address circuits unit to memory 16 where the instruction is performed. Matrix OR 66 determines whether the instruction requires one cycle, two cycles, or three cycles, etc. of master clock signal 12 and generates an event completion signal that tells control logic that the decoding task is complete.

The AND matrix and OR matrix 66 also send signal 80 to the next state decode block 82 to determine the next state. The state decode block also receives interrupt block information 84 which is central processing unit 14 of the internal interrupt mechanism which is controlled to allow only one central processing unit interrupt 14 at a time.

[0042] Figure 5 shows the generic timing that could occur during any of the master clock 12 signal cycle of master clock 10. A full cycle of a master clock signal period 12 is illustrated. During the single cycle, the following operations are obtained: a read-only memory read operation 410; instruction / control decoding 412 (as described above); or generating random access memory address or reading log data 414; or reading random access memory or writing random access memory 416; operation of arithmetic logic unit 418; and locking of the resulting data 420. Thus, it can be seen that many individual operations are performed within a single cycle of master clock signal 12. A complete period of master clock signal 12 is considered a single central processing unit cycle.

[0043] Figure 6 illustrates timing signals and events in a typical instruction executed by central processing unit 14. At the positive edge of master clock signal 12, the logic control block in Figure 4 generates an RDROM signal 510, which starts accessing a read-only memory (ROM) and thus beginning decoding PLA 516 preload cycle instructions in the AND 64 array. Memory 16 responds some time later with an event termination signal (the edge ROMDRDS), namely full access signal 512, indicating that read access is complete. Logical control block 76 responds with data validation signal (DS) 514, which requests memory 16 to place the accessed data on bus 18 and has low ROMDRDS, meaning that the data is valid. This completes the reading of ROM event 410 shown in Figure 5.

Subsequently, the AND64 matrix is taken from preload 516 as long as valid data is available on input to the AND 64 matrix in operation code lock 60. The instruction type, addressing mode and branch decisions are decoded and the corresponding control signals are generated. This step completes the INSTR / CONTROL DECODING step 412 in Figure 5 and is represented here in Figure 6 with PLA OUT 518 being elevated. The final event in the first half of master clock cycle 12 is random access memory (RAM) or input / output (I / O) address generation. This is done as control signals of the AND 64 matrix ripple through the OR 66 matrix and address unit blocks. RAM address (RAMADR) 520 is still valid. At the negative edge of master clock signal 12, logic control block 76 generates a RAM read signal (RDRAM) 522 or that begins read access from RAM 416 (Figure 5). In one embodiment, RAM read / write (or I / O access for some instructions) is the first event in the second half of the master clock signal cycle 12 for cycles that require a read or write to RAM. Memory (RAM) 16 responds some time later with a full access signal, the rising edge of RAMIODR 524 and the later RAM data is valid for completing the RAM / I / O reading or writing to RAM / I / O 416 in Figure 5

The event completion signal RAMIODR 524 is used by logic control 76 to start the OR 66 array of operation 418 indicated by the ALUON 526 signal being raised. The ALUON 526 signal allows the arithmetic logic unit 62 to process data from memory 16 or input / output. The ALUOUT 526 signal means that data from arithmetic logic unit 62 is ready to be cached.

The rising edge of the master clock signal 12 as it begins its next cycle is used to lock data from arithmetic logic unit 62. Data locking completes data lock step 420 in Figure 5 and is represented in Figure 6 by an AR 530 signal being raised while the first event of the next cycle of master clock signal 12 begins. Because the result is locked to a target register, for example, ALU, the program counter is updated and locked.

[0047] Figure 7 shows the specific events for an instruction that moves data from one register to RAM 16 or register to I / O. This type of instruction completes a master clock signal cycle 12. The first half of the master clock signal cycle 12 is the same as the first half illustrated in Figure 5, that is a read-only memory read operation 410; instruction / control decoding 412; or random access memory address generation or log data read 414. In the second half of master clock cycle 10, either random access read memory or random access write memory 416 is executed. The program counter is incremented 422 and data is locked to either RAM or I / O 420.

Figure 8 is illustrative of instructions involving two master clock signal cycles 12, in this case an instruction that moves data formation from RAM to RAM or from I / O to I / O. The first loop 710 is similar to the steps involved in the specification illustrated in Figure 5, that is a read-only memory read operation 410; instruction / control decoding 412; random access memory address generation (since data need not be read from the registry); random access read memory 424 (the read option from step 416); arithmetic logic operation unit 418; lock the resulting data 420 into a temporary support register and increment program counter 422. To move the data back to RAM, a second cycle 712 of master clock signal 12 is used. As in the first cycle 710, instruction / control decoding 412 is processed. Read-only memory read operation 410 and random access memory address generation 414 need not occur since in loop 712, data is not being read from memory 16. In the second half of second loop 712, The temporary media register data is written 416 to RAM or I / O. The program counter was incremented at the end of the first cycle 710 and need not be incremented at the end of the second cycle 712 as it involves two cycles of master clock signal instructions 12.

With the hardware block diagrams of Figure 1, Figure 2, Figure 3 and Figure 4 illustrate how the master clock synchronizes 10 self-timer blocks 14, 16 and 20 and the generation of timing signals and Synchronization 13 and the detailed timing diagrams of Figure 5, Figure 6, Figure 7, and Figure 8 illustrate how each implantable medical device block 8 is self-timing using event completion signals synchronized by the master clock signal 12. A complete understanding of implantable medical device operation can be achieved.

Figure 9 is a simplified view of an implantable medical device embodiment ("IMD") 10 in which embodiments of the present invention are implemented. The IMD 10 shown in Figure 9 is a pacemaker comprising at least one regulating and sensing conductor 116 and 118 connected to the hermetically sealed housing 114 and implanted close to the human or mammalian heart 108. The regulating conductors and Detection 116 and 118 senses the electrical signals in response to heart depolarization and repolarization 108, and additionally provides regulating impulses to cause depolarization of cardiac tissue in the vicinity of the distal edges thereof. Leads 116 and 118 may have, for example, unipolar or bipolar electrodes disposed thereon, as is well known in the art. Examples of IMD 10 include implantable cardiac pacemakers described in US Patent No. 5,158,078 to Bennett et al., Or US Patent No. 5,312,453 to Shelton et al., Or US Patent No. 5,144,949 to Olson

Figure 10 shows a connector module 112 and a hermetically sealed IMD 10 housing 114 located near the human or mammalian heart 108. Atrial and ventricular regulating conduits 116 and 118 extend from connector header module 112. to the right atrium and ventricle of the heart 108, respectively. The atrial electrodes 120 and 121 disposed at the distal edge of the atrial regulating conductor 116 are located in the right atrium. Ventricular electrodes 128 and 129 at the distal edge of the ventricular regulation lead 118 are located in the right ventricle.

Accordingly, embodiments of the claimed invention are described. One skilled in the art will appreciate that the present invention may be practiced with other than the disclosed embodiments. The described embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the following claims.

Claims (14)

An implantable medical device, characterized in that it comprises: a clock generation circuit configured to generate a clock signal having a clock generation circuit frequency and having a clock period; a self-timer central processing unit configured to process the computing instructions, said central processing unit generating a complete processing signal upon completion of processing each of said computing instructions; a self-timer memory operatively coupled to said central processing unit and configured to store the information for said implantable medical device and using a read operation and a store operation, said memory providing a full access signal upon completion of at least one of said read operations and said store operation; said clock signal, said full processing signal from said central processing unit, said full signal access from said memory being used to synchronize data transmission within said implantable medical device; a sensing circuit configured to detect cardiac events for the operation of said implantable medical device; an output circuit configured to generate output signals dependent, at least in part, on said processing of said computing processing instructions; and a dimming state machine configured to develop timing signals independent of said self-timer central processing unit to coordinate said sensing circuit and said output circuit of said implantable medical device. Implantable medical device according to claim 1, characterized in that said self-timer central processing unit processes each of said computing instructions within a single clock period of said clock generation circuit. Implantable medical device according to claim 1, characterized in that said central processing unit processes each of said computing instructions within no more than three of said clock periods of said clock generation circuit. . Implantable medical device according to claim 2, characterized in that said memory performs a read operation or a storage operation within a memory period and wherein said clock period of said memory generation circuit clock is longer than said memory period. Implantable medical device according to claim 4, characterized in that said regulating state machine is configured by defining signals from said central processing unit. Implantable medical device according to claim 4, characterized in that each of said computing instructions being processed by said central processing unit begins with a start signal from said clock generating circuit. Implantable medical device according to claim 1, characterized in that said regulating state machine control said output circuit for providing said output signal without interaction with said central processing unit. Implantable medical device according to claim 7, characterized in that said regulating state machine is updated by said central processing unit to change a configuration of said output signals. Implantable medical device according to claim 1, characterized in that it further comprises a delay element operably coupled to said clock generating circuit providing a delayed version of said clock signal and wherein said delayed version of said clock signal. clock signal is used in conjunction with said clock signal, said processed signal from said central processing unit, said full signal access from said memory to synchronize data transmission within said implantable medical device . Implantable medical device according to claim 9, characterized in that said clock generating circuit includes a low frequency oscillator. Implantable medical device according to claim 9, characterized in that said implantable medical device comprises a cardiac pacemaker and wherein said output signals comprise cardiac regulation signals. Implantable medical device according to claim 1, characterized in that it further comprises a self-timer telemetry module configured for external communication of said implantable medical device via telemetry signals. Implantable medical device according to claim 1, characterized in that said central processing unit and said regulating state machine operate in parallel. Implantable medical device according to claim 1, characterized in that said clock generation circuit is configured to generate a single clock signal having said clock generation circuit frequency and having said clock period. .