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  • University of Chinese Academy of Sciences
  • Beijing, China
  • 17:46 (UTC +08:00)

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Showing results

rfuzz: coverage-directed fuzzing for RTL research platform

Rust 2 Updated May 12, 2022

HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware

Verilog 4 1 Updated Jul 24, 2024

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Assembly 2,281 689 Updated Nov 12, 2024

Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)

Scala 111 7 Updated Aug 30, 2024

人人都能用英语

TypeScript 25,123 3,778 Updated Nov 14, 2024

VeeR EL2 Core

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Revizor - a fuzzer to search for microarchitectural leaks in CPUs

Python 114 34 Updated Nov 4, 2024

Circuit IR Compilers and Tools

C++ 1,674 298 Updated Nov 14, 2024

Open-source high-performance RISC-V processor

Scala 4,841 663 Updated Nov 14, 2024

mor1kx - an OpenRISC 1000 processor IP core

Verilog 495 147 Updated Oct 13, 2024

关于RISC-V你所需要知道的一切

542 66 Updated Apr 1, 2023

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,144 755 Updated Jun 27, 2024

RISC-V Cores, SoC platforms and SoCs

837 204 Updated Mar 26, 2021

RISC-V Instruction Set Manual

TeX 3,688 644 Updated Nov 14, 2024

Project Repo for the Simulator Independent Coverage Research

C++ 16 1 Updated Feb 28, 2023

A command-line benchmarking tool

Rust 22,192 357 Updated Nov 13, 2024

AutoGPT is the vision of accessible AI for everyone, to use and to build on. Our mission is to provide the tools, so that you can focus on what matters.

Python 168,318 44,399 Updated Nov 14, 2024

rfuzz: coverage-directed fuzzing for RTL research platform

Rust 98 12 Updated May 12, 2022
Verilog 74 18 Updated May 27, 2024