Merge branch 'master' of https://github.com/jamesbowman/swapforth

esp8266/uart_register.h

@@ -0,0 +1,128 @@
+//Generated at 2012-07-03 18:44:06
+/*
+ * Copyright (c) 2010 - 2011 Espressif System
+ *
+ */
+
+#ifndef UART_REGISTER_H_INCLUDED
+#define UART_REGISTER_H_INCLUDED
+#define REG_UART_BASE( i ) (0x60000000+(i)*0xf00)
+//version value:32'h062000
+
+#define UART_FIFO( i ) (REG_UART_BASE( i ) + 0x0)
+#define UART_RXFIFO_RD_BYTE 0x000000FF
+#define UART_RXFIFO_RD_BYTE_S 0
+
+#define UART_INT_RAW( i ) (REG_UART_BASE( i ) + 0x4)
+#define UART_RXFIFO_TOUT_INT_RAW (BIT(8))
+#define UART_BRK_DET_INT_RAW (BIT(7))
+#define UART_CTS_CHG_INT_RAW (BIT(6))
+#define UART_DSR_CHG_INT_RAW (BIT(5))
+#define UART_RXFIFO_OVF_INT_RAW (BIT(4))
+#define UART_FRM_ERR_INT_RAW (BIT(3))
+#define UART_PARITY_ERR_INT_RAW (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1))
+#define UART_RXFIFO_FULL_INT_RAW (BIT(0))
+
+#define UART_INT_ST( i ) (REG_UART_BASE( i ) + 0x8)
+#define UART_RXFIFO_TOUT_INT_ST (BIT(8))
+#define UART_BRK_DET_INT_ST (BIT(7))
+#define UART_CTS_CHG_INT_ST (BIT(6))
+#define UART_DSR_CHG_INT_ST (BIT(5))
+#define UART_RXFIFO_OVF_INT_ST (BIT(4))
+#define UART_FRM_ERR_INT_ST (BIT(3))
+#define UART_PARITY_ERR_INT_ST (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_ST (BIT(1))
+#define UART_RXFIFO_FULL_INT_ST (BIT(0))
+
+#define UART_INT_ENA( i ) (REG_UART_BASE( i ) + 0xC)
+#define UART_RXFIFO_TOUT_INT_ENA (BIT(8))
+#define UART_BRK_DET_INT_ENA (BIT(7))
+#define UART_CTS_CHG_INT_ENA (BIT(6))
+#define UART_DSR_CHG_INT_ENA (BIT(5))
+#define UART_RXFIFO_OVF_INT_ENA (BIT(4))
+#define UART_FRM_ERR_INT_ENA (BIT(3))
+#define UART_PARITY_ERR_INT_ENA (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1))
+#define UART_RXFIFO_FULL_INT_ENA (BIT(0))
+
+#define UART_INT_CLR( i ) (REG_UART_BASE( i ) + 0x10)
+#define UART_RXFIFO_TOUT_INT_CLR (BIT(8))
+#define UART_BRK_DET_INT_CLR (BIT(7))
+#define UART_CTS_CHG_INT_CLR (BIT(6))
+#define UART_DSR_CHG_INT_CLR (BIT(5))
+#define UART_RXFIFO_OVF_INT_CLR (BIT(4))
+#define UART_FRM_ERR_INT_CLR (BIT(3))
+#define UART_PARITY_ERR_INT_CLR (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1))
+#define UART_RXFIFO_FULL_INT_CLR (BIT(0))
+
+#define UART_CLKDIV( i ) (REG_UART_BASE( i ) + 0x14)
+#define UART_CLKDIV_CNT 0x000FFFFF
+#define UART_CLKDIV_S 0
+
+#define UART_AUTOBAUD( i ) (REG_UART_BASE( i ) + 0x18)
+#define UART_GLITCH_FILT 0x000000FF
+#define UART_GLITCH_FILT_S 8
+#define UART_AUTOBAUD_EN (BIT(0))
+
+#define UART_STATUS( i ) (REG_UART_BASE( i ) + 0x1C)
+#define UART_TXD (BIT(31))
+#define UART_RTSN (BIT(30))
+#define UART_DTRN (BIT(29))
+#define UART_TXFIFO_CNT 0x000000FF
+#define UART_TXFIFO_CNT_S 16
+#define UART_RXD (BIT(15))
+#define UART_CTSN (BIT(14))
+#define UART_DSRN (BIT(13))
+#define UART_RXFIFO_CNT 0x000000FF
+#define UART_RXFIFO_CNT_S 0
+
+#define UART_CONF0( i ) (REG_UART_BASE( i ) + 0x20)
+#define UART_TXFIFO_RST (BIT(18))
+#define UART_RXFIFO_RST (BIT(17))
+#define UART_IRDA_EN (BIT(16))
+#define UART_TX_FLOW_EN (BIT(15))
+#define UART_LOOPBACK (BIT(14))
+#define UART_IRDA_RX_INV (BIT(13))
+#define UART_IRDA_TX_INV (BIT(12))
+#define UART_IRDA_WCTL (BIT(11))
+#define UART_IRDA_TX_EN (BIT(10))
+#define UART_IRDA_DPLX (BIT(9))
+#define UART_TXD_BRK (BIT(8))
+#define UART_SW_DTR (BIT(7))
+#define UART_SW_RTS (BIT(6))
+#define UART_STOP_BIT_NUM 0x00000003
+#define UART_STOP_BIT_NUM_S 4
+#define UART_BIT_NUM 0x00000003
+#define UART_BIT_NUM_S 2
+#define UART_PARITY_EN (BIT(1))
+#define UART_PARITY (BIT(0))
+
+#define UART_CONF1( i ) (REG_UART_BASE( i ) + 0x24)
+#define UART_RX_TOUT_EN (BIT(31))
+#define UART_RX_TOUT_THRHD 0x0000007F
+#define UART_RX_TOUT_THRHD_S 24
+#define UART_RX_FLOW_EN (BIT(23))
+#define UART_RX_FLOW_THRHD 0x0000007F
+#define UART_RX_FLOW_THRHD_S 16
+#define UART_TXFIFO_EMPTY_THRHD 0x0000007F
+#define UART_TXFIFO_EMPTY_THRHD_S 8
+#define UART_RXFIFO_FULL_THRHD 0x0000007F
+#define UART_RXFIFO_FULL_THRHD_S 0
+
+#define UART_LOWPULSE( i ) (REG_UART_BASE( i ) + 0x28)
+#define UART_LOWPULSE_MIN_CNT 0x000FFFFF
+#define UART_LOWPULSE_MIN_CNT_S 0
+
+#define UART_HIGHPULSE( i ) (REG_UART_BASE( i ) + 0x2C)
+#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF
+#define UART_HIGHPULSE_MIN_CNT_S 0
+
+#define UART_PULSE_NUM( i ) (REG_UART_BASE( i ) + 0x30)
+#define UART_PULSE_NUM_CNT 0x0003FF
+#define UART_PULSE_NUM_CNT_S 0
+
+#define UART_DATE( i ) (REG_UART_BASE( i ) + 0x78)
+#define UART_ID( i ) (REG_UART_BASE( i ) + 0x7C)
+#endif // UART_REGISTER_H_INCLUDED

j1a/nandland-go/.gitignore

@@ -0,0 +1,3 @@
+*.blif
+*.txt
+*.ex

j1a/nandland-go/Makefile

@@ -0,0 +1,56 @@
+VERILOGS = j1a.v uart.v ../verilog/j1.v ../verilog/stack2.v
+
+VERILOGS8k = j1a8k.v uart.v ../verilog/j1.v ../verilog/stack2.v
+
+VERILOGS8k4 = j4a.v uart.v ../verilog/j1.v ../verilog/stack2.v ../verilog/j4.v ../verilog/stack2pipe4.v ../verilog/greycount.v
+
+SUBDIRS = ..
+
+all: $(SUBDIRS) j1a.bin
+
+j1a.bin: $(VERILOGS) j1a.pcf Makefile ../build/ram.v
+ yosys -q -p "synth_ice40 -top top -abc2 -blif j1a.blif" $(VERILOGS)
+ arachne-pnr -P vq100 -p j1a.pcf j1a.blif -o j1a.txt
+ #skipped:# icebox_explain j1a.txt > j1a.ex
+ icepack j1a.txt j1a0.bin
+ icemulti -p0 j1a0.bin > j1a.bin && rm j1a0.bin
+
+j1a8k.bin: $(VERILOGS8k) j1a8k.pcf Makefile ../build/ram.v
+ yosys -q -p "synth_ice40 -top top -abc2 -blif j1a8k.blif" $(VERILOGS8k)
+ arachne-pnr -d 8k -p j1a8k.pcf j1a8k.blif -o j1a8k.txt
+ #skipped:# icebox_explain j1a8k.txt > j1a8k.ex
+ icepack j1a8k.txt j1a8k0.bin
+ icemulti -p0 j1a8k0.bin > j1a8k.bin && rm j1a8k0.bin
+
+j4a.bin: $(VERILOGS8k4) j1a8k.pcf Makefile ../build/ram.v
+ yosys -q -p "synth_ice40 -top top -abc2 -blif j4a.blif" $(VERILOGS8k4)
+ arachne-pnr -d 8k -p j1a8k.pcf j4a.blif -o j4a.txt
+ #skipped:# icebox_explain j4a.txt > j4a.ex
+ icepack j4a.txt j4a0.bin
+ icemulti -p0 j4a0.bin > j4a.bin && rm j4a0.bin
+
+j1a8k: j1a8k.bin
+ sudo iceprog j1a8k.bin
+
+j1a: j1a.bin
+ sudo iceprog j1a.bin
+
+j4a: j4a.bin
+ sudo iceprog j4a.bin
+
+
+$(SUBDIRS):
+ $(MAKE) -C $@
+
+clean:
+ rm -f j1a.blif j1a.txt j1a.bin
+ rm -f j1a8k.blif j1a8k.txt j1a8k.bin
+ rm -f j1a.blif j4a.txt j4a.bin
+
+.PHONY: subdirs
+.PHONY: subdirs $(SUBDIRS)
+.PHONY: clean
+.PHONY: j1a8k
+.PHONY: j1a
+.PHONY: j4a
+

j1a/nandland-go/findserial

@@ -0,0 +1,6 @@
+#!/bin/sh
+for D in /dev/ttyUSB?
+do
+ udevadm info -a -n $D|grep 'ATTRS{idProduct}=="6010"'>/dev/null && echo $D
+done | tail -1
+true

j1a/nandland-go/go

@@ -0,0 +1,4 @@
+set -e
+make
+iceprog j1a.bin
+# PYTHONPATH=../..//shell:$PYTHONPATH python ../shell.py -h `./findserial` -p .. -p ../../common -p ../../anstests swapforth.fs debug.fs # spi2.fs

j1a/nandland-go/j1a.pcf

@@ -0,0 +1,18 @@
+set_io TXD 74
+set_io RXD 73
+set_io CLK 15
+
+set_io o_Segment1_A 3
+set_io o_Segment1_B 4
+set_io o_Segment1_C 93
+set_io o_Segment1_D 91
+set_io o_Segment1_E 90
+set_io o_Segment1_F 1
+set_io o_Segment1_G 2
+set_io o_Segment2_A 100
+set_io o_Segment2_B 99
+set_io o_Segment2_C 97
+set_io o_Segment2_D 95
+set_io o_Segment2_E 94
+set_io o_Segment2_F 8
+set_io o_Segment2_G 96