Modifications to the wb_interface branch The goal is to add the simple WB master interface to the J1b processor. Only simple transfers are needed.

In fact it may be an additional block added on a higher level, which offers two address spaces - One which is used to map a part of WB address space to the J1b I/O pace and the second one which allows controlling of the interface. In particular this "control" space should include the "page" registers used to select the part of the WB address space to be mapped in the "data" window. The WB part of the controller shoud be organized as below:

-- Here we have the WB ports
-- The clock and reset are comming from AXI!
wb_clk_o      : out std_logic;
wb_rst_o      : out std_logic;
-- master_ipb_out - flattened due to Vivado inability to handle user types
-- in BD
wb_addr_o     : out std_logic_vector(31 downto 0);
wb_dat_o      : out std_logic_vector(31 downto 0);
wb_we_o       : out std_logic;
wb_sel_o      : out std_logic_vector(3 downto 0);
wb_stb_o      : out std_logic;
wb_cyc_o      : out std_logic;
-- master_ipb_in -  flattened due to Vivado inability to handle user types
-- in BD
wb_dat_i      : in  std_logic_vector(31 downto 0);
wb_err_i      : in  std_logic;  -- Not used in figure 1-2 in specification!
wb_ack_i      : in  std_logic

The J1 part... (To be completed)

It is enough to define the "cold" word, which will be started instead of the interpreter loop.