Merge pull request jamesbowman#84 from RGD2/verilator-fixes-2023-09-w…

…ith-pyenv-python Verilator fixes with pyenv python
wzab · Sep 29, 2023 · 0c520f0 · 0c520f0
2 parents 8dbff77 + c4f1116
commit 0c520f0
Show file tree

Hide file tree

Showing 3 changed files with 6 additions and 4 deletions.
diff --git a/j1a/.python-version b/j1a/.python-version
@@ -0,0 +1 @@
+2.7.18
diff --git a/j1a/verilator/j1a.v b/j1a/verilator/j1a.v
@@ -19,7 +19,7 @@ module j1a(input wire clk,
  /* verilator lint_off UNUSED */
  wire [12:0] code_addr;
  /* verilator lint_on UNUSED */
- wire [15:0] insn;
+ reg [15:0] insn;
 
  reg [15:0] ram_prog[0:4095] /* verilator public_flat */;
  always @(posedge clk) begin
@@ -57,8 +57,8 @@ module j1a(input wire clk,
 
  // ###### UART ##########################################
 
- wire uart0_wr = io_wr_ & io_addr_[12];
- wire uart0_rd = io_rd_ & io_addr_[12];
+ assign uart0_wr = io_wr_ & io_addr_[12];
+ assign uart0_rd = io_rd_ & io_addr_[12];
  assign uart_w = dout_[7:0];
 
  // always @(posedge clk) begin

diff --git a/j1a/verilator/shell.py b/j1a/verilator/shell.py
@@ -6,7 +6,8 @@
 import struct
 import os
 
-sys.path.append("build/lib/python/")
+import site
+site.addsitedir("build/lib/python/")
 import vsimj1a
 
 sys.path.append("../../shell")