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How to Handle conv + bias in conv_3x3 for input(int8) * weight(int8) + bias(int32)?
#122
opened Jul 30, 2024 by
Haleski47
Applications hang indefinitely on Verilator when size of data cache is different than 0
#121
opened Jan 4, 2024 by
maheshejs
Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model
#118
opened Nov 28, 2023 by
AnjaliVerma1314
'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8
#112
opened Jul 3, 2023 by
ParkerJones567
Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core
#111
opened May 5, 2023 by
Nikhil-311293
narrowing instructions are never popped from the instruction queue
#103
opened Aug 11, 2022 by
moimfeld
Wrong result generated by multiply unit (probably control logic related)
#101
opened Aug 9, 2022 by
moimfeld
Error in Synthesizing the vicuna on Genesys2 board
question
Further information is requested
#91
opened Jul 7, 2022 by
Nikhil-311293
Illegal configuration created by config.mk
bug
Something isn't working
#89
opened Jun 27, 2022 by
moimfeld
Rare infinite stall triggered by a specific delay constellation during memory transactions
bug
Something isn't working
#85
opened Jun 15, 2022 by
moimfeld
Tail-agnostic policy violation for mask instruction
bug
Something isn't working
#79
opened Jun 9, 2022 by
moimfeld
vzext.vf2 instruction execution problem
bug
Something isn't working
#75
opened Jun 7, 2022 by
moimfeld
C code simulation using Verilator
question
Further information is requested
#66
opened May 28, 2022 by
kuoyaoming93
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