Wrong operand for vwmacc(u|us|su).vx

[moimfeld]

Hi @michael-platzer

A vector widening multiply accumulate instruction does a SEW * SEW multiplication and adds the product to a 2*SEW value. The result will have a width of 2*SEW.

Issue

If I understand the execution of vwmacc(u|us|su) instructions in Vicuna correctly, both multiplicands are first sign- or zero-extended to 2*SEW. After that the multiplication and the addition are all done on values with a 2*SEW width. In general this approach is correct, but for the vector-scalar version of these instruction there is an issue with the sign/zero-extension. In fact, no extension is done for the scalar source operand, instead a 2*SEW value is directly taken from the scalar source operand.

In the screenshot below you can see such a "non-extended" scalar source operand. The values in the screenshot are mostly taken from the multiply unit. SEW=8 for the duration of this screenshot.

On the top left of the wave window one can see the value that is passed to Vicuna as the source operand for the vwmacc(u|us|su).vx instructions (rs1=0x3784F1C6). At the yellow cursor one can see that the op1 for the multiply unit is 0xF1C6_F1C6_F1C6_F1C6_F1C6_F1C6_F1C6_F1C6 instead of 0xFFC6_FFC6_FFC6_FFC6_FFC6_FFC6_FFC6_FFC6 (i.e. the values are not zero/sign extended but instead directly a 2*SEW value is taken from the scalar source operand.

How to reproduce

You can reproduce this issue by running the cvxif_test_direct_issue_102 in the UVM verification environment.